1 /* 2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #if defined(CONFIG_E300) 18 #include <asm/e300.h> 19 #endif 20 21 /* MPC83xx cpu provide RCR register to do reset thing specially 22 */ 23 #define MPC83xx_RESET 24 25 /* System reset offset (PowerPC standard) 26 */ 27 #define EXC_OFF_SYS_RESET 0x0100 28 29 /* IMMRBAR - Internal Memory Register Base Address 30 */ 31 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 32 #define IMMRBAR 0x0000 /* Register offset to immr */ 33 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 34 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 35 36 /* LAWBAR - Local Access Window Base Address Register 37 */ 38 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 39 #define LBLAWAR0 0x0024 40 #define LBLAWBAR1 0x0028 41 #define LBLAWAR1 0x002C 42 #define LBLAWBAR2 0x0030 43 #define LBLAWAR2 0x0034 44 #define LBLAWBAR3 0x0038 45 #define LBLAWAR3 0x003C 46 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 47 48 /* SPRIDR - System Part and Revision ID Register 49 */ 50 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 51 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 52 53 #define SPR_8349E_REV10 0x80300100 54 #define SPR_8349_REV10 0x80310100 55 #define SPR_8347E_REV10_TBGA 0x80320100 56 #define SPR_8347_REV10_TBGA 0x80330100 57 #define SPR_8347E_REV10_PBGA 0x80340100 58 #define SPR_8347_REV10_PBGA 0x80350100 59 #define SPR_8343E_REV10 0x80360100 60 #define SPR_8343_REV10 0x80370100 61 62 #define SPR_8349E_REV11 0x80300101 63 #define SPR_8349_REV11 0x80310101 64 #define SPR_8347E_REV11_TBGA 0x80320101 65 #define SPR_8347_REV11_TBGA 0x80330101 66 #define SPR_8347E_REV11_PBGA 0x80340101 67 #define SPR_8347_REV11_PBGA 0x80350101 68 #define SPR_8343E_REV11 0x80360101 69 #define SPR_8343_REV11 0x80370101 70 71 #define SPR_8349E_REV31 0x80300300 72 #define SPR_8349_REV31 0x80310300 73 #define SPR_8347E_REV31_TBGA 0x80320300 74 #define SPR_8347_REV31_TBGA 0x80330300 75 #define SPR_8347E_REV31_PBGA 0x80340300 76 #define SPR_8347_REV31_PBGA 0x80350300 77 #define SPR_8343E_REV31 0x80360300 78 #define SPR_8343_REV31 0x80370300 79 80 #define SPR_8360E_REV10 0x80480010 81 #define SPR_8360_REV10 0x80490010 82 #define SPR_8360E_REV11 0x80480011 83 #define SPR_8360_REV11 0x80490011 84 #define SPR_8360E_REV12 0x80480012 85 #define SPR_8360_REV12 0x80490012 86 #define SPR_8360E_REV20 0x80480020 87 #define SPR_8360_REV20 0x80490020 88 89 #define SPR_8323E_REV10 0x80620010 90 #define SPR_8323_REV10 0x80630010 91 #define SPR_8321E_REV10 0x80660010 92 #define SPR_8321_REV10 0x80670010 93 #define SPR_8323E_REV11 0x80620011 94 #define SPR_8323_REV11 0x80630011 95 #define SPR_8321E_REV11 0x80660011 96 #define SPR_8321_REV11 0x80670011 97 98 #define SPR_8311_REV10 0x80B30010 99 #define SPR_8311E_REV10 0x80B20010 100 #define SPR_8313_REV10 0x80B10010 101 #define SPR_8313E_REV10 0x80B00010 102 103 /* SPCR - System Priority Configuration Register 104 */ 105 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 106 #define SPCR_PCIHPE_SHIFT (31-3) 107 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 108 #define SPCR_PCIPR_SHIFT (31-7) 109 #define SPCR_OPT 0x00800000 /* Optimize */ 110 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 111 #define SPCR_TBEN_SHIFT (31-9) 112 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 113 #define SPCR_COREPR_SHIFT (31-11) 114 115 #if defined(CONFIG_MPC834X) 116 /* SPCR bits - MPC8349 specific */ 117 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 118 #define SPCR_TSEC1DP_SHIFT (31-19) 119 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 120 #define SPCR_TSEC1BDP_SHIFT (31-21) 121 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 122 #define SPCR_TSEC1EP_SHIFT (31-23) 123 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 124 #define SPCR_TSEC2DP_SHIFT (31-27) 125 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 126 #define SPCR_TSEC2BDP_SHIFT (31-29) 127 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 128 #define SPCR_TSEC2EP_SHIFT (31-31) 129 130 #elif defined(CONFIG_MPC831X) 131 /* SPCR bits - MPC831x specific */ 132 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 133 #define SPCR_TSECDP_SHIFT (31-19) 134 #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ 135 #define SPCR_TSECEP_SHIFT (31-21) 136 #define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */ 137 #define SPCR_TSECBDP_SHIFT (31-23) 138 #endif 139 140 /* SICRL/H - System I/O Configuration Register Low/High 141 */ 142 #if defined(CONFIG_MPC834X) 143 /* SICRL bits - MPC8349 specific */ 144 #define SICRL_LDP_A 0x80000000 145 #define SICRL_USB1 0x40000000 146 #define SICRL_USB0 0x20000000 147 #define SICRL_UART 0x0C000000 148 #define SICRL_GPIO1_A 0x02000000 149 #define SICRL_GPIO1_B 0x01000000 150 #define SICRL_GPIO1_C 0x00800000 151 #define SICRL_GPIO1_D 0x00400000 152 #define SICRL_GPIO1_E 0x00200000 153 #define SICRL_GPIO1_F 0x00180000 154 #define SICRL_GPIO1_G 0x00040000 155 #define SICRL_GPIO1_H 0x00020000 156 #define SICRL_GPIO1_I 0x00010000 157 #define SICRL_GPIO1_J 0x00008000 158 #define SICRL_GPIO1_K 0x00004000 159 #define SICRL_GPIO1_L 0x00003000 160 161 /* SICRH bits - MPC8349 specific */ 162 #define SICRH_DDR 0x80000000 163 #define SICRH_TSEC1_A 0x10000000 164 #define SICRH_TSEC1_B 0x08000000 165 #define SICRH_TSEC1_C 0x04000000 166 #define SICRH_TSEC1_D 0x02000000 167 #define SICRH_TSEC1_E 0x01000000 168 #define SICRH_TSEC1_F 0x00800000 169 #define SICRH_TSEC2_A 0x00400000 170 #define SICRH_TSEC2_B 0x00200000 171 #define SICRH_TSEC2_C 0x00100000 172 #define SICRH_TSEC2_D 0x00080000 173 #define SICRH_TSEC2_E 0x00040000 174 #define SICRH_TSEC2_F 0x00020000 175 #define SICRH_TSEC2_G 0x00010000 176 #define SICRH_TSEC2_H 0x00008000 177 #define SICRH_GPIO2_A 0x00004000 178 #define SICRH_GPIO2_B 0x00002000 179 #define SICRH_GPIO2_C 0x00001000 180 #define SICRH_GPIO2_D 0x00000800 181 #define SICRH_GPIO2_E 0x00000400 182 #define SICRH_GPIO2_F 0x00000200 183 #define SICRH_GPIO2_G 0x00000180 184 #define SICRH_GPIO2_H 0x00000060 185 #define SICRH_TSOBI1 0x00000002 186 #define SICRH_TSOBI2 0x00000001 187 188 #elif defined(CONFIG_MPC8360) 189 /* SICRL bits - MPC8360 specific */ 190 #define SICRL_LDP_A 0xC0000000 191 #define SICRL_LCLK_1 0x10000000 192 #define SICRL_LCLK_2 0x08000000 193 #define SICRL_SRCID_A 0x03000000 194 #define SICRL_IRQ_CKSTP_A 0x00C00000 195 196 /* SICRH bits - MPC8360 specific */ 197 #define SICRH_DDR 0x80000000 198 #define SICRH_SECONDARY_DDR 0x40000000 199 #define SICRH_SDDROE 0x20000000 200 #define SICRH_IRQ3 0x10000000 201 #define SICRH_UC1EOBI 0x00000004 202 #define SICRH_UC2E1OBI 0x00000002 203 #define SICRH_UC2E2OBI 0x00000001 204 205 #elif defined(CONFIG_MPC832X) 206 /* SICRL bits - MPC832X specific */ 207 #define SICRL_LDP_LCS_A 0x80000000 208 #define SICRL_IRQ_CKS 0x20000000 209 #define SICRL_PCI_MSRC 0x10000000 210 #define SICRL_URT_CTPR 0x06000000 211 #define SICRL_IRQ_CTPR 0x00C00000 212 213 #elif defined(CONFIG_MPC831X) 214 /* SICRL bits - MPC831x specific */ 215 #define SICRL_LBC 0x30000000 216 #define SICRL_UART 0x0C000000 217 #define SICRL_SPI_A 0x03000000 218 #define SICRL_SPI_B 0x00C00000 219 #define SICRL_SPI_C 0x00300000 220 #define SICRL_SPI_D 0x000C0000 221 #define SICRL_USBDR 0x00000C00 222 #define SICRL_ETSEC1_A 0x0000000C 223 #define SICRL_ETSEC2_A 0x00000003 224 225 /* SICRH bits - MPC831x specific */ 226 #define SICRH_INTR_A 0x02000000 227 #define SICRH_INTR_B 0x00C00000 228 #define SICRH_IIC 0x00300000 229 #define SICRH_ETSEC2_B 0x000C0000 230 #define SICRH_ETSEC2_C 0x00030000 231 #define SICRH_ETSEC2_D 0x0000C000 232 #define SICRH_ETSEC2_E 0x00003000 233 #define SICRH_ETSEC2_F 0x00000C00 234 #define SICRH_ETSEC2_G 0x00000300 235 #define SICRH_ETSEC1_B 0x00000080 236 #define SICRH_ETSEC1_C 0x00000060 237 #define SICRH_GTX1_DLY 0x00000008 238 #define SICRH_GTX2_DLY 0x00000004 239 #define SICRH_TSOBI1 0x00000002 240 #define SICRH_TSOBI2 0x00000001 241 242 #endif 243 244 /* SWCRR - System Watchdog Control Register 245 */ 246 #define SWCRR 0x0204 /* Register offset to immr */ 247 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 248 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 249 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 250 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 251 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 252 253 /* SWCNR - System Watchdog Counter Register 254 */ 255 #define SWCNR 0x0208 /* Register offset to immr */ 256 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 257 #define SWCNR_RES ~(SWCNR_SWCN) 258 259 /* SWSRR - System Watchdog Service Register 260 */ 261 #define SWSRR 0x020E /* Register offset to immr */ 262 263 /* ACR - Arbiter Configuration Register 264 */ 265 #define ACR_COREDIS 0x10000000 /* Core disable */ 266 #define ACR_COREDIS_SHIFT (31-7) 267 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 268 #define ACR_PIPE_DEP_SHIFT (31-15) 269 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 270 #define ACR_PCI_RPTCNT_SHIFT (31-19) 271 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 272 #define ACR_RPTCNT_SHIFT (31-23) 273 #define ACR_APARK 0x00000030 /* Address parking */ 274 #define ACR_APARK_SHIFT (31-27) 275 #define ACR_PARKM 0x0000000F /* Parking master */ 276 #define ACR_PARKM_SHIFT (31-31) 277 278 /* ATR - Arbiter Timers Register 279 */ 280 #define ATR_DTO 0x00FF0000 /* Data time out */ 281 #define ATR_ATO 0x000000FF /* Address time out */ 282 283 /* AER - Arbiter Event Register 284 */ 285 #define AER_ETEA 0x00000020 /* Transfer error */ 286 #define AER_RES 0x00000010 /* Reserved transfer type */ 287 #define AER_ECW 0x00000008 /* External control word transfer type */ 288 #define AER_AO 0x00000004 /* Address Only transfer type */ 289 #define AER_DTO 0x00000002 /* Data time out */ 290 #define AER_ATO 0x00000001 /* Address time out */ 291 292 /* AEATR - Arbiter Event Address Register 293 */ 294 #define AEATR_EVENT 0x07000000 /* Event type */ 295 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 296 #define AEATR_TBST 0x00000800 /* Transfer burst */ 297 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 298 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 299 300 /* HRCWL - Hard Reset Configuration Word Low 301 */ 302 #define HRCWL_LBIUCM 0x80000000 303 #define HRCWL_LBIUCM_SHIFT 31 304 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 305 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 306 307 #define HRCWL_DDRCM 0x40000000 308 #define HRCWL_DDRCM_SHIFT 30 309 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 310 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 311 312 #define HRCWL_SPMF 0x0f000000 313 #define HRCWL_SPMF_SHIFT 24 314 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 315 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 316 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 317 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 318 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 319 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 320 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 321 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 322 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 323 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 324 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 325 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 326 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 327 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 328 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 329 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 330 331 #define HRCWL_VCO_BYPASS 0x00000000 332 #define HRCWL_VCO_1X2 0x00000000 333 #define HRCWL_VCO_1X4 0x00200000 334 #define HRCWL_VCO_1X8 0x00400000 335 336 #define HRCWL_COREPLL 0x007F0000 337 #define HRCWL_COREPLL_SHIFT 16 338 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 339 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 340 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 341 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 342 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 343 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 344 345 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 346 #define HRCWL_CEVCOD 0x000000C0 347 #define HRCWL_CEVCOD_SHIFT 6 348 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 349 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 350 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 351 352 #define HRCWL_CEPDF 0x00000020 353 #define HRCWL_CEPDF_SHIFT 5 354 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 355 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 356 357 #define HRCWL_CEPMF 0x0000001F 358 #define HRCWL_CEPMF_SHIFT 0 359 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 360 #define HRCWL_CE_TO_PLL_1X2 0x00000002 361 #define HRCWL_CE_TO_PLL_1X3 0x00000003 362 #define HRCWL_CE_TO_PLL_1X4 0x00000004 363 #define HRCWL_CE_TO_PLL_1X5 0x00000005 364 #define HRCWL_CE_TO_PLL_1X6 0x00000006 365 #define HRCWL_CE_TO_PLL_1X7 0x00000007 366 #define HRCWL_CE_TO_PLL_1X8 0x00000008 367 #define HRCWL_CE_TO_PLL_1X9 0x00000009 368 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 369 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 370 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 371 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 372 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 373 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 374 #define HRCWL_CE_TO_PLL_1X16 0x00000010 375 #define HRCWL_CE_TO_PLL_1X17 0x00000011 376 #define HRCWL_CE_TO_PLL_1X18 0x00000012 377 #define HRCWL_CE_TO_PLL_1X19 0x00000013 378 #define HRCWL_CE_TO_PLL_1X20 0x00000014 379 #define HRCWL_CE_TO_PLL_1X21 0x00000015 380 #define HRCWL_CE_TO_PLL_1X22 0x00000016 381 #define HRCWL_CE_TO_PLL_1X23 0x00000017 382 #define HRCWL_CE_TO_PLL_1X24 0x00000018 383 #define HRCWL_CE_TO_PLL_1X25 0x00000019 384 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 385 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 386 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 387 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 388 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 389 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 390 #endif 391 392 /* HRCWH - Hardware Reset Configuration Word High 393 */ 394 #define HRCWH_PCI_HOST 0x80000000 395 #define HRCWH_PCI_HOST_SHIFT 31 396 #define HRCWH_PCI_AGENT 0x00000000 397 398 #if defined(CONFIG_MPC834X) 399 #define HRCWH_32_BIT_PCI 0x00000000 400 #define HRCWH_64_BIT_PCI 0x40000000 401 #endif 402 403 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 404 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 405 406 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 407 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 408 409 #if defined(CONFIG_MPC834X) 410 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 411 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 412 413 #elif defined(CONFIG_MPC8360) 414 #define HRCWH_PCICKDRV_DISABLE 0x00000000 415 #define HRCWH_PCICKDRV_ENABLE 0x10000000 416 #endif 417 418 #define HRCWH_CORE_DISABLE 0x08000000 419 #define HRCWH_CORE_ENABLE 0x00000000 420 421 #define HRCWH_FROM_0X00000100 0x00000000 422 #define HRCWH_FROM_0XFFF00100 0x04000000 423 424 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 425 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 426 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 427 428 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 429 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 430 431 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 432 #define HRCWH_ROM_LOC_PCI1 0x00100000 433 #if defined(CONFIG_MPC834X) 434 #define HRCWH_ROM_LOC_PCI2 0x00200000 435 #endif 436 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 437 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 438 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 439 440 #if defined(CONFIG_MPC831X) 441 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 442 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 443 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 444 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 445 446 #define HRCWH_RL_EXT_LEGACY 0x00000000 447 #define HRCWH_RL_EXT_NAND 0x00040000 448 449 #define HRCWH_TSEC1M_IN_MII 0x00000000 450 #define HRCWH_TSEC1M_IN_RMII 0x00002000 451 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 452 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 453 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 454 455 #define HRCWH_TSEC2M_IN_MII 0x00000000 456 #define HRCWH_TSEC2M_IN_RMII 0x00000400 457 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 458 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 459 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 460 #endif 461 462 #if defined(CONFIG_MPC834X) 463 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 464 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 465 #define HRCWH_TSEC1M_IN_GMII 0x00008000 466 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 467 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 468 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 469 #define HRCWH_TSEC2M_IN_GMII 0x00002000 470 #define HRCWH_TSEC2M_IN_TBI 0x00003000 471 #endif 472 473 #if defined(CONFIG_MPC8360) 474 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 475 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 476 #endif 477 478 #define HRCWH_BIG_ENDIAN 0x00000000 479 #define HRCWH_LITTLE_ENDIAN 0x00000008 480 481 #define HRCWH_LALE_NORMAL 0x00000000 482 #define HRCWH_LALE_EARLY 0x00000004 483 484 #define HRCWH_LDP_SET 0x00000000 485 #define HRCWH_LDP_CLEAR 0x00000002 486 487 /* RSR - Reset Status Register 488 */ 489 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 490 #define RSR_RSTSRC_SHIFT 29 491 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 492 #define RSR_BSF_SHIFT 16 493 #define RSR_SWSR 0x00002000 /* software soft reset */ 494 #define RSR_SWSR_SHIFT 13 495 #define RSR_SWHR 0x00001000 /* software hard reset */ 496 #define RSR_SWHR_SHIFT 12 497 #define RSR_JHRS 0x00000200 /* jtag hreset */ 498 #define RSR_JHRS_SHIFT 9 499 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 500 #define RSR_JSRS_SHIFT 8 501 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 502 #define RSR_CSHR_SHIFT 4 503 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 504 #define RSR_SWRS_SHIFT 3 505 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 506 #define RSR_BMRS_SHIFT 2 507 #define RSR_SRS 0x00000002 /* soft reset status */ 508 #define RSR_SRS_SHIFT 1 509 #define RSR_HRS 0x00000001 /* hard reset status */ 510 #define RSR_HRS_SHIFT 0 511 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 512 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 513 RSR_BMRS | RSR_SRS | RSR_HRS) 514 /* RMR - Reset Mode Register 515 */ 516 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 517 #define RMR_CSRE_SHIFT 0 518 #define RMR_RES ~(RMR_CSRE) 519 520 /* RCR - Reset Control Register 521 */ 522 #define RCR_SWHR 0x00000002 /* software hard reset */ 523 #define RCR_SWSR 0x00000001 /* software soft reset */ 524 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 525 526 /* RCER - Reset Control Enable Register 527 */ 528 #define RCER_CRE 0x00000001 /* software hard reset */ 529 #define RCER_RES ~(RCER_CRE) 530 531 /* SPMR - System PLL Mode Register 532 */ 533 #define SPMR_LBIUCM 0x80000000 534 #define SPMR_DDRCM 0x40000000 535 #define SPMR_SPMF 0x0F000000 536 #define SPMR_CKID 0x00800000 537 #define SPMR_CKID_SHIFT 23 538 #define SPMR_COREPLL 0x007F0000 539 #define SPMR_CEVCOD 0x000000C0 540 #define SPMR_CEPDF 0x00000020 541 #define SPMR_CEPMF 0x0000001F 542 543 /* OCCR - Output Clock Control Register 544 */ 545 #define OCCR_PCICOE0 0x80000000 546 #define OCCR_PCICOE1 0x40000000 547 #define OCCR_PCICOE2 0x20000000 548 #define OCCR_PCICOE3 0x10000000 549 #define OCCR_PCICOE4 0x08000000 550 #define OCCR_PCICOE5 0x04000000 551 #define OCCR_PCICOE6 0x02000000 552 #define OCCR_PCICOE7 0x01000000 553 #define OCCR_PCICD0 0x00800000 554 #define OCCR_PCICD1 0x00400000 555 #define OCCR_PCICD2 0x00200000 556 #define OCCR_PCICD3 0x00100000 557 #define OCCR_PCICD4 0x00080000 558 #define OCCR_PCICD5 0x00040000 559 #define OCCR_PCICD6 0x00020000 560 #define OCCR_PCICD7 0x00010000 561 #define OCCR_PCI1CR 0x00000002 562 #define OCCR_PCI2CR 0x00000001 563 #define OCCR_PCICR OCCR_PCI1CR 564 565 /* SCCR - System Clock Control Register 566 */ 567 #define SCCR_ENCCM 0x03000000 568 #define SCCR_ENCCM_SHIFT 24 569 #define SCCR_ENCCM_0 0x00000000 570 #define SCCR_ENCCM_1 0x01000000 571 #define SCCR_ENCCM_2 0x02000000 572 #define SCCR_ENCCM_3 0x03000000 573 574 #define SCCR_PCICM 0x00010000 575 #define SCCR_PCICM_SHIFT 16 576 577 /* SCCR bits - MPC8349 specific */ 578 #ifdef CONFIG_MPC834X 579 #define SCCR_TSEC1CM 0xc0000000 580 #define SCCR_TSEC1CM_SHIFT 30 581 #define SCCR_TSEC1CM_0 0x00000000 582 #define SCCR_TSEC1CM_1 0x40000000 583 #define SCCR_TSEC1CM_2 0x80000000 584 #define SCCR_TSEC1CM_3 0xC0000000 585 586 #define SCCR_TSEC2CM 0x30000000 587 #define SCCR_TSEC2CM_SHIFT 28 588 #define SCCR_TSEC2CM_0 0x00000000 589 #define SCCR_TSEC2CM_1 0x10000000 590 #define SCCR_TSEC2CM_2 0x20000000 591 #define SCCR_TSEC2CM_3 0x30000000 592 593 #elif defined(CONFIG_MPC831X) 594 /* TSEC1 bits are for TSEC2 as well */ 595 #define SCCR_TSEC1CM 0xc0000000 596 #define SCCR_TSEC1CM_SHIFT 30 597 #define SCCR_TSEC1CM_1 0x40000000 598 #define SCCR_TSEC1CM_2 0x80000000 599 #define SCCR_TSEC1CM_3 0xC0000000 600 601 #define SCCR_TSEC1ON 0x20000000 602 #define SCCR_TSEC2ON 0x10000000 603 604 #endif 605 606 #define SCCR_USBMPHCM 0x00c00000 607 #define SCCR_USBMPHCM_SHIFT 22 608 #define SCCR_USBDRCM 0x00300000 609 #define SCCR_USBDRCM_SHIFT 20 610 611 #define SCCR_USBCM_0 0x00000000 612 #define SCCR_USBCM_1 0x00500000 613 #define SCCR_USBCM_2 0x00A00000 614 #define SCCR_USBCM_3 0x00F00000 615 616 /* CSn_BDNS - Chip Select memory Bounds Register 617 */ 618 #define CSBNDS_SA 0x00FF0000 619 #define CSBNDS_SA_SHIFT 8 620 #define CSBNDS_EA 0x000000FF 621 #define CSBNDS_EA_SHIFT 24 622 623 /* CSn_CONFIG - Chip Select Configuration Register 624 */ 625 #define CSCONFIG_EN 0x80000000 626 #define CSCONFIG_AP 0x00800000 627 #define CSCONFIG_ROW_BIT 0x00000700 628 #define CSCONFIG_ROW_BIT_12 0x00000000 629 #define CSCONFIG_ROW_BIT_13 0x00000100 630 #define CSCONFIG_ROW_BIT_14 0x00000200 631 #define CSCONFIG_COL_BIT 0x00000007 632 #define CSCONFIG_COL_BIT_8 0x00000000 633 #define CSCONFIG_COL_BIT_9 0x00000001 634 #define CSCONFIG_COL_BIT_10 0x00000002 635 #define CSCONFIG_COL_BIT_11 0x00000003 636 637 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 638 */ 639 #define TIMING_CFG0_RWT 0xC0000000 640 #define TIMING_CFG0_RWT_SHIFT 30 641 #define TIMING_CFG0_WRT 0x30000000 642 #define TIMING_CFG0_WRT_SHIFT 28 643 #define TIMING_CFG0_RRT 0x0C000000 644 #define TIMING_CFG0_RRT_SHIFT 26 645 #define TIMING_CFG0_WWT 0x03000000 646 #define TIMING_CFG0_WWT_SHIFT 24 647 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 648 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 649 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 650 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 651 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 652 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 653 #define TIMING_CFG0_MRS_CYC 0x00000F00 654 #define TIMING_CFG0_MRS_CYC_SHIFT 0 655 656 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 657 */ 658 #define TIMING_CFG1_PRETOACT 0x70000000 659 #define TIMING_CFG1_PRETOACT_SHIFT 28 660 #define TIMING_CFG1_ACTTOPRE 0x0F000000 661 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 662 #define TIMING_CFG1_ACTTORW 0x00700000 663 #define TIMING_CFG1_ACTTORW_SHIFT 20 664 #define TIMING_CFG1_CASLAT 0x00070000 665 #define TIMING_CFG1_CASLAT_SHIFT 16 666 #define TIMING_CFG1_REFREC 0x0000F000 667 #define TIMING_CFG1_REFREC_SHIFT 12 668 #define TIMING_CFG1_WRREC 0x00000700 669 #define TIMING_CFG1_WRREC_SHIFT 8 670 #define TIMING_CFG1_ACTTOACT 0x00000070 671 #define TIMING_CFG1_ACTTOACT_SHIFT 4 672 #define TIMING_CFG1_WRTORD 0x00000007 673 #define TIMING_CFG1_WRTORD_SHIFT 0 674 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 675 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 676 677 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 678 */ 679 #define TIMING_CFG2_CPO 0x0F800000 680 #define TIMING_CFG2_CPO_SHIFT 23 681 #define TIMING_CFG2_ACSM 0x00080000 682 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 683 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 684 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 685 686 #define TIMING_CFG2_ADD_LAT 0x70000000 687 #define TIMING_CFG2_ADD_LAT_SHIFT 28 688 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 689 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 690 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 691 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 692 #define TIMING_CFG2_CKE_PLS 0x000001C0 693 #define TIMING_CFG2_CKE_PLS_SHIFT 6 694 #define TIMING_CFG2_FOUR_ACT 0x0000003F 695 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 696 697 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 698 */ 699 #define SDRAM_CFG_MEM_EN 0x80000000 700 #define SDRAM_CFG_SREN 0x40000000 701 #define SDRAM_CFG_ECC_EN 0x20000000 702 #define SDRAM_CFG_RD_EN 0x10000000 703 #define SDRAM_CFG_SDRAM_TYPE 0x03000000 704 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 705 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 706 #define SDRAM_CFG_DYN_PWR 0x00200000 707 #define SDRAM_CFG_32_BE 0x00080000 708 #define SDRAM_CFG_8_BE 0x00040000 709 #define SDRAM_CFG_NCAP 0x00020000 710 #define SDRAM_CFG_2T_EN 0x00008000 711 #define SDRAM_CFG_BI 0x00000001 712 713 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 714 */ 715 #define SDRAM_MODE_ESD 0xFFFF0000 716 #define SDRAM_MODE_ESD_SHIFT 16 717 #define SDRAM_MODE_SD 0x0000FFFF 718 #define SDRAM_MODE_SD_SHIFT 0 719 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 720 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 721 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 722 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 723 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 724 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 725 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 726 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 727 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 728 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 729 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 730 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 731 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 732 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 733 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 734 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 735 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 736 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 737 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 738 739 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 740 */ 741 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 742 #define SDRAM_INTERVAL_REFINT_SHIFT 16 743 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 744 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 745 746 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 747 */ 748 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 749 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 750 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 751 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 752 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 753 754 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 755 */ 756 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 757 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 758 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 759 #define ECC_ERR_INJECT_EEIM_SHIFT 0 760 761 /* CAPTURE_ECC - Memory data path read capture ECC 762 */ 763 #define CAPTURE_ECC_ECE (0xff000000>>24) 764 #define CAPTURE_ECC_ECE_SHIFT 0 765 766 /* ERR_DETECT - Memory error detect 767 */ 768 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 769 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 770 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 771 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 772 773 /* ERR_DISABLE - Memory error disable 774 */ 775 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 776 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 777 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 778 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 779 ECC_ERROR_DISABLE_MBED) 780 /* ERR_INT_EN - Memory error interrupt enable 781 */ 782 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 783 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 784 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 785 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 786 ECC_ERR_INT_EN_MSEE) 787 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 788 */ 789 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 790 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 791 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 792 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 793 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 794 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 795 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 796 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 797 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 798 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 799 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 800 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 801 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 802 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 803 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 804 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 805 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 806 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 807 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 808 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 809 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 810 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 811 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 812 #define ECC_CAPT_ATTR_TTYP_READ 0x2 813 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 814 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 815 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 816 817 /* ERR_SBE - Single bit ECC memory error management 818 */ 819 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 820 #define ECC_ERROR_MAN_SBET_SHIFT 16 821 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 822 #define ECC_ERROR_MAN_SBEC_SHIFT 0 823 824 /* BR - Base Registers 825 */ 826 #define BR0 0x5000 /* Register offset to immr */ 827 #define BR1 0x5008 828 #define BR2 0x5010 829 #define BR3 0x5018 830 #define BR4 0x5020 831 #define BR5 0x5028 832 #define BR6 0x5030 833 #define BR7 0x5038 834 835 #define BR_BA 0xFFFF8000 836 #define BR_BA_SHIFT 15 837 #define BR_PS 0x00001800 838 #define BR_PS_SHIFT 11 839 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 840 #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 841 #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 842 #define BR_DECC 0x00000600 843 #define BR_DECC_SHIFT 9 844 #define BR_DECC_OFF 0x00000000 845 #define BR_DECC_CHK 0x00000200 846 #define BR_DECC_CHK_GEN 0x00000400 847 #define BR_WP 0x00000100 848 #define BR_WP_SHIFT 8 849 #define BR_MSEL 0x000000E0 850 #define BR_MSEL_SHIFT 5 851 #define BR_MS_GPCM 0x00000000 /* GPCM */ 852 #define BR_MS_FCM 0x00000020 /* FCM */ 853 #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 854 #define BR_MS_UPMA 0x00000080 /* UPMA */ 855 #define BR_MS_UPMB 0x000000A0 /* UPMB */ 856 #define BR_MS_UPMC 0x000000C0 /* UPMC */ 857 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 858 #define BR_ATOM 0x0000000C 859 #define BR_ATOM_SHIFT 2 860 #endif 861 #define BR_V 0x00000001 862 #define BR_V_SHIFT 0 863 864 #if defined(CONFIG_MPC834X) 865 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 866 #elif defined(CONFIG_MPC8360) 867 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 868 #endif 869 870 /* OR - Option Registers 871 */ 872 #define OR0 0x5004 /* Register offset to immr */ 873 #define OR1 0x500C 874 #define OR2 0x5014 875 #define OR3 0x501C 876 #define OR4 0x5024 877 #define OR5 0x502C 878 #define OR6 0x5034 879 #define OR7 0x503C 880 881 #define OR_GPCM_AM 0xFFFF8000 882 #define OR_GPCM_AM_SHIFT 15 883 #define OR_GPCM_BCTLD 0x00001000 884 #define OR_GPCM_BCTLD_SHIFT 12 885 #define OR_GPCM_CSNT 0x00000800 886 #define OR_GPCM_CSNT_SHIFT 11 887 #define OR_GPCM_ACS 0x00000600 888 #define OR_GPCM_ACS_SHIFT 9 889 #define OR_GPCM_ACS_0b10 0x00000400 890 #define OR_GPCM_ACS_0b11 0x00000600 891 #define OR_GPCM_XACS 0x00000100 892 #define OR_GPCM_XACS_SHIFT 8 893 #define OR_GPCM_SCY 0x000000F0 894 #define OR_GPCM_SCY_SHIFT 4 895 #define OR_GPCM_SCY_1 0x00000010 896 #define OR_GPCM_SCY_2 0x00000020 897 #define OR_GPCM_SCY_3 0x00000030 898 #define OR_GPCM_SCY_4 0x00000040 899 #define OR_GPCM_SCY_5 0x00000050 900 #define OR_GPCM_SCY_6 0x00000060 901 #define OR_GPCM_SCY_7 0x00000070 902 #define OR_GPCM_SCY_8 0x00000080 903 #define OR_GPCM_SCY_9 0x00000090 904 #define OR_GPCM_SCY_10 0x000000a0 905 #define OR_GPCM_SCY_11 0x000000b0 906 #define OR_GPCM_SCY_12 0x000000c0 907 #define OR_GPCM_SCY_13 0x000000d0 908 #define OR_GPCM_SCY_14 0x000000e0 909 #define OR_GPCM_SCY_15 0x000000f0 910 #define OR_GPCM_SETA 0x00000008 911 #define OR_GPCM_SETA_SHIFT 3 912 #define OR_GPCM_TRLX 0x00000004 913 #define OR_GPCM_TRLX_SHIFT 2 914 #define OR_GPCM_EHTR 0x00000002 915 #define OR_GPCM_EHTR_SHIFT 1 916 #define OR_GPCM_EAD 0x00000001 917 #define OR_GPCM_EAD_SHIFT 0 918 919 #define OR_FCM_AM 0xFFFF8000 920 #define OR_FCM_AM_SHIFT 15 921 #define OR_FCM_BCTLD 0x00001000 922 #define OR_FCM_BCTLD_SHIFT 12 923 #define OR_FCM_PGS 0x00000400 924 #define OR_FCM_PGS_SHIFT 10 925 #define OR_FCM_CSCT 0x00000200 926 #define OR_FCM_CSCT_SHIFT 9 927 #define OR_FCM_CST 0x00000100 928 #define OR_FCM_CST_SHIFT 8 929 #define OR_FCM_CHT 0x00000080 930 #define OR_FCM_CHT_SHIFT 7 931 #define OR_FCM_SCY 0x00000070 932 #define OR_FCM_SCY_SHIFT 4 933 #define OR_FCM_SCY_1 0x00000010 934 #define OR_FCM_SCY_2 0x00000020 935 #define OR_FCM_SCY_3 0x00000030 936 #define OR_FCM_SCY_4 0x00000040 937 #define OR_FCM_SCY_5 0x00000050 938 #define OR_FCM_SCY_6 0x00000060 939 #define OR_FCM_SCY_7 0x00000070 940 #define OR_FCM_RST 0x00000008 941 #define OR_FCM_RST_SHIFT 3 942 #define OR_FCM_TRLX 0x00000004 943 #define OR_FCM_TRLX_SHIFT 2 944 #define OR_FCM_EHTR 0x00000002 945 #define OR_FCM_EHTR_SHIFT 1 946 947 #define OR_UPM_AM 0xFFFF8000 948 #define OR_UPM_AM_SHIFT 15 949 #define OR_UPM_XAM 0x00006000 950 #define OR_UPM_XAM_SHIFT 13 951 #define OR_UPM_BCTLD 0x00001000 952 #define OR_UPM_BCTLD_SHIFT 12 953 #define OR_UPM_BI 0x00000100 954 #define OR_UPM_BI_SHIFT 8 955 #define OR_UPM_TRLX 0x00000004 956 #define OR_UPM_TRLX_SHIFT 2 957 #define OR_UPM_EHTR 0x00000002 958 #define OR_UPM_EHTR_SHIFT 1 959 #define OR_UPM_EAD 0x00000001 960 #define OR_UPM_EAD_SHIFT 0 961 962 #define OR_SDRAM_AM 0xFFFF8000 963 #define OR_SDRAM_AM_SHIFT 15 964 #define OR_SDRAM_XAM 0x00006000 965 #define OR_SDRAM_XAM_SHIFT 13 966 #define OR_SDRAM_COLS 0x00001C00 967 #define OR_SDRAM_COLS_SHIFT 10 968 #define OR_SDRAM_ROWS 0x000001C0 969 #define OR_SDRAM_ROWS_SHIFT 6 970 #define OR_SDRAM_PMSEL 0x00000020 971 #define OR_SDRAM_PMSEL_SHIFT 5 972 #define OR_SDRAM_EAD 0x00000001 973 #define OR_SDRAM_EAD_SHIFT 0 974 975 #define OR_AM_32KB 0xFFFF8000 976 #define OR_AM_64KB 0xFFFF0000 977 #define OR_AM_128KB 0xFFFE0000 978 #define OR_AM_256KB 0xFFFC0000 979 #define OR_AM_512KB 0xFFF80000 980 #define OR_AM_1MB 0xFFF00000 981 #define OR_AM_2MB 0xFFE00000 982 #define OR_AM_4MB 0xFFC00000 983 #define OR_AM_8MB 0xFF800000 984 #define OR_AM_16MB 0xFF000000 985 #define OR_AM_32MB 0xFE000000 986 #define OR_AM_64MB 0xFC000000 987 #define OR_AM_128MB 0xF8000000 988 #define OR_AM_256MB 0xF0000000 989 #define OR_AM_512MB 0xE0000000 990 #define OR_AM_1GB 0xC0000000 991 #define OR_AM_2GB 0x80000000 992 #define OR_AM_4GB 0x00000000 993 994 #define LBLAWAR_EN 0x80000000 995 #define LBLAWAR_4KB 0x0000000B 996 #define LBLAWAR_8KB 0x0000000C 997 #define LBLAWAR_16KB 0x0000000D 998 #define LBLAWAR_32KB 0x0000000E 999 #define LBLAWAR_64KB 0x0000000F 1000 #define LBLAWAR_128KB 0x00000010 1001 #define LBLAWAR_256KB 0x00000011 1002 #define LBLAWAR_512KB 0x00000012 1003 #define LBLAWAR_1MB 0x00000013 1004 #define LBLAWAR_2MB 0x00000014 1005 #define LBLAWAR_4MB 0x00000015 1006 #define LBLAWAR_8MB 0x00000016 1007 #define LBLAWAR_16MB 0x00000017 1008 #define LBLAWAR_32MB 0x00000018 1009 #define LBLAWAR_64MB 0x00000019 1010 #define LBLAWAR_128MB 0x0000001A 1011 #define LBLAWAR_256MB 0x0000001B 1012 #define LBLAWAR_512MB 0x0000001C 1013 #define LBLAWAR_1GB 0x0000001D 1014 #define LBLAWAR_2GB 0x0000001E 1015 1016 /* LBCR - Local Bus Configuration Register 1017 */ 1018 #define LBCR_LDIS 0x80000000 1019 #define LBCR_LDIS_SHIFT 31 1020 #define LBCR_BCTLC 0x00C00000 1021 #define LBCR_BCTLC_SHIFT 22 1022 #define LBCR_LPBSE 0x00020000 1023 #define LBCR_LPBSE_SHIFT 17 1024 #define LBCR_EPAR 0x00010000 1025 #define LBCR_EPAR_SHIFT 16 1026 #define LBCR_BMT 0x0000FF00 1027 #define LBCR_BMT_SHIFT 8 1028 1029 /* LCRR - Clock Ratio Register 1030 */ 1031 #define LCRR_DBYP 0x80000000 1032 #define LCRR_DBYP_SHIFT 31 1033 #define LCRR_BUFCMDC 0x30000000 1034 #define LCRR_BUFCMDC_SHIFT 28 1035 #define LCRR_BUFCMDC_1 0x10000000 1036 #define LCRR_BUFCMDC_2 0x20000000 1037 #define LCRR_BUFCMDC_3 0x30000000 1038 #define LCRR_BUFCMDC_4 0x00000000 1039 #define LCRR_ECL 0x03000000 1040 #define LCRR_ECL_SHIFT 24 1041 #define LCRR_ECL_4 0x00000000 1042 #define LCRR_ECL_5 0x01000000 1043 #define LCRR_ECL_6 0x02000000 1044 #define LCRR_ECL_7 0x03000000 1045 #define LCRR_EADC 0x00030000 1046 #define LCRR_EADC_SHIFT 16 1047 #define LCRR_EADC_1 0x00010000 1048 #define LCRR_EADC_2 0x00020000 1049 #define LCRR_EADC_3 0x00030000 1050 #define LCRR_EADC_4 0x00000000 1051 #define LCRR_CLKDIV 0x0000000F 1052 #define LCRR_CLKDIV_SHIFT 0 1053 #define LCRR_CLKDIV_2 0x00000002 1054 #define LCRR_CLKDIV_4 0x00000004 1055 #define LCRR_CLKDIV_8 0x00000008 1056 1057 /* DMAMR - DMA Mode Register 1058 */ 1059 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1060 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1061 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1062 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1063 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1064 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1065 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1066 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1067 1068 /* DMASR - DMA Status Register 1069 */ 1070 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1071 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 1072 1073 /* CONFIG_ADDRESS - PCI Config Address Register 1074 */ 1075 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1076 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1077 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1078 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1079 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1080 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1081 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1082 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1083 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1084 1085 /* POTAR - PCI Outbound Translation Address Register 1086 */ 1087 #define POTAR_TA_MASK 0x000fffff 1088 1089 /* POBAR - PCI Outbound Base Address Register 1090 */ 1091 #define POBAR_BA_MASK 0x000fffff 1092 1093 /* POCMR - PCI Outbound Comparision Mask Register 1094 */ 1095 #define POCMR_EN 0x80000000 1096 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1097 #define POCMR_SE 0x20000000 /* streaming enable */ 1098 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1099 #define POCMR_CM_MASK 0x000fffff 1100 #define POCMR_CM_4G 0x00000000 1101 #define POCMR_CM_2G 0x00080000 1102 #define POCMR_CM_1G 0x000C0000 1103 #define POCMR_CM_512M 0x000E0000 1104 #define POCMR_CM_256M 0x000F0000 1105 #define POCMR_CM_128M 0x000F8000 1106 #define POCMR_CM_64M 0x000FC000 1107 #define POCMR_CM_32M 0x000FE000 1108 #define POCMR_CM_16M 0x000FF000 1109 #define POCMR_CM_8M 0x000FF800 1110 #define POCMR_CM_4M 0x000FFC00 1111 #define POCMR_CM_2M 0x000FFE00 1112 #define POCMR_CM_1M 0x000FFF00 1113 #define POCMR_CM_512K 0x000FFF80 1114 #define POCMR_CM_256K 0x000FFFC0 1115 #define POCMR_CM_128K 0x000FFFE0 1116 #define POCMR_CM_64K 0x000FFFF0 1117 #define POCMR_CM_32K 0x000FFFF8 1118 #define POCMR_CM_16K 0x000FFFFC 1119 #define POCMR_CM_8K 0x000FFFFE 1120 #define POCMR_CM_4K 0x000FFFFF 1121 1122 /* PITAR - PCI Inbound Translation Address Register 1123 */ 1124 #define PITAR_TA_MASK 0x000fffff 1125 1126 /* PIBAR - PCI Inbound Base/Extended Address Register 1127 */ 1128 #define PIBAR_MASK 0xffffffff 1129 #define PIEBAR_EBA_MASK 0x000fffff 1130 1131 /* PIWAR - PCI Inbound Windows Attributes Register 1132 */ 1133 #define PIWAR_EN 0x80000000 1134 #define PIWAR_PF 0x20000000 1135 #define PIWAR_RTT_MASK 0x000f0000 1136 #define PIWAR_RTT_NO_SNOOP 0x00040000 1137 #define PIWAR_RTT_SNOOP 0x00050000 1138 #define PIWAR_WTT_MASK 0x0000f000 1139 #define PIWAR_WTT_NO_SNOOP 0x00004000 1140 #define PIWAR_WTT_SNOOP 0x00005000 1141 #define PIWAR_IWS_MASK 0x0000003F 1142 #define PIWAR_IWS_4K 0x0000000B 1143 #define PIWAR_IWS_8K 0x0000000C 1144 #define PIWAR_IWS_16K 0x0000000D 1145 #define PIWAR_IWS_32K 0x0000000E 1146 #define PIWAR_IWS_64K 0x0000000F 1147 #define PIWAR_IWS_128K 0x00000010 1148 #define PIWAR_IWS_256K 0x00000011 1149 #define PIWAR_IWS_512K 0x00000012 1150 #define PIWAR_IWS_1M 0x00000013 1151 #define PIWAR_IWS_2M 0x00000014 1152 #define PIWAR_IWS_4M 0x00000015 1153 #define PIWAR_IWS_8M 0x00000016 1154 #define PIWAR_IWS_16M 0x00000017 1155 #define PIWAR_IWS_32M 0x00000018 1156 #define PIWAR_IWS_64M 0x00000019 1157 #define PIWAR_IWS_128M 0x0000001A 1158 #define PIWAR_IWS_256M 0x0000001B 1159 #define PIWAR_IWS_512M 0x0000001C 1160 #define PIWAR_IWS_1G 0x0000001D 1161 #define PIWAR_IWS_2G 0x0000001E 1162 1163 /* PMCCR1 - PCI Configuration Register 1 1164 */ 1165 #define PMCCR1_POWER_OFF 0x00000020 1166 1167 /* FMR - Flash Mode Register 1168 */ 1169 #define FMR_CWTO 0x0000F000 1170 #define FMR_CWTO_SHIFT 12 1171 #define FMR_BOOT 0x00000800 1172 #define FMR_ECCM 0x00000100 1173 #define FMR_AL 0x00000030 1174 #define FMR_AL_SHIFT 4 1175 #define FMR_OP 0x00000003 1176 #define FMR_OP_SHIFT 0 1177 1178 /* FIR - Flash Instruction Register 1179 */ 1180 #define FIR_OP0 0xF0000000 1181 #define FIR_OP0_SHIFT 28 1182 #define FIR_OP1 0x0F000000 1183 #define FIR_OP1_SHIFT 24 1184 #define FIR_OP2 0x00F00000 1185 #define FIR_OP2_SHIFT 20 1186 #define FIR_OP3 0x000F0000 1187 #define FIR_OP3_SHIFT 16 1188 #define FIR_OP4 0x0000F000 1189 #define FIR_OP4_SHIFT 12 1190 #define FIR_OP5 0x00000F00 1191 #define FIR_OP5_SHIFT 8 1192 #define FIR_OP6 0x000000F0 1193 #define FIR_OP6_SHIFT 4 1194 #define FIR_OP7 0x0000000F 1195 #define FIR_OP7_SHIFT 0 1196 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1197 #define FIR_OP_CA 0x1 /* Issue current column address */ 1198 #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1199 #define FIR_OP_UA 0x3 /* Issue user defined address */ 1200 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1201 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1202 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1203 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1204 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1205 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1206 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1207 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1208 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1209 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1210 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1211 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1212 1213 /* FCR - Flash Command Register 1214 */ 1215 #define FCR_CMD0 0xFF000000 1216 #define FCR_CMD0_SHIFT 24 1217 #define FCR_CMD1 0x00FF0000 1218 #define FCR_CMD1_SHIFT 16 1219 #define FCR_CMD2 0x0000FF00 1220 #define FCR_CMD2_SHIFT 8 1221 #define FCR_CMD3 0x000000FF 1222 #define FCR_CMD3_SHIFT 0 1223 1224 /* FBAR - Flash Block Address Register 1225 */ 1226 #define FBAR_BLK 0x00FFFFFF 1227 1228 /* FPAR - Flash Page Address Register 1229 */ 1230 #define FPAR_SP_PI 0x00007C00 1231 #define FPAR_SP_PI_SHIFT 10 1232 #define FPAR_SP_MS 0x00000200 1233 #define FPAR_SP_CI 0x000001FF 1234 #define FPAR_SP_CI_SHIFT 0 1235 #define FPAR_LP_PI 0x0003F000 1236 #define FPAR_LP_PI_SHIFT 12 1237 #define FPAR_LP_MS 0x00000800 1238 #define FPAR_LP_CI 0x000007FF 1239 #define FPAR_LP_CI_SHIFT 0 1240 1241 /* LTESR - Transfer Error Status Register 1242 */ 1243 #define LTESR_BM 0x80000000 1244 #define LTESR_FCT 0x40000000 1245 #define LTESR_PAR 0x20000000 1246 #define LTESR_WP 0x04000000 1247 #define LTESR_ATMW 0x00800000 1248 #define LTESR_ATMR 0x00400000 1249 #define LTESR_CS 0x00080000 1250 #define LTESR_CC 0x00000001 1251 1252 /* DDR Control Driver Register 1253 */ 1254 #define DDRCDR_EN 0x40000000 1255 #define DDRCDR_PZ 0x3C000000 1256 #define DDRCDR_PZ_MAXZ 0x00000000 1257 #define DDRCDR_PZ_HIZ 0x20000000 1258 #define DDRCDR_PZ_NOMZ 0x30000000 1259 #define DDRCDR_PZ_LOZ 0x38000000 1260 #define DDRCDR_PZ_MINZ 0x3C000000 1261 #define DDRCDR_NZ 0x3C000000 1262 #define DDRCDR_NZ_MAXZ 0x00000000 1263 #define DDRCDR_NZ_HIZ 0x02000000 1264 #define DDRCDR_NZ_NOMZ 0x03000000 1265 #define DDRCDR_NZ_LOZ 0x03800000 1266 #define DDRCDR_NZ_MINZ 0x03C00000 1267 #define DDRCDR_ODT 0x00080000 1268 #define DDRCDR_DDR_CFG 0x00040000 1269 #define DDRCDR_M_ODR 0x00000002 1270 #define DDRCDR_Q_DRN 0x00000001 1271 1272 #ifndef __ASSEMBLY__ 1273 struct pci_region; 1274 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1275 #endif 1276 1277 #endif /* __MPC83XX_H__ */ 1278