1 /* 2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 /* 14 * mpc83xx.h 15 * 16 * MPC83xx specific definitions 17 */ 18 19 #ifndef __MPC83XX_H__ 20 #define __MPC83XX_H__ 21 22 #include <config.h> 23 #if defined(CONFIG_E300) 24 #include <asm/e300.h> 25 #endif 26 27 /* 28 * MPC83xx cpu provide RCR register to do reset thing specially. easier 29 * to implement 30 */ 31 32 #define MPC83xx_RESET 33 34 /* 35 * System reset offset (PowerPC standard) 36 */ 37 #define EXC_OFF_SYS_RESET 0x0100 38 39 /* 40 * Default Internal Memory Register Space (Freescale recomandation) 41 */ 42 #define CONFIG_DEFAULT_IMMR 0xFF400000 43 44 /* 45 * Watchdog 46 */ 47 #define SWCRR 0x0204 48 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ 49 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ 50 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ 51 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ 52 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 53 54 #define SWCNR 0x0208 55 #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. 56 #define SWCNR_RES ~(SWCNR_SWCN) 57 58 #define SWSRR 0x020E 59 60 /* 61 * Default Internal Memory Register Space (Freescale recomandation) 62 */ 63 #define IMMRBAR 0x0000 64 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ 65 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 66 67 /* 68 * Default Internal Memory Register Space (Freescale recomandation) 69 */ 70 #define LBLAWBAR0 0x0020 71 #define LBLAWAR0 0x0024 72 #define LBLAWBAR1 0x0028 73 #define LBLAWAR1 0x002C 74 #define LBLAWBAR2 0x0030 75 #define LBLAWAR2 0x0034 76 #define LBLAWBAR3 0x0038 77 #define LBLAWAR3 0x003C 78 79 /* 80 * The device ID and revision numbers 81 */ 82 #define SPR_8349E_REV10 0x80300100 83 #define SPR_8349_REV10 0x80310100 84 #define SPR_8347E_REV10_TBGA 0x80320100 85 #define SPR_8347_REV10_TBGA 0x80330100 86 #define SPR_8347E_REV10_PBGA 0x80340100 87 #define SPR_8347_REV10_PBGA 0x80350100 88 #define SPR_8343E_REV10 0x80360100 89 #define SPR_8343_REV10 0x80370100 90 91 #define SPR_8349E_REV11 0x80300101 92 #define SPR_8349_REV11 0x80310101 93 #define SPR_8347E_REV11_TBGA 0x80320101 94 #define SPR_8347_REV11_TBGA 0x80330101 95 #define SPR_8347E_REV11_PBGA 0x80340101 96 #define SPR_8347_REV11_PBGA 0x80350101 97 #define SPR_8343E_REV11 0x80360101 98 #define SPR_8343_REV11 0x80370101 99 100 #define SPR_8360E_REV10 0x80480010 101 #define SPR_8360_REV10 0x80490010 102 #define SPR_8360E_REV11 0x80480011 103 #define SPR_8360_REV11 0x80490011 104 #define SPR_8360E_REV12 0x80480012 105 #define SPR_8360_REV12 0x80490012 106 107 /* 108 * Base Registers & Option Registers 109 */ 110 #define BR0 0x5000 111 #define BR1 0x5008 112 #define BR2 0x5010 113 #define BR3 0x5018 114 #define BR4 0x5020 115 #define BR5 0x5028 116 #define BR6 0x5030 117 #define BR7 0x5038 118 119 #define BR_BA 0xFFFF8000 120 #define BR_BA_SHIFT 15 121 #define BR_PS 0x00001800 122 #define BR_PS_SHIFT 11 123 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 124 #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 125 #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 126 #define BR_DECC 0x00000600 127 #define BR_DECC_SHIFT 9 128 #define BR_WP 0x00000100 129 #define BR_WP_SHIFT 8 130 #define BR_MSEL 0x000000E0 131 #define BR_MSEL_SHIFT 5 132 #define BR_MS_GPCM 0x00000000 /* GPCM */ 133 #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 134 #define BR_MS_UPMA 0x00000080 /* UPMA */ 135 #define BR_MS_UPMB 0x000000A0 /* UPMB */ 136 #define BR_MS_UPMC 0x000000C0 /* UPMC */ 137 #if defined (CONFIG_MPC8360) 138 #define BR_ATOM 0x0000000C 139 #define BR_ATOM_SHIFT 2 140 #endif 141 #define BR_V 0x00000001 142 #define BR_V_SHIFT 0 143 #if defined (CONFIG_MPC8349) 144 #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 145 #elif defined (CONFIG_MPC8360) 146 #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) 147 #endif 148 149 #define OR0 0x5004 150 #define OR1 0x500C 151 #define OR2 0x5014 152 #define OR3 0x501C 153 #define OR4 0x5024 154 #define OR5 0x502C 155 #define OR6 0x5034 156 #define OR7 0x503C 157 158 #define OR_GPCM_AM 0xFFFF8000 159 #define OR_GPCM_AM_SHIFT 15 160 #define OR_GPCM_BCTLD 0x00001000 161 #define OR_GPCM_BCTLD_SHIFT 12 162 #define OR_GPCM_CSNT 0x00000800 163 #define OR_GPCM_CSNT_SHIFT 11 164 #define OR_GPCM_ACS 0x00000600 165 #define OR_GPCM_ACS_SHIFT 9 166 #define OR_GPCM_ACS_0b10 0x00000400 167 #define OR_GPCM_ACS_0b11 0x00000600 168 #define OR_GPCM_XACS 0x00000100 169 #define OR_GPCM_XACS_SHIFT 8 170 #define OR_GPCM_SCY 0x000000F0 171 #define OR_GPCM_SCY_SHIFT 4 172 #define OR_GPCM_SCY_1 0x00000010 173 #define OR_GPCM_SCY_2 0x00000020 174 #define OR_GPCM_SCY_3 0x00000030 175 #define OR_GPCM_SCY_4 0x00000040 176 #define OR_GPCM_SCY_5 0x00000050 177 #define OR_GPCM_SCY_6 0x00000060 178 #define OR_GPCM_SCY_7 0x00000070 179 #define OR_GPCM_SCY_8 0x00000080 180 #define OR_GPCM_SCY_9 0x00000090 181 #define OR_GPCM_SCY_10 0x000000a0 182 #define OR_GPCM_SCY_11 0x000000b0 183 #define OR_GPCM_SCY_12 0x000000c0 184 #define OR_GPCM_SCY_13 0x000000d0 185 #define OR_GPCM_SCY_14 0x000000e0 186 #define OR_GPCM_SCY_15 0x000000f0 187 #define OR_GPCM_SETA 0x00000008 188 #define OR_GPCM_SETA_SHIFT 3 189 #define OR_GPCM_TRLX 0x00000004 190 #define OR_GPCM_TRLX_SHIFT 2 191 #define OR_GPCM_EHTR 0x00000002 192 #define OR_GPCM_EHTR_SHIFT 1 193 #define OR_GPCM_EAD 0x00000001 194 #define OR_GPCM_EAD_SHIFT 0 195 196 #define OR_UPM_AM 0xFFFF8000 197 #define OR_UPM_AM_SHIFT 15 198 #define OR_UPM_XAM 0x00006000 199 #define OR_UPM_XAM_SHIFT 13 200 #define OR_UPM_BCTLD 0x00001000 201 #define OR_UPM_BCTLD_SHIFT 12 202 #define OR_UPM_BI 0x00000100 203 #define OR_UPM_BI_SHIFT 8 204 #define OR_UPM_TRLX 0x00000004 205 #define OR_UPM_TRLX_SHIFT 2 206 #define OR_UPM_EHTR 0x00000002 207 #define OR_UPM_EHTR_SHIFT 1 208 #define OR_UPM_EAD 0x00000001 209 #define OR_UPM_EAD_SHIFT 0 210 211 #define OR_SDRAM_AM 0xFFFF8000 212 #define OR_SDRAM_AM_SHIFT 15 213 #define OR_SDRAM_XAM 0x00006000 214 #define OR_SDRAM_XAM_SHIFT 13 215 #define OR_SDRAM_COLS 0x00001C00 216 #define OR_SDRAM_COLS_SHIFT 10 217 #define OR_SDRAM_ROWS 0x000001C0 218 #define OR_SDRAM_ROWS_SHIFT 6 219 #define OR_SDRAM_PMSEL 0x00000020 220 #define OR_SDRAM_PMSEL_SHIFT 5 221 #define OR_SDRAM_EAD 0x00000001 222 #define OR_SDRAM_EAD_SHIFT 0 223 224 /* 225 * Hard Reset Configration Word - High 226 */ 227 #define HRCWH_PCI_AGENT 0x00000000 228 #define HRCWH_PCI_HOST 0x80000000 229 230 #if defined (CONFIG_MPC8349) 231 #define HRCWH_32_BIT_PCI 0x00000000 232 #define HRCWH_64_BIT_PCI 0x40000000 233 #endif 234 235 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 236 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 237 238 #if defined (CONFIG_MPC8349) 239 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 240 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 241 #elif defined (CONFIG_MPC8360) 242 #define HRCWH_PCICKDRV_DISABLE 0x00000000 243 #define HRCWH_PCICKDRV_ENABLE 0x10000000 244 #endif 245 246 #define HRCWH_CORE_DISABLE 0x08000000 247 #define HRCWH_CORE_ENABLE 0x00000000 248 249 #define HRCWH_FROM_0X00000100 0x00000000 250 #define HRCWH_FROM_0XFFF00100 0x04000000 251 252 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 253 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 254 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 255 256 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 257 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 258 259 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 260 #define HRCWH_ROM_LOC_PCI1 0x00100000 261 #if defined (CONFIG_MPC8349) 262 #define HRCWH_ROM_LOC_PCI2 0x00200000 263 #endif 264 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 265 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 266 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 267 268 #if defined (CONFIG_MPC8349) 269 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 270 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 271 #define HRCWH_TSEC1M_IN_GMII 0x00008000 272 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 273 274 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 275 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 276 #define HRCWH_TSEC2M_IN_GMII 0x00002000 277 #define HRCWH_TSEC2M_IN_TBI 0x00003000 278 #endif 279 280 #if defined (CONFIG_MPC8360) 281 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 282 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 283 #endif 284 285 #define HRCWH_BIG_ENDIAN 0x00000000 286 #define HRCWH_LITTLE_ENDIAN 0x00000008 287 288 #define HRCWH_LALE_NORMAL 0x00000000 289 #define HRCWH_LALE_EARLY 0x00000004 290 291 #define HRCWH_LDP_SET 0x00000000 292 #define HRCWH_LDP_CLEAR 0x00000002 293 294 /* 295 * Hard Reset Configration Word - Low 296 */ 297 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 298 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 299 300 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 301 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 302 303 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 304 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 305 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 306 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 307 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 308 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 309 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 310 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 311 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 312 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 313 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 314 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 315 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 316 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 317 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 318 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 319 320 #define HRCWL_VCO_BYPASS 0x00000000 321 #define HRCWL_VCO_1X2 0x00000000 322 #define HRCWL_VCO_1X4 0x00200000 323 #define HRCWL_VCO_1X8 0x00400000 324 325 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 326 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 327 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 328 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 329 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 330 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 331 332 #if defined (CONFIG_MPC8360) 333 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 334 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 335 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 336 337 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 338 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 339 340 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 341 #define HRCWL_CE_TO_PLL_1X2 0x00000002 342 #define HRCWL_CE_TO_PLL_1X3 0x00000003 343 #define HRCWL_CE_TO_PLL_1X4 0x00000004 344 #define HRCWL_CE_TO_PLL_1X5 0x00000005 345 #define HRCWL_CE_TO_PLL_1X6 0x00000006 346 #define HRCWL_CE_TO_PLL_1X7 0x00000007 347 #define HRCWL_CE_TO_PLL_1X8 0x00000008 348 #define HRCWL_CE_TO_PLL_1X9 0x00000009 349 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 350 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 351 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 352 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 353 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 354 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 355 #define HRCWL_CE_TO_PLL_1X16 0x00000010 356 #define HRCWL_CE_TO_PLL_1X17 0x00000011 357 #define HRCWL_CE_TO_PLL_1X18 0x00000012 358 #define HRCWL_CE_TO_PLL_1X19 0x00000013 359 #define HRCWL_CE_TO_PLL_1X20 0x00000014 360 #define HRCWL_CE_TO_PLL_1X21 0x00000015 361 #define HRCWL_CE_TO_PLL_1X22 0x00000016 362 #define HRCWL_CE_TO_PLL_1X23 0x00000017 363 #define HRCWL_CE_TO_PLL_1X24 0x00000018 364 #define HRCWL_CE_TO_PLL_1X25 0x00000019 365 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 366 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 367 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 368 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 369 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 370 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 371 #endif 372 373 /* 374 * LCRR - Clock Ratio Register (10.3.1.16) 375 */ 376 #define LCRR_DBYP 0x80000000 377 #define LCRR_DBYP_SHIFT 31 378 #define LCRR_BUFCMDC 0x30000000 379 #define LCRR_BUFCMDC_1 0x10000000 380 #define LCRR_BUFCMDC_2 0x20000000 381 #define LCRR_BUFCMDC_3 0x30000000 382 #define LCRR_BUFCMDC_4 0x00000000 383 #define LCRR_BUFCMDC_SHIFT 28 384 #define LCRR_ECL 0x03000000 385 #define LCRR_ECL_4 0x00000000 386 #define LCRR_ECL_5 0x01000000 387 #define LCRR_ECL_6 0x02000000 388 #define LCRR_ECL_7 0x03000000 389 #define LCRR_ECL_SHIFT 24 390 #define LCRR_EADC 0x00030000 391 #define LCRR_EADC_1 0x00010000 392 #define LCRR_EADC_2 0x00020000 393 #define LCRR_EADC_3 0x00030000 394 #define LCRR_EADC_4 0x00000000 395 #define LCRR_EADC_SHIFT 16 396 #define LCRR_CLKDIV 0x0000000F 397 #define LCRR_CLKDIV_2 0x00000002 398 #define LCRR_CLKDIV_4 0x00000004 399 #define LCRR_CLKDIV_8 0x00000008 400 #define LCRR_CLKDIV_SHIFT 0 401 402 /* 403 * SCCR-System Clock Control Register 404 */ 405 #define SCCR_TSEC1CM_0 0x00000000 406 #define SCCR_TSEC1CM_1 0x40000000 407 #define SCCR_TSEC1CM_2 0x80000000 408 #define SCCR_TSEC1CM_3 0xC0000000 409 #define SCCR_TSEC2CM_0 0x00000000 410 #define SCCR_TSEC2CM_1 0x10000000 411 #define SCCR_TSEC2CM_2 0x20000000 412 #define SCCR_TSEC2CM_3 0x30000000 413 #define SCCR_ENCCM_0 0x00000000 414 #define SCCR_ENCCM_1 0x01000000 415 #define SCCR_ENCCM_2 0x02000000 416 #define SCCR_ENCCM_3 0x03000000 417 #define SCCR_USBCM_0 0x00000000 418 #define SCCR_USBCM_1 0x00500000 419 #define SCCR_USBCM_2 0x00A00000 420 #define SCCR_USBCM_3 0x00F00000 421 422 #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ 423 | SCCR_TSEC2CM_3 \ 424 | SCCR_ENCCM_3 \ 425 | SCCR_USBCM_3 ) 426 427 #define SCCR_DEFAULT 0xFFFFFFFF 428 429 #endif /* __MPC83XX_H__ */ 430