1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #include <asm/fsl_lbc.h> 18 #if defined(CONFIG_E300) 19 #include <asm/e300.h> 20 #endif 21 22 /* MPC83xx cpu provide RCR register to do reset thing specially 23 */ 24 #define MPC83xx_RESET 25 26 /* System reset offset (PowerPC standard) 27 */ 28 #define EXC_OFF_SYS_RESET 0x0100 29 #define _START_OFFSET EXC_OFF_SYS_RESET 30 31 /* IMMRBAR - Internal Memory Register Base Address 32 */ 33 #ifndef CONFIG_DEFAULT_IMMR 34 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 35 #endif 36 #define IMMRBAR 0x0000 /* Register offset to immr */ 37 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 38 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 39 40 /* LAWBAR - Local Access Window Base Address Register 41 */ 42 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 43 #define LBLAWAR0 0x0024 44 #define LBLAWBAR1 0x0028 45 #define LBLAWAR1 0x002C 46 #define LBLAWBAR2 0x0030 47 #define LBLAWAR2 0x0034 48 #define LBLAWBAR3 0x0038 49 #define LBLAWAR3 0x003C 50 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 51 52 /* SPRIDR - System Part and Revision ID Register 53 */ 54 #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 55 #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 56 57 #if defined(CONFIG_MPC834X) 58 #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 59 #define REVID_MINOR(spridr) (spridr & 0x000000FF) 60 #else 61 #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 62 #define REVID_MINOR(spridr) (spridr & 0x0000000F) 63 #endif 64 65 #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 66 #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 67 68 #define SPR_831X_FAMILY 0x80B 69 #define SPR_8311 0x80B2 70 #define SPR_8313 0x80B0 71 #define SPR_8314 0x80B6 72 #define SPR_8315 0x80B4 73 #define SPR_832X_FAMILY 0x806 74 #define SPR_8321 0x8066 75 #define SPR_8323 0x8062 76 #define SPR_834X_FAMILY 0x803 77 #define SPR_8343 0x8036 78 #define SPR_8347_TBGA_ 0x8032 79 #define SPR_8347_PBGA_ 0x8034 80 #define SPR_8349 0x8030 81 #define SPR_836X_FAMILY 0x804 82 #define SPR_8358_TBGA_ 0x804A 83 #define SPR_8358_PBGA_ 0x804E 84 #define SPR_8360 0x8048 85 #define SPR_837X_FAMILY 0x80C 86 #define SPR_8377 0x80C6 87 #define SPR_8378 0x80C4 88 #define SPR_8379 0x80C2 89 90 /* SPCR - System Priority Configuration Register 91 */ 92 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 93 #define SPCR_PCIHPE_SHIFT (31-3) 94 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 95 #define SPCR_PCIPR_SHIFT (31-7) 96 #define SPCR_OPT 0x00800000 /* Optimize */ 97 #define SPCR_OPT_SHIFT (31-8) 98 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 99 #define SPCR_TBEN_SHIFT (31-9) 100 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 101 #define SPCR_COREPR_SHIFT (31-11) 102 103 #if defined(CONFIG_MPC834X) 104 /* SPCR bits - MPC8349 specific */ 105 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 106 #define SPCR_TSEC1DP_SHIFT (31-19) 107 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 108 #define SPCR_TSEC1BDP_SHIFT (31-21) 109 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 110 #define SPCR_TSEC1EP_SHIFT (31-23) 111 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 112 #define SPCR_TSEC2DP_SHIFT (31-27) 113 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 114 #define SPCR_TSEC2BDP_SHIFT (31-29) 115 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 116 #define SPCR_TSEC2EP_SHIFT (31-31) 117 118 #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 119 /* SPCR bits - MPC831x and MPC837x specific */ 120 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 121 #define SPCR_TSECDP_SHIFT (31-19) 122 #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 123 #define SPCR_TSECBDP_SHIFT (31-21) 124 #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 125 #define SPCR_TSECEP_SHIFT (31-23) 126 #endif 127 128 /* SICRL/H - System I/O Configuration Register Low/High 129 */ 130 #if defined(CONFIG_MPC834X) 131 /* SICRL bits - MPC8349 specific */ 132 #define SICRL_LDP_A 0x80000000 133 #define SICRL_USB1 0x40000000 134 #define SICRL_USB0 0x20000000 135 #define SICRL_UART 0x0C000000 136 #define SICRL_GPIO1_A 0x02000000 137 #define SICRL_GPIO1_B 0x01000000 138 #define SICRL_GPIO1_C 0x00800000 139 #define SICRL_GPIO1_D 0x00400000 140 #define SICRL_GPIO1_E 0x00200000 141 #define SICRL_GPIO1_F 0x00180000 142 #define SICRL_GPIO1_G 0x00040000 143 #define SICRL_GPIO1_H 0x00020000 144 #define SICRL_GPIO1_I 0x00010000 145 #define SICRL_GPIO1_J 0x00008000 146 #define SICRL_GPIO1_K 0x00004000 147 #define SICRL_GPIO1_L 0x00003000 148 149 /* SICRH bits - MPC8349 specific */ 150 #define SICRH_DDR 0x80000000 151 #define SICRH_TSEC1_A 0x10000000 152 #define SICRH_TSEC1_B 0x08000000 153 #define SICRH_TSEC1_C 0x04000000 154 #define SICRH_TSEC1_D 0x02000000 155 #define SICRH_TSEC1_E 0x01000000 156 #define SICRH_TSEC1_F 0x00800000 157 #define SICRH_TSEC2_A 0x00400000 158 #define SICRH_TSEC2_B 0x00200000 159 #define SICRH_TSEC2_C 0x00100000 160 #define SICRH_TSEC2_D 0x00080000 161 #define SICRH_TSEC2_E 0x00040000 162 #define SICRH_TSEC2_F 0x00020000 163 #define SICRH_TSEC2_G 0x00010000 164 #define SICRH_TSEC2_H 0x00008000 165 #define SICRH_GPIO2_A 0x00004000 166 #define SICRH_GPIO2_B 0x00002000 167 #define SICRH_GPIO2_C 0x00001000 168 #define SICRH_GPIO2_D 0x00000800 169 #define SICRH_GPIO2_E 0x00000400 170 #define SICRH_GPIO2_F 0x00000200 171 #define SICRH_GPIO2_G 0x00000180 172 #define SICRH_GPIO2_H 0x00000060 173 #define SICRH_TSOBI1 0x00000002 174 #define SICRH_TSOBI2 0x00000001 175 176 #elif defined(CONFIG_MPC8360) 177 /* SICRL bits - MPC8360 specific */ 178 #define SICRL_LDP_A 0xC0000000 179 #define SICRL_LCLK_1 0x10000000 180 #define SICRL_LCLK_2 0x08000000 181 #define SICRL_SRCID_A 0x03000000 182 #define SICRL_IRQ_CKSTP_A 0x00C00000 183 184 /* SICRH bits - MPC8360 specific */ 185 #define SICRH_DDR 0x80000000 186 #define SICRH_SECONDARY_DDR 0x40000000 187 #define SICRH_SDDROE 0x20000000 188 #define SICRH_IRQ3 0x10000000 189 #define SICRH_UC1EOBI 0x00000004 190 #define SICRH_UC2E1OBI 0x00000002 191 #define SICRH_UC2E2OBI 0x00000001 192 193 #elif defined(CONFIG_MPC832X) 194 /* SICRL bits - MPC832X specific */ 195 #define SICRL_LDP_LCS_A 0x80000000 196 #define SICRL_IRQ_CKS 0x20000000 197 #define SICRL_PCI_MSRC 0x10000000 198 #define SICRL_URT_CTPR 0x06000000 199 #define SICRL_IRQ_CTPR 0x00C00000 200 201 #elif defined(CONFIG_MPC8313) 202 /* SICRL bits - MPC8313 specific */ 203 #define SICRL_LBC 0x30000000 204 #define SICRL_UART 0x0C000000 205 #define SICRL_SPI_A 0x03000000 206 #define SICRL_SPI_B 0x00C00000 207 #define SICRL_SPI_C 0x00300000 208 #define SICRL_SPI_D 0x000C0000 209 #define SICRL_USBDR 0x00000C00 210 #define SICRL_ETSEC1_A 0x0000000C 211 #define SICRL_ETSEC2_A 0x00000003 212 213 /* SICRH bits - MPC8313 specific */ 214 #define SICRH_INTR_A 0x02000000 215 #define SICRH_INTR_B 0x00C00000 216 #define SICRH_IIC 0x00300000 217 #define SICRH_ETSEC2_B 0x000C0000 218 #define SICRH_ETSEC2_C 0x00030000 219 #define SICRH_ETSEC2_D 0x0000C000 220 #define SICRH_ETSEC2_E 0x00003000 221 #define SICRH_ETSEC2_F 0x00000C00 222 #define SICRH_ETSEC2_G 0x00000300 223 #define SICRH_ETSEC1_B 0x00000080 224 #define SICRH_ETSEC1_C 0x00000060 225 #define SICRH_GTX1_DLY 0x00000008 226 #define SICRH_GTX2_DLY 0x00000004 227 #define SICRH_TSOBI1 0x00000002 228 #define SICRH_TSOBI2 0x00000001 229 230 #elif defined(CONFIG_MPC8315) 231 /* SICRL bits - MPC8315 specific */ 232 #define SICRL_DMA_CH0 0xc0000000 233 #define SICRL_DMA_SPI 0x30000000 234 #define SICRL_UART 0x0c000000 235 #define SICRL_IRQ4 0x02000000 236 #define SICRL_IRQ5 0x01800000 237 #define SICRL_IRQ6_7 0x00400000 238 #define SICRL_IIC1 0x00300000 239 #define SICRL_TDM 0x000c0000 240 #define SICRL_TDM_SHARED 0x00030000 241 #define SICRL_PCI_A 0x0000c000 242 #define SICRL_ELBC_A 0x00003000 243 #define SICRL_ETSEC1_A 0x000000c0 244 #define SICRL_ETSEC1_B 0x00000030 245 #define SICRL_ETSEC1_C 0x0000000c 246 #define SICRL_TSEXPOBI 0x00000001 247 248 /* SICRH bits - MPC8315 specific */ 249 #define SICRH_GPIO_0 0xc0000000 250 #define SICRH_GPIO_1 0x30000000 251 #define SICRH_GPIO_2 0x0c000000 252 #define SICRH_GPIO_3 0x03000000 253 #define SICRH_GPIO_4 0x00c00000 254 #define SICRH_GPIO_5 0x00300000 255 #define SICRH_GPIO_6 0x000c0000 256 #define SICRH_GPIO_7 0x00030000 257 #define SICRH_GPIO_8 0x0000c000 258 #define SICRH_GPIO_9 0x00003000 259 #define SICRH_GPIO_10 0x00000c00 260 #define SICRH_GPIO_11 0x00000300 261 #define SICRH_ETSEC2_A 0x000000c0 262 #define SICRH_TSOBI1 0x00000002 263 #define SICRH_TSOBI2 0x00000001 264 265 #elif defined(CONFIG_MPC837X) 266 /* SICRL bits - MPC837x specific */ 267 #define SICRL_USB_A 0xC0000000 268 #define SICRL_USB_B 0x30000000 269 #define SICRL_UART 0x0C000000 270 #define SICRL_GPIO_A 0x02000000 271 #define SICRL_GPIO_B 0x01000000 272 #define SICRL_GPIO_C 0x00800000 273 #define SICRL_GPIO_D 0x00400000 274 #define SICRL_GPIO_E 0x00200000 275 #define SICRL_GPIO_F 0x00180000 276 #define SICRL_GPIO_G 0x00040000 277 #define SICRL_GPIO_H 0x00020000 278 #define SICRL_GPIO_I 0x00010000 279 #define SICRL_GPIO_J 0x00008000 280 #define SICRL_GPIO_K 0x00004000 281 #define SICRL_GPIO_L 0x00003000 282 #define SICRL_DMA_A 0x00000800 283 #define SICRL_DMA_B 0x00000400 284 #define SICRL_DMA_C 0x00000200 285 #define SICRL_DMA_D 0x00000100 286 #define SICRL_DMA_E 0x00000080 287 #define SICRL_DMA_F 0x00000040 288 #define SICRL_DMA_G 0x00000020 289 #define SICRL_DMA_H 0x00000010 290 #define SICRL_DMA_I 0x00000008 291 #define SICRL_DMA_J 0x00000004 292 #define SICRL_LDP_A 0x00000002 293 #define SICRL_LDP_B 0x00000001 294 295 /* SICRH bits - MPC837x specific */ 296 #define SICRH_DDR 0x80000000 297 #define SICRH_TSEC1_A 0x10000000 298 #define SICRH_TSEC1_B 0x08000000 299 #define SICRH_TSEC2_A 0x00400000 300 #define SICRH_TSEC2_B 0x00200000 301 #define SICRH_TSEC2_C 0x00100000 302 #define SICRH_TSEC2_D 0x00080000 303 #define SICRH_TSEC2_E 0x00040000 304 #define SICRH_TMR 0x00010000 305 #define SICRH_GPIO2_A 0x00008000 306 #define SICRH_GPIO2_B 0x00004000 307 #define SICRH_GPIO2_C 0x00002000 308 #define SICRH_GPIO2_D 0x00001000 309 #define SICRH_GPIO2_E 0x00000C00 310 #define SICRH_GPIO2_F 0x00000300 311 #define SICRH_GPIO2_G 0x000000C0 312 #define SICRH_GPIO2_H 0x00000030 313 #define SICRH_SPI 0x00000003 314 #endif 315 316 /* SWCRR - System Watchdog Control Register 317 */ 318 #define SWCRR 0x0204 /* Register offset to immr */ 319 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 320 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 321 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 322 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 323 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 324 325 /* SWCNR - System Watchdog Counter Register 326 */ 327 #define SWCNR 0x0208 /* Register offset to immr */ 328 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 329 #define SWCNR_RES ~(SWCNR_SWCN) 330 331 /* SWSRR - System Watchdog Service Register 332 */ 333 #define SWSRR 0x020E /* Register offset to immr */ 334 335 /* ACR - Arbiter Configuration Register 336 */ 337 #define ACR_COREDIS 0x10000000 /* Core disable */ 338 #define ACR_COREDIS_SHIFT (31-7) 339 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 340 #define ACR_PIPE_DEP_SHIFT (31-15) 341 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 342 #define ACR_PCI_RPTCNT_SHIFT (31-19) 343 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 344 #define ACR_RPTCNT_SHIFT (31-23) 345 #define ACR_APARK 0x00000030 /* Address parking */ 346 #define ACR_APARK_SHIFT (31-27) 347 #define ACR_PARKM 0x0000000F /* Parking master */ 348 #define ACR_PARKM_SHIFT (31-31) 349 350 /* ATR - Arbiter Timers Register 351 */ 352 #define ATR_DTO 0x00FF0000 /* Data time out */ 353 #define ATR_ATO 0x000000FF /* Address time out */ 354 355 /* AER - Arbiter Event Register 356 */ 357 #define AER_ETEA 0x00000020 /* Transfer error */ 358 #define AER_RES 0x00000010 /* Reserved transfer type */ 359 #define AER_ECW 0x00000008 /* External control word transfer type */ 360 #define AER_AO 0x00000004 /* Address Only transfer type */ 361 #define AER_DTO 0x00000002 /* Data time out */ 362 #define AER_ATO 0x00000001 /* Address time out */ 363 364 /* AEATR - Arbiter Event Address Register 365 */ 366 #define AEATR_EVENT 0x07000000 /* Event type */ 367 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 368 #define AEATR_TBST 0x00000800 /* Transfer burst */ 369 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 370 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 371 372 /* HRCWL - Hard Reset Configuration Word Low 373 */ 374 #define HRCWL_LBIUCM 0x80000000 375 #define HRCWL_LBIUCM_SHIFT 31 376 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 377 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 378 379 #define HRCWL_DDRCM 0x40000000 380 #define HRCWL_DDRCM_SHIFT 30 381 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 382 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 383 384 #define HRCWL_SPMF 0x0f000000 385 #define HRCWL_SPMF_SHIFT 24 386 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 387 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 388 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 389 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 390 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 391 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 392 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 393 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 394 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 395 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 396 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 397 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 398 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 399 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 400 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 401 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 402 403 #define HRCWL_VCO_BYPASS 0x00000000 404 #define HRCWL_VCO_1X2 0x00000000 405 #define HRCWL_VCO_1X4 0x00200000 406 #define HRCWL_VCO_1X8 0x00400000 407 408 #define HRCWL_COREPLL 0x007F0000 409 #define HRCWL_COREPLL_SHIFT 16 410 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 411 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 412 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 413 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 414 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 415 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 416 417 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 418 #define HRCWL_CEVCOD 0x000000C0 419 #define HRCWL_CEVCOD_SHIFT 6 420 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 421 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 422 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 423 424 #define HRCWL_CEPDF 0x00000020 425 #define HRCWL_CEPDF_SHIFT 5 426 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 427 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 428 429 #define HRCWL_CEPMF 0x0000001F 430 #define HRCWL_CEPMF_SHIFT 0 431 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 432 #define HRCWL_CE_TO_PLL_1X2 0x00000002 433 #define HRCWL_CE_TO_PLL_1X3 0x00000003 434 #define HRCWL_CE_TO_PLL_1X4 0x00000004 435 #define HRCWL_CE_TO_PLL_1X5 0x00000005 436 #define HRCWL_CE_TO_PLL_1X6 0x00000006 437 #define HRCWL_CE_TO_PLL_1X7 0x00000007 438 #define HRCWL_CE_TO_PLL_1X8 0x00000008 439 #define HRCWL_CE_TO_PLL_1X9 0x00000009 440 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 441 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 442 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 443 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 444 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 445 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 446 #define HRCWL_CE_TO_PLL_1X16 0x00000010 447 #define HRCWL_CE_TO_PLL_1X17 0x00000011 448 #define HRCWL_CE_TO_PLL_1X18 0x00000012 449 #define HRCWL_CE_TO_PLL_1X19 0x00000013 450 #define HRCWL_CE_TO_PLL_1X20 0x00000014 451 #define HRCWL_CE_TO_PLL_1X21 0x00000015 452 #define HRCWL_CE_TO_PLL_1X22 0x00000016 453 #define HRCWL_CE_TO_PLL_1X23 0x00000017 454 #define HRCWL_CE_TO_PLL_1X24 0x00000018 455 #define HRCWL_CE_TO_PLL_1X25 0x00000019 456 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 457 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 458 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 459 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 460 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 461 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 462 463 #elif defined(CONFIG_MPC8315) 464 #define HRCWL_SVCOD 0x30000000 465 #define HRCWL_SVCOD_SHIFT 28 466 #define HRCWL_SVCOD_DIV_2 0x00000000 467 #define HRCWL_SVCOD_DIV_4 0x10000000 468 #define HRCWL_SVCOD_DIV_8 0x20000000 469 #define HRCWL_SVCOD_DIV_1 0x30000000 470 471 #elif defined(CONFIG_MPC837X) 472 #define HRCWL_SVCOD 0x30000000 473 #define HRCWL_SVCOD_SHIFT 28 474 #define HRCWL_SVCOD_DIV_4 0x00000000 475 #define HRCWL_SVCOD_DIV_8 0x10000000 476 #define HRCWL_SVCOD_DIV_2 0x20000000 477 #define HRCWL_SVCOD_DIV_1 0x30000000 478 #endif 479 480 /* HRCWH - Hardware Reset Configuration Word High 481 */ 482 #define HRCWH_PCI_HOST 0x80000000 483 #define HRCWH_PCI_HOST_SHIFT 31 484 #define HRCWH_PCI_AGENT 0x00000000 485 486 #if defined(CONFIG_MPC834X) 487 #define HRCWH_32_BIT_PCI 0x00000000 488 #define HRCWH_64_BIT_PCI 0x40000000 489 #endif 490 491 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 492 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 493 494 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 495 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 496 497 #if defined(CONFIG_MPC834X) 498 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 499 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 500 501 #elif defined(CONFIG_MPC8360) 502 #define HRCWH_PCICKDRV_DISABLE 0x00000000 503 #define HRCWH_PCICKDRV_ENABLE 0x10000000 504 #endif 505 506 #define HRCWH_CORE_DISABLE 0x08000000 507 #define HRCWH_CORE_ENABLE 0x00000000 508 509 #define HRCWH_FROM_0X00000100 0x00000000 510 #define HRCWH_FROM_0XFFF00100 0x04000000 511 512 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 513 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 514 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 515 516 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 517 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 518 519 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 520 #define HRCWH_ROM_LOC_PCI1 0x00100000 521 #if defined(CONFIG_MPC834X) 522 #define HRCWH_ROM_LOC_PCI2 0x00200000 523 #endif 524 #if defined(CONIFG_MPC837X) 525 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 526 #endif 527 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 528 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 529 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 530 531 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 532 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 533 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 534 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 535 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 536 537 #define HRCWH_RL_EXT_LEGACY 0x00000000 538 #define HRCWH_RL_EXT_NAND 0x00040000 539 540 #define HRCWH_TSEC1M_IN_MII 0x00000000 541 #define HRCWH_TSEC1M_IN_RMII 0x00002000 542 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 543 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 544 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 545 546 #define HRCWH_TSEC2M_IN_MII 0x00000000 547 #define HRCWH_TSEC2M_IN_RMII 0x00000400 548 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 549 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 550 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 551 #endif 552 553 #if defined(CONFIG_MPC834X) 554 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 555 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 556 #define HRCWH_TSEC1M_IN_GMII 0x00008000 557 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 558 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 559 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 560 #define HRCWH_TSEC2M_IN_GMII 0x00002000 561 #define HRCWH_TSEC2M_IN_TBI 0x00003000 562 #endif 563 564 #if defined(CONFIG_MPC8360) 565 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 566 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 567 #endif 568 569 #define HRCWH_BIG_ENDIAN 0x00000000 570 #define HRCWH_LITTLE_ENDIAN 0x00000008 571 572 #define HRCWH_LALE_NORMAL 0x00000000 573 #define HRCWH_LALE_EARLY 0x00000004 574 575 #define HRCWH_LDP_SET 0x00000000 576 #define HRCWH_LDP_CLEAR 0x00000002 577 578 /* RSR - Reset Status Register 579 */ 580 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 581 #define RSR_RSTSRC 0xF0000000 /* Reset source */ 582 #define RSR_RSTSRC_SHIFT 28 583 #else 584 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 585 #define RSR_RSTSRC_SHIFT 29 586 #endif 587 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 588 #define RSR_BSF_SHIFT 16 589 #define RSR_SWSR 0x00002000 /* software soft reset */ 590 #define RSR_SWSR_SHIFT 13 591 #define RSR_SWHR 0x00001000 /* software hard reset */ 592 #define RSR_SWHR_SHIFT 12 593 #define RSR_JHRS 0x00000200 /* jtag hreset */ 594 #define RSR_JHRS_SHIFT 9 595 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 596 #define RSR_JSRS_SHIFT 8 597 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 598 #define RSR_CSHR_SHIFT 4 599 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 600 #define RSR_SWRS_SHIFT 3 601 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 602 #define RSR_BMRS_SHIFT 2 603 #define RSR_SRS 0x00000002 /* soft reset status */ 604 #define RSR_SRS_SHIFT 1 605 #define RSR_HRS 0x00000001 /* hard reset status */ 606 #define RSR_HRS_SHIFT 0 607 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 608 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 609 RSR_BMRS | RSR_SRS | RSR_HRS) 610 /* RMR - Reset Mode Register 611 */ 612 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 613 #define RMR_CSRE_SHIFT 0 614 #define RMR_RES ~(RMR_CSRE) 615 616 /* RCR - Reset Control Register 617 */ 618 #define RCR_SWHR 0x00000002 /* software hard reset */ 619 #define RCR_SWSR 0x00000001 /* software soft reset */ 620 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 621 622 /* RCER - Reset Control Enable Register 623 */ 624 #define RCER_CRE 0x00000001 /* software hard reset */ 625 #define RCER_RES ~(RCER_CRE) 626 627 /* SPMR - System PLL Mode Register 628 */ 629 #define SPMR_LBIUCM 0x80000000 630 #define SPMR_DDRCM 0x40000000 631 #define SPMR_SPMF 0x0F000000 632 #define SPMR_CKID 0x00800000 633 #define SPMR_CKID_SHIFT 23 634 #define SPMR_COREPLL 0x007F0000 635 #define SPMR_CEVCOD 0x000000C0 636 #define SPMR_CEPDF 0x00000020 637 #define SPMR_CEPMF 0x0000001F 638 639 /* OCCR - Output Clock Control Register 640 */ 641 #define OCCR_PCICOE0 0x80000000 642 #define OCCR_PCICOE1 0x40000000 643 #define OCCR_PCICOE2 0x20000000 644 #define OCCR_PCICOE3 0x10000000 645 #define OCCR_PCICOE4 0x08000000 646 #define OCCR_PCICOE5 0x04000000 647 #define OCCR_PCICOE6 0x02000000 648 #define OCCR_PCICOE7 0x01000000 649 #define OCCR_PCICD0 0x00800000 650 #define OCCR_PCICD1 0x00400000 651 #define OCCR_PCICD2 0x00200000 652 #define OCCR_PCICD3 0x00100000 653 #define OCCR_PCICD4 0x00080000 654 #define OCCR_PCICD5 0x00040000 655 #define OCCR_PCICD6 0x00020000 656 #define OCCR_PCICD7 0x00010000 657 #define OCCR_PCI1CR 0x00000002 658 #define OCCR_PCI2CR 0x00000001 659 #define OCCR_PCICR OCCR_PCI1CR 660 661 /* SCCR - System Clock Control Register 662 */ 663 #define SCCR_ENCCM 0x03000000 664 #define SCCR_ENCCM_SHIFT 24 665 #define SCCR_ENCCM_0 0x00000000 666 #define SCCR_ENCCM_1 0x01000000 667 #define SCCR_ENCCM_2 0x02000000 668 #define SCCR_ENCCM_3 0x03000000 669 670 #define SCCR_PCICM 0x00010000 671 #define SCCR_PCICM_SHIFT 16 672 673 #if defined(CONFIG_MPC834X) 674 /* SCCR bits - MPC834x specific */ 675 #define SCCR_TSEC1CM 0xc0000000 676 #define SCCR_TSEC1CM_SHIFT 30 677 #define SCCR_TSEC1CM_0 0x00000000 678 #define SCCR_TSEC1CM_1 0x40000000 679 #define SCCR_TSEC1CM_2 0x80000000 680 #define SCCR_TSEC1CM_3 0xC0000000 681 682 #define SCCR_TSEC2CM 0x30000000 683 #define SCCR_TSEC2CM_SHIFT 28 684 #define SCCR_TSEC2CM_0 0x00000000 685 #define SCCR_TSEC2CM_1 0x10000000 686 #define SCCR_TSEC2CM_2 0x20000000 687 #define SCCR_TSEC2CM_3 0x30000000 688 689 /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 690 #define SCCR_USBMPHCM 0x00c00000 691 #define SCCR_USBMPHCM_SHIFT 22 692 #define SCCR_USBDRCM 0x00300000 693 #define SCCR_USBDRCM_SHIFT 20 694 #define SCCR_USBCM 0x00f00000 695 #define SCCR_USBCM_SHIFT 20 696 #define SCCR_USBCM_0 0x00000000 697 #define SCCR_USBCM_1 0x00500000 698 #define SCCR_USBCM_2 0x00A00000 699 #define SCCR_USBCM_3 0x00F00000 700 701 #elif defined(CONFIG_MPC8313) 702 /* TSEC1 bits are for TSEC2 as well */ 703 #define SCCR_TSEC1CM 0xc0000000 704 #define SCCR_TSEC1CM_SHIFT 30 705 #define SCCR_TSEC1CM_0 0x00000000 706 #define SCCR_TSEC1CM_1 0x40000000 707 #define SCCR_TSEC1CM_2 0x80000000 708 #define SCCR_TSEC1CM_3 0xC0000000 709 710 #define SCCR_TSEC1ON 0x20000000 711 #define SCCR_TSEC1ON_SHIFT 29 712 #define SCCR_TSEC2ON 0x10000000 713 #define SCCR_TSEC2ON_SHIFT 28 714 715 #define SCCR_USBDRCM 0x00300000 716 #define SCCR_USBDRCM_SHIFT 20 717 #define SCCR_USBDRCM_0 0x00000000 718 #define SCCR_USBDRCM_1 0x00100000 719 #define SCCR_USBDRCM_2 0x00200000 720 #define SCCR_USBDRCM_3 0x00300000 721 722 #elif defined(CONFIG_MPC8315) 723 /* SCCR bits - MPC8315 specific */ 724 #define SCCR_TSEC1CM 0xc0000000 725 #define SCCR_TSEC1CM_SHIFT 30 726 #define SCCR_TSEC1CM_0 0x00000000 727 #define SCCR_TSEC1CM_1 0x40000000 728 #define SCCR_TSEC1CM_2 0x80000000 729 #define SCCR_TSEC1CM_3 0xC0000000 730 731 #define SCCR_TSEC2CM 0x30000000 732 #define SCCR_TSEC2CM_SHIFT 28 733 #define SCCR_TSEC2CM_0 0x00000000 734 #define SCCR_TSEC2CM_1 0x10000000 735 #define SCCR_TSEC2CM_2 0x20000000 736 #define SCCR_TSEC2CM_3 0x30000000 737 738 #define SCCR_USBDRCM 0x00c00000 739 #define SCCR_USBDRCM_SHIFT 22 740 #define SCCR_USBDRCM_0 0x00000000 741 #define SCCR_USBDRCM_1 0x00400000 742 #define SCCR_USBDRCM_2 0x00800000 743 #define SCCR_USBDRCM_3 0x00c00000 744 745 #define SCCR_PCIEXP1CM 0x00300000 746 #define SCCR_PCIEXP2CM 0x000c0000 747 748 #define SCCR_SATA1CM 0x00003000 749 #define SCCR_SATA1CM_SHIFT 12 750 #define SCCR_SATACM 0x00003c00 751 #define SCCR_SATACM_SHIFT 10 752 #define SCCR_SATACM_0 0x00000000 753 #define SCCR_SATACM_1 0x00001400 754 #define SCCR_SATACM_2 0x00002800 755 #define SCCR_SATACM_3 0x00003c00 756 757 #define SCCR_TDMCM 0x00000030 758 #define SCCR_TDMCM_SHIFT 4 759 #define SCCR_TDMCM_0 0x00000000 760 #define SCCR_TDMCM_1 0x00000010 761 #define SCCR_TDMCM_2 0x00000020 762 #define SCCR_TDMCM_3 0x00000030 763 764 #elif defined(CONFIG_MPC837X) 765 /* SCCR bits - MPC837x specific */ 766 #define SCCR_TSEC1CM 0xc0000000 767 #define SCCR_TSEC1CM_SHIFT 30 768 #define SCCR_TSEC1CM_0 0x00000000 769 #define SCCR_TSEC1CM_1 0x40000000 770 #define SCCR_TSEC1CM_2 0x80000000 771 #define SCCR_TSEC1CM_3 0xC0000000 772 773 #define SCCR_TSEC2CM 0x30000000 774 #define SCCR_TSEC2CM_SHIFT 28 775 #define SCCR_TSEC2CM_0 0x00000000 776 #define SCCR_TSEC2CM_1 0x10000000 777 #define SCCR_TSEC2CM_2 0x20000000 778 #define SCCR_TSEC2CM_3 0x30000000 779 780 #define SCCR_SDHCCM 0x0c000000 781 #define SCCR_SDHCCM_SHIFT 26 782 #define SCCR_SDHCCM_0 0x00000000 783 #define SCCR_SDHCCM_1 0x04000000 784 #define SCCR_SDHCCM_2 0x08000000 785 #define SCCR_SDHCCM_3 0x0c000000 786 787 #define SCCR_USBDRCM 0x00c00000 788 #define SCCR_USBDRCM_SHIFT 22 789 #define SCCR_USBDRCM_0 0x00000000 790 #define SCCR_USBDRCM_1 0x00400000 791 #define SCCR_USBDRCM_2 0x00800000 792 #define SCCR_USBDRCM_3 0x00c00000 793 794 #define SCCR_PCIEXP1CM 0x00300000 795 #define SCCR_PCIEXP1CM_SHIFT 20 796 #define SCCR_PCIEXP1CM_0 0x00000000 797 #define SCCR_PCIEXP1CM_1 0x00100000 798 #define SCCR_PCIEXP1CM_2 0x00200000 799 #define SCCR_PCIEXP1CM_3 0x00300000 800 801 #define SCCR_PCIEXP2CM 0x000c0000 802 #define SCCR_PCIEXP2CM_SHIFT 18 803 #define SCCR_PCIEXP2CM_0 0x00000000 804 #define SCCR_PCIEXP2CM_1 0x00040000 805 #define SCCR_PCIEXP2CM_2 0x00080000 806 #define SCCR_PCIEXP2CM_3 0x000c0000 807 808 /* All of the four SATA controllers must have the same clock ratio */ 809 #define SCCR_SATA1CM 0x000000c0 810 #define SCCR_SATA1CM_SHIFT 6 811 #define SCCR_SATACM 0x000000ff 812 #define SCCR_SATACM_SHIFT 0 813 #define SCCR_SATACM_0 0x00000000 814 #define SCCR_SATACM_1 0x00000055 815 #define SCCR_SATACM_2 0x000000aa 816 #define SCCR_SATACM_3 0x000000ff 817 #endif 818 819 /* CSn_BDNS - Chip Select memory Bounds Register 820 */ 821 #define CSBNDS_SA 0x00FF0000 822 #define CSBNDS_SA_SHIFT 8 823 #define CSBNDS_EA 0x000000FF 824 #define CSBNDS_EA_SHIFT 24 825 826 /* CSn_CONFIG - Chip Select Configuration Register 827 */ 828 #define CSCONFIG_EN 0x80000000 829 #define CSCONFIG_AP 0x00800000 830 #define CSCONFIG_ODT_WR_ACS 0x00010000 831 #define CSCONFIG_BANK_BIT_3 0x00004000 832 #define CSCONFIG_ROW_BIT 0x00000700 833 #define CSCONFIG_ROW_BIT_12 0x00000000 834 #define CSCONFIG_ROW_BIT_13 0x00000100 835 #define CSCONFIG_ROW_BIT_14 0x00000200 836 #define CSCONFIG_COL_BIT 0x00000007 837 #define CSCONFIG_COL_BIT_8 0x00000000 838 #define CSCONFIG_COL_BIT_9 0x00000001 839 #define CSCONFIG_COL_BIT_10 0x00000002 840 #define CSCONFIG_COL_BIT_11 0x00000003 841 842 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 843 */ 844 #define TIMING_CFG0_RWT 0xC0000000 845 #define TIMING_CFG0_RWT_SHIFT 30 846 #define TIMING_CFG0_WRT 0x30000000 847 #define TIMING_CFG0_WRT_SHIFT 28 848 #define TIMING_CFG0_RRT 0x0C000000 849 #define TIMING_CFG0_RRT_SHIFT 26 850 #define TIMING_CFG0_WWT 0x03000000 851 #define TIMING_CFG0_WWT_SHIFT 24 852 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 853 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 854 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 855 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 856 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 857 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 858 #define TIMING_CFG0_MRS_CYC 0x0000000F 859 #define TIMING_CFG0_MRS_CYC_SHIFT 0 860 861 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 862 */ 863 #define TIMING_CFG1_PRETOACT 0x70000000 864 #define TIMING_CFG1_PRETOACT_SHIFT 28 865 #define TIMING_CFG1_ACTTOPRE 0x0F000000 866 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 867 #define TIMING_CFG1_ACTTORW 0x00700000 868 #define TIMING_CFG1_ACTTORW_SHIFT 20 869 #define TIMING_CFG1_CASLAT 0x00070000 870 #define TIMING_CFG1_CASLAT_SHIFT 16 871 #define TIMING_CFG1_REFREC 0x0000F000 872 #define TIMING_CFG1_REFREC_SHIFT 12 873 #define TIMING_CFG1_WRREC 0x00000700 874 #define TIMING_CFG1_WRREC_SHIFT 8 875 #define TIMING_CFG1_ACTTOACT 0x00000070 876 #define TIMING_CFG1_ACTTOACT_SHIFT 4 877 #define TIMING_CFG1_WRTORD 0x00000007 878 #define TIMING_CFG1_WRTORD_SHIFT 0 879 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 880 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 881 #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ 882 883 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 884 */ 885 #define TIMING_CFG2_CPO 0x0F800000 886 #define TIMING_CFG2_CPO_SHIFT 23 887 #define TIMING_CFG2_ACSM 0x00080000 888 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 889 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 890 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 891 892 #define TIMING_CFG2_ADD_LAT 0x70000000 893 #define TIMING_CFG2_ADD_LAT_SHIFT 28 894 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 895 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 896 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 897 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 898 #define TIMING_CFG2_CKE_PLS 0x000001C0 899 #define TIMING_CFG2_CKE_PLS_SHIFT 6 900 #define TIMING_CFG2_FOUR_ACT 0x0000003F 901 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 902 903 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 904 */ 905 #define SDRAM_CFG_MEM_EN 0x80000000 906 #define SDRAM_CFG_SREN 0x40000000 907 #define SDRAM_CFG_ECC_EN 0x20000000 908 #define SDRAM_CFG_RD_EN 0x10000000 909 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 910 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 911 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 912 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 913 #define SDRAM_CFG_DYN_PWR 0x00200000 914 #define SDRAM_CFG_32_BE 0x00080000 915 #define SDRAM_CFG_8_BE 0x00040000 916 #define SDRAM_CFG_NCAP 0x00020000 917 #define SDRAM_CFG_2T_EN 0x00008000 918 #define SDRAM_CFG_BI 0x00000001 919 920 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 921 */ 922 #define SDRAM_MODE_ESD 0xFFFF0000 923 #define SDRAM_MODE_ESD_SHIFT 16 924 #define SDRAM_MODE_SD 0x0000FFFF 925 #define SDRAM_MODE_SD_SHIFT 0 926 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 927 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 928 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 929 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 930 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 931 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 932 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 933 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 934 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 935 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 936 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 937 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 938 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 939 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 940 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 941 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 942 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 943 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 944 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 945 946 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 947 */ 948 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 949 #define SDRAM_INTERVAL_REFINT_SHIFT 16 950 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 951 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 952 953 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 954 */ 955 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 956 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 957 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 958 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 959 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 960 961 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 962 */ 963 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 964 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 965 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 966 #define ECC_ERR_INJECT_EEIM_SHIFT 0 967 968 /* CAPTURE_ECC - Memory data path read capture ECC 969 */ 970 #define CAPTURE_ECC_ECE (0xff000000>>24) 971 #define CAPTURE_ECC_ECE_SHIFT 0 972 973 /* ERR_DETECT - Memory error detect 974 */ 975 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 976 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 977 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 978 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 979 980 /* ERR_DISABLE - Memory error disable 981 */ 982 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 983 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 984 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 985 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 986 ECC_ERROR_DISABLE_MBED) 987 /* ERR_INT_EN - Memory error interrupt enable 988 */ 989 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 990 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 991 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 992 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 993 ECC_ERR_INT_EN_MSEE) 994 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 995 */ 996 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 997 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 998 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 999 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1000 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1001 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1002 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1003 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1004 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1005 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1006 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1007 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1008 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1009 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1010 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1011 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1012 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1013 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1014 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1015 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1016 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1017 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1018 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1019 #define ECC_CAPT_ATTR_TTYP_READ 0x2 1020 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1021 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1022 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1023 1024 /* ERR_SBE - Single bit ECC memory error management 1025 */ 1026 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1027 #define ECC_ERROR_MAN_SBET_SHIFT 16 1028 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1029 #define ECC_ERROR_MAN_SBEC_SHIFT 0 1030 1031 /* DMAMR - DMA Mode Register 1032 */ 1033 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1034 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1035 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1036 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1037 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1038 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1039 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1040 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1041 1042 /* DMASR - DMA Status Register 1043 */ 1044 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1045 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 1046 1047 /* CONFIG_ADDRESS - PCI Config Address Register 1048 */ 1049 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1050 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1051 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1052 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1053 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1054 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1055 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1056 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1057 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1058 1059 /* POTAR - PCI Outbound Translation Address Register 1060 */ 1061 #define POTAR_TA_MASK 0x000fffff 1062 1063 /* POBAR - PCI Outbound Base Address Register 1064 */ 1065 #define POBAR_BA_MASK 0x000fffff 1066 1067 /* POCMR - PCI Outbound Comparision Mask Register 1068 */ 1069 #define POCMR_EN 0x80000000 1070 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1071 #define POCMR_SE 0x20000000 /* streaming enable */ 1072 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1073 #define POCMR_CM_MASK 0x000fffff 1074 #define POCMR_CM_4G 0x00000000 1075 #define POCMR_CM_2G 0x00080000 1076 #define POCMR_CM_1G 0x000C0000 1077 #define POCMR_CM_512M 0x000E0000 1078 #define POCMR_CM_256M 0x000F0000 1079 #define POCMR_CM_128M 0x000F8000 1080 #define POCMR_CM_64M 0x000FC000 1081 #define POCMR_CM_32M 0x000FE000 1082 #define POCMR_CM_16M 0x000FF000 1083 #define POCMR_CM_8M 0x000FF800 1084 #define POCMR_CM_4M 0x000FFC00 1085 #define POCMR_CM_2M 0x000FFE00 1086 #define POCMR_CM_1M 0x000FFF00 1087 #define POCMR_CM_512K 0x000FFF80 1088 #define POCMR_CM_256K 0x000FFFC0 1089 #define POCMR_CM_128K 0x000FFFE0 1090 #define POCMR_CM_64K 0x000FFFF0 1091 #define POCMR_CM_32K 0x000FFFF8 1092 #define POCMR_CM_16K 0x000FFFFC 1093 #define POCMR_CM_8K 0x000FFFFE 1094 #define POCMR_CM_4K 0x000FFFFF 1095 1096 /* PITAR - PCI Inbound Translation Address Register 1097 */ 1098 #define PITAR_TA_MASK 0x000fffff 1099 1100 /* PIBAR - PCI Inbound Base/Extended Address Register 1101 */ 1102 #define PIBAR_MASK 0xffffffff 1103 #define PIEBAR_EBA_MASK 0x000fffff 1104 1105 /* PIWAR - PCI Inbound Windows Attributes Register 1106 */ 1107 #define PIWAR_EN 0x80000000 1108 #define PIWAR_PF 0x20000000 1109 #define PIWAR_RTT_MASK 0x000f0000 1110 #define PIWAR_RTT_NO_SNOOP 0x00040000 1111 #define PIWAR_RTT_SNOOP 0x00050000 1112 #define PIWAR_WTT_MASK 0x0000f000 1113 #define PIWAR_WTT_NO_SNOOP 0x00004000 1114 #define PIWAR_WTT_SNOOP 0x00005000 1115 #define PIWAR_IWS_MASK 0x0000003F 1116 #define PIWAR_IWS_4K 0x0000000B 1117 #define PIWAR_IWS_8K 0x0000000C 1118 #define PIWAR_IWS_16K 0x0000000D 1119 #define PIWAR_IWS_32K 0x0000000E 1120 #define PIWAR_IWS_64K 0x0000000F 1121 #define PIWAR_IWS_128K 0x00000010 1122 #define PIWAR_IWS_256K 0x00000011 1123 #define PIWAR_IWS_512K 0x00000012 1124 #define PIWAR_IWS_1M 0x00000013 1125 #define PIWAR_IWS_2M 0x00000014 1126 #define PIWAR_IWS_4M 0x00000015 1127 #define PIWAR_IWS_8M 0x00000016 1128 #define PIWAR_IWS_16M 0x00000017 1129 #define PIWAR_IWS_32M 0x00000018 1130 #define PIWAR_IWS_64M 0x00000019 1131 #define PIWAR_IWS_128M 0x0000001A 1132 #define PIWAR_IWS_256M 0x0000001B 1133 #define PIWAR_IWS_512M 0x0000001C 1134 #define PIWAR_IWS_1G 0x0000001D 1135 #define PIWAR_IWS_2G 0x0000001E 1136 1137 /* PMCCR1 - PCI Configuration Register 1 1138 */ 1139 #define PMCCR1_POWER_OFF 0x00000020 1140 1141 /* FMR - Flash Mode Register 1142 */ 1143 #define FMR_CWTO 0x0000F000 1144 #define FMR_CWTO_SHIFT 12 1145 #define FMR_BOOT 0x00000800 1146 #define FMR_ECCM 0x00000100 1147 #define FMR_AL 0x00000030 1148 #define FMR_AL_SHIFT 4 1149 #define FMR_OP 0x00000003 1150 #define FMR_OP_SHIFT 0 1151 1152 /* FIR - Flash Instruction Register 1153 */ 1154 #define FIR_OP0 0xF0000000 1155 #define FIR_OP0_SHIFT 28 1156 #define FIR_OP1 0x0F000000 1157 #define FIR_OP1_SHIFT 24 1158 #define FIR_OP2 0x00F00000 1159 #define FIR_OP2_SHIFT 20 1160 #define FIR_OP3 0x000F0000 1161 #define FIR_OP3_SHIFT 16 1162 #define FIR_OP4 0x0000F000 1163 #define FIR_OP4_SHIFT 12 1164 #define FIR_OP5 0x00000F00 1165 #define FIR_OP5_SHIFT 8 1166 #define FIR_OP6 0x000000F0 1167 #define FIR_OP6_SHIFT 4 1168 #define FIR_OP7 0x0000000F 1169 #define FIR_OP7_SHIFT 0 1170 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1171 #define FIR_OP_CA 0x1 /* Issue current column address */ 1172 #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1173 #define FIR_OP_UA 0x3 /* Issue user defined address */ 1174 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1175 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1176 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1177 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1178 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1179 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1180 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1181 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1182 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1183 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1184 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1185 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1186 1187 /* FCR - Flash Command Register 1188 */ 1189 #define FCR_CMD0 0xFF000000 1190 #define FCR_CMD0_SHIFT 24 1191 #define FCR_CMD1 0x00FF0000 1192 #define FCR_CMD1_SHIFT 16 1193 #define FCR_CMD2 0x0000FF00 1194 #define FCR_CMD2_SHIFT 8 1195 #define FCR_CMD3 0x000000FF 1196 #define FCR_CMD3_SHIFT 0 1197 1198 /* FBAR - Flash Block Address Register 1199 */ 1200 #define FBAR_BLK 0x00FFFFFF 1201 1202 /* FPAR - Flash Page Address Register 1203 */ 1204 #define FPAR_SP_PI 0x00007C00 1205 #define FPAR_SP_PI_SHIFT 10 1206 #define FPAR_SP_MS 0x00000200 1207 #define FPAR_SP_CI 0x000001FF 1208 #define FPAR_SP_CI_SHIFT 0 1209 #define FPAR_LP_PI 0x0003F000 1210 #define FPAR_LP_PI_SHIFT 12 1211 #define FPAR_LP_MS 0x00000800 1212 #define FPAR_LP_CI 0x000007FF 1213 #define FPAR_LP_CI_SHIFT 0 1214 1215 /* LTESR - Transfer Error Status Register 1216 */ 1217 #define LTESR_BM 0x80000000 1218 #define LTESR_FCT 0x40000000 1219 #define LTESR_PAR 0x20000000 1220 #define LTESR_WP 0x04000000 1221 #define LTESR_ATMW 0x00800000 1222 #define LTESR_ATMR 0x00400000 1223 #define LTESR_CS 0x00080000 1224 #define LTESR_CC 0x00000001 1225 1226 /* DDRCDR - DDR Control Driver Register 1227 */ 1228 #define DDRCDR_DHC_EN 0x80000000 1229 #define DDRCDR_EN 0x40000000 1230 #define DDRCDR_PZ 0x3C000000 1231 #define DDRCDR_PZ_MAXZ 0x00000000 1232 #define DDRCDR_PZ_HIZ 0x20000000 1233 #define DDRCDR_PZ_NOMZ 0x30000000 1234 #define DDRCDR_PZ_LOZ 0x38000000 1235 #define DDRCDR_PZ_MINZ 0x3C000000 1236 #define DDRCDR_NZ 0x3C000000 1237 #define DDRCDR_NZ_MAXZ 0x00000000 1238 #define DDRCDR_NZ_HIZ 0x02000000 1239 #define DDRCDR_NZ_NOMZ 0x03000000 1240 #define DDRCDR_NZ_LOZ 0x03800000 1241 #define DDRCDR_NZ_MINZ 0x03C00000 1242 #define DDRCDR_ODT 0x00080000 1243 #define DDRCDR_DDR_CFG 0x00040000 1244 #define DDRCDR_M_ODR 0x00000002 1245 #define DDRCDR_Q_DRN 0x00000001 1246 1247 #ifndef __ASSEMBLY__ 1248 struct pci_region; 1249 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1250 #endif 1251 1252 #endif /* __MPC83XX_H__ */ 1253