xref: /rk3399_rockchip-uboot/include/mpc106.h (revision 326ea986ac150acdc7656d57fca647db80b50158)
11df49e27Swdenk /*
21df49e27Swdenk  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
31df49e27Swdenk  * Andreas Heppel <aheppel@sysgo.de>
41df49e27Swdenk  *
5*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
61df49e27Swdenk  */
71df49e27Swdenk 
81df49e27Swdenk #ifndef _MPC106_PCI_H
91df49e27Swdenk #define _MPC106_PCI_H
101df49e27Swdenk 
111df49e27Swdenk /*
121df49e27Swdenk  * Defines for the MPC106 PCI Config address and data registers followed by
131df49e27Swdenk  * defines for the standard PCI device configuration header.
141df49e27Swdenk  */
151df49e27Swdenk #define PCIDEVID_MPC106			0x0
161df49e27Swdenk 
171df49e27Swdenk /*
181df49e27Swdenk  * MPC106 Registers
191df49e27Swdenk  */
201df49e27Swdenk #define	MPC106_REG			0x80000000
211df49e27Swdenk 
226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_ADDRESS_MAP_A
231df49e27Swdenk #define MPC106_REG_ADDR			0x80000cf8
241df49e27Swdenk #define	MPC106_REG_DATA			0x80000cfc
251df49e27Swdenk #define MPC106_ISA_IO_PHYS		0x80000000
261df49e27Swdenk #define MPC106_ISA_IO_BUS		0x00000000
271df49e27Swdenk #define MPC106_ISA_IO_SIZE		0x00800000
281df49e27Swdenk #define MPC106_PCI_IO_PHYS		0x81000000
291df49e27Swdenk #define MPC106_PCI_IO_BUS		0x01000000
301df49e27Swdenk #define MPC106_PCI_IO_SIZE		0x3e800000
311df49e27Swdenk #define MPC106_PCI_MEM_PHYS		0xc0000000
321df49e27Swdenk #define MPC106_PCI_MEM_BUS		0x00000000
331df49e27Swdenk #define MPC106_PCI_MEM_SIZE		0x3f000000
341df49e27Swdenk #define	MPC106_PCI_MEMORY_PHYS		0x00000000
351df49e27Swdenk #define	MPC106_PCI_MEMORY_BUS		0x80000000
361df49e27Swdenk #define	MPC106_PCI_MEMORY_SIZE		0x80000000
371df49e27Swdenk #else
381df49e27Swdenk #define MPC106_REG_ADDR			0xfec00cf8
391df49e27Swdenk #define	MPC106_REG_DATA			0xfee00cfc
401df49e27Swdenk #define MPC106_ISA_MEM_PHYS		0xfd000000
411df49e27Swdenk #define MPC106_ISA_MEM_BUS		0x00000000
421df49e27Swdenk #define MPC106_ISA_MEM_SIZE		0x01000000
431df49e27Swdenk #define MPC106_ISA_IO_PHYS		0xfe000000
441df49e27Swdenk #define MPC106_ISA_IO_BUS		0x00000000
451df49e27Swdenk #define MPC106_ISA_IO_SIZE		0x00800000
461df49e27Swdenk #define MPC106_PCI_IO_PHYS		0xfe800000
471df49e27Swdenk #define MPC106_PCI_IO_BUS		0x00800000
481df49e27Swdenk #define MPC106_PCI_IO_SIZE		0x00400000
491df49e27Swdenk #define MPC106_PCI_MEM_PHYS		0x80000000
501df49e27Swdenk #define MPC106_PCI_MEM_BUS		0x80000000
511df49e27Swdenk #define MPC106_PCI_MEM_SIZE		0x7d000000
521df49e27Swdenk #define	MPC106_PCI_MEMORY_PHYS		0x00000000
531df49e27Swdenk #define	MPC106_PCI_MEMORY_BUS		0x00000000
541df49e27Swdenk #define MPC106_PCI_MEMORY_SIZE		0x40000000
551df49e27Swdenk #endif
561df49e27Swdenk 
571df49e27Swdenk #define CMD_SERR			0x0100
581df49e27Swdenk #define PCI_CMD_MASTER			0x0004
591df49e27Swdenk #define PCI_CMD_MEMEN			0x0002
601df49e27Swdenk #define PCI_CMD_IOEN			0x0001
611df49e27Swdenk 
621df49e27Swdenk #define PCI_STAT_NO_RSV_BITS		0xffff
631df49e27Swdenk 
641df49e27Swdenk #define PCI_BUSNUM			0x40
651df49e27Swdenk #define PCI_SUBBUSNUM			0x41
661df49e27Swdenk #define PCI_DISCOUNT			0x42
671df49e27Swdenk 
681df49e27Swdenk #define PCI_PICR1			0xA8
691df49e27Swdenk #define PICR1_CF_CBA(value)		((value & 0xff) << 24)
701df49e27Swdenk #define PICR1_CF_BREAD_WS(value)	((value & 0x3) << 22)
711df49e27Swdenk #define PICR1_PROC_TYPE_603		0x40000
721df49e27Swdenk #define PICR1_PROC_TYPE_604		0x60000
731df49e27Swdenk #define PICR1_MCP_EN			0x800
741df49e27Swdenk #define PICR1_CF_DPARK			0x200
751df49e27Swdenk #define PICR1_CF_LOOP_SNOOP		0x10
761df49e27Swdenk #define PICR1_CF_L2_COPY_BACK		0x2
771df49e27Swdenk #define PICR1_CF_L2_CACHE_MASK		0x3
781df49e27Swdenk #define PICR1_CF_APARK			0x8
791df49e27Swdenk #define PICR1_ADDRESS_MAP		0x10000
801df49e27Swdenk #define PICR1_XIO_MODE			0x80000
811df49e27Swdenk #define PICR1_CF_CACHE_1G		0x200000
821df49e27Swdenk 
831df49e27Swdenk #define PCI_PICR2			0xAC
841df49e27Swdenk #define PICR2_CF_SNOOP_WS(value)	((value & 0x3) << 18)
851df49e27Swdenk #define PICR2_CF_FLUSH_L2		0x10000000
861df49e27Swdenk #define PICR2_CF_L2_HIT_DELAY(value)	((value & 0x3) << 9)
871df49e27Swdenk #define PICR2_CF_APHASE_WS(value)	((value & 0x3) << 2)
881df49e27Swdenk #define PICR2_CF_INV_MODE		0x00001000
891df49e27Swdenk #define PICR2_CF_MOD_HIGH		0x00020000
901df49e27Swdenk #define PICR2_CF_HIT_HIGH		0x00010000
911df49e27Swdenk #define PICR2_L2_SIZE_256K		0x00000000
921df49e27Swdenk #define PICR2_L2_SIZE_512K		0x00000010
931df49e27Swdenk #define PICR2_L2_SIZE_1MB		0x00000020
941df49e27Swdenk #define PICR2_L2_EN			0x40000000
951df49e27Swdenk #define PICR2_L2_UPDATE_EN		0x80000000
961df49e27Swdenk #define PICR2_CF_ADDR_ONLY_DISABLE	0x00004000
971df49e27Swdenk #define PICR2_CF_FAST_CASTOUT		0x00000080
981df49e27Swdenk #define PICR2_CF_WDATA			0x00000001
991df49e27Swdenk #define PICR2_CF_DATA_RAM_PBURST	0x00400000
1001df49e27Swdenk 
1011df49e27Swdenk /*
1021df49e27Swdenk  * Memory controller
1031df49e27Swdenk  */
1041df49e27Swdenk #define MPC106_MCCR1			0xF0
1051df49e27Swdenk #define MCCR1_TYPE_EDO			0x00020000
1061df49e27Swdenk #define MCCR1_BK0_9BITS			0x0
1071df49e27Swdenk #define MCCR1_BK0_10BITS		0x1
1081df49e27Swdenk #define MCCR1_BK0_11BITS		0x2
1091df49e27Swdenk #define MCCR1_BK0_12BITS		0x3
1101df49e27Swdenk #define MCCR1_BK1_9BITS			0x0
1111df49e27Swdenk #define MCCR1_BK1_10BITS		0x4
1121df49e27Swdenk #define MCCR1_BK1_11BITS		0x8
1131df49e27Swdenk #define MCCR1_BK1_12BITS		0xC
1141df49e27Swdenk #define MCCR1_BK2_9BITS			0x00
1151df49e27Swdenk #define MCCR1_BK2_10BITS		0x10
1161df49e27Swdenk #define MCCR1_BK2_11BITS		0x20
1171df49e27Swdenk #define MCCR1_BK2_12BITS		0x30
1181df49e27Swdenk #define MCCR1_BK3_9BITS			0x00
1191df49e27Swdenk #define MCCR1_BK3_10BITS		0x40
1201df49e27Swdenk #define MCCR1_BK3_11BITS		0x80
1211df49e27Swdenk #define MCCR1_BK3_12BITS		0xC0
1221df49e27Swdenk #define MCCR1_MEMGO			0x00080000
1231df49e27Swdenk 
1241df49e27Swdenk #define MPC106_MCCR2			0xF4
1251df49e27Swdenk #define MPC106_MCCR3			0xF8
1261df49e27Swdenk #define MPC106_MCCR4			0xFC
1271df49e27Swdenk 
1281df49e27Swdenk #define MPC106_MSAR1			0x80
1291df49e27Swdenk #define MPC106_EMSAR1			0x88
1301df49e27Swdenk #define MPC106_EMSAR2			0x8C
1311df49e27Swdenk #define MPC106_MEAR1			0x90
1321df49e27Swdenk #define MPC106_EMEAR1			0x98
1331df49e27Swdenk #define MPC106_EMEAR2			0x9C
1341df49e27Swdenk 
1351df49e27Swdenk #define MPC106_MBER			0xA0
1361df49e27Swdenk #define MBER_BANK0			0x1
1371df49e27Swdenk #define MBER_BANK1			0x2
1381df49e27Swdenk #define MBER_BANK2			0x4
1391df49e27Swdenk #define MBER_BANK3			0x8
1401df49e27Swdenk 
1411df49e27Swdenk #endif
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