1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/sizes.h> 15 #include <linux/compiler.h> 16 #include <part.h> 17 18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 19 #define SD_VERSION_SD (1U << 31) 20 #define MMC_VERSION_MMC (1U << 30) 21 22 #define MAKE_SDMMC_VERSION(a, b, c) \ 23 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 24 #define MAKE_SD_VERSION(a, b, c) \ 25 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 26 #define MAKE_MMC_VERSION(a, b, c) \ 27 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 28 29 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 30 (((u32)(x) >> 16) & 0xff) 31 #define EXTRACT_SDMMC_MINOR_VERSION(x) \ 32 (((u32)(x) >> 8) & 0xff) 33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 34 ((u32)(x) & 0xff) 35 36 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 37 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 38 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 39 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 40 41 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 42 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 43 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 44 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 45 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 46 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 47 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 48 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 49 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 50 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 51 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 52 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 53 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) 54 55 #define MMC_MODE_HS (1 << 0) 56 #define MMC_MODE_HS_52MHz (1 << 1) 57 #define MMC_MODE_4BIT (1 << 2) 58 #define MMC_MODE_8BIT (1 << 3) 59 #define MMC_MODE_SPI (1 << 4) 60 #define MMC_MODE_DDR_52MHz (1 << 5) 61 #define MMC_MODE_HS200 (1 << 6) 62 #define MMC_MODE_HS400 (1 << 7) 63 #define MMC_MODE_HS400ES (1 << 8) 64 65 #define SD_DATA_4BIT 0x00040000 66 67 #define IS_SD(x) ((x)->version & SD_VERSION_SD) 68 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 69 70 #define MMC_DATA_READ 1 71 #define MMC_DATA_WRITE 2 72 73 #define MMC_CMD_GO_IDLE_STATE 0 74 #define MMC_CMD_SEND_OP_COND 1 75 #define MMC_CMD_ALL_SEND_CID 2 76 #define MMC_CMD_SET_RELATIVE_ADDR 3 77 #define MMC_CMD_SET_DSR 4 78 #define MMC_CMD_SWITCH 6 79 #define MMC_CMD_SELECT_CARD 7 80 #define MMC_CMD_SEND_EXT_CSD 8 81 #define MMC_CMD_SEND_CSD 9 82 #define MMC_CMD_SEND_CID 10 83 #define MMC_CMD_STOP_TRANSMISSION 12 84 #define MMC_CMD_SEND_STATUS 13 85 #define MMC_CMD_SET_BLOCKLEN 16 86 #define MMC_CMD_READ_SINGLE_BLOCK 17 87 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 88 #define MMC_SEND_TUNING_BLOCK 19 89 #define MMC_SEND_TUNING_BLOCK_HS200 21 90 #define MMC_CMD_SET_BLOCK_COUNT 23 91 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 92 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 93 #define MMC_CMD_ERASE_GROUP_START 35 94 #define MMC_CMD_ERASE_GROUP_END 36 95 #define MMC_CMD_ERASE 38 96 #define MMC_CMD_APP_CMD 55 97 #define MMC_CMD_SPI_READ_OCR 58 98 #define MMC_CMD_SPI_CRC_ON_OFF 59 99 #define MMC_CMD_RES_MAN 62 100 101 #define MMC_CMD62_ARG1 0xefac62ec 102 #define MMC_CMD62_ARG2 0xcbaea7 103 104 105 #define SD_CMD_SEND_RELATIVE_ADDR 3 106 #define SD_CMD_SWITCH_FUNC 6 107 #define SD_CMD_SEND_IF_COND 8 108 #define SD_CMD_SWITCH_UHS18V 11 109 110 #define SD_CMD_APP_SET_BUS_WIDTH 6 111 #define SD_CMD_APP_SD_STATUS 13 112 #define SD_CMD_ERASE_WR_BLK_START 32 113 #define SD_CMD_ERASE_WR_BLK_END 33 114 #define SD_CMD_APP_SEND_OP_COND 41 115 #define SD_CMD_APP_SEND_SCR 51 116 117 /* SCR definitions in different words */ 118 #define SD_HIGHSPEED_BUSY 0x00020000 119 #define SD_HIGHSPEED_SUPPORTED 0x00020000 120 121 #define OCR_BUSY 0x80000000 122 #define OCR_HCS 0x40000000 123 #define OCR_VOLTAGE_MASK 0x007FFF80 124 #define OCR_ACCESS_MODE 0x60000000 125 126 #define MMC_ERASE_ARG 0x00000000 127 #define MMC_SECURE_ERASE_ARG 0x80000000 128 #define MMC_TRIM_ARG 0x00000001 129 #define MMC_DISCARD_ARG 0x00000003 130 #define MMC_SECURE_TRIM1_ARG 0x80000001 131 #define MMC_SECURE_TRIM2_ARG 0x80008000 132 133 #define MMC_STATUS_MASK (~0x0206BF7F) 134 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 135 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 136 #define MMC_STATUS_CURR_STATE (0xf << 9) 137 #define MMC_STATUS_ERROR (1 << 19) 138 139 #define MMC_STATE_PRG (7 << 9) 140 141 #define MMC_VDD_165_195_SHIFT 7 142 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 143 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 144 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 145 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 146 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 147 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 148 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 149 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 150 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 151 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 152 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 153 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 154 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 155 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 156 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 157 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 158 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 159 160 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 161 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 162 addressed by index which are 163 1 in value field */ 164 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 165 addressed by index, which are 166 1 in value field */ 167 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 168 169 #define SD_SWITCH_CHECK 0 170 #define SD_SWITCH_SWITCH 1 171 172 /* 173 * EXT_CSD fields 174 */ 175 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 176 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 177 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 178 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 179 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 180 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 181 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 182 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 183 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ 184 #define EXT_CSD_WR_REL_PARAM 166 /* R */ 185 #define EXT_CSD_WR_REL_SET 167 /* R/W */ 186 #define EXT_CSD_RPMB_MULT 168 /* RO */ 187 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 188 #define EXT_CSD_BOOT_BUS_WIDTH 177 189 #define EXT_CSD_PART_CONF 179 /* R/W */ 190 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 191 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ 192 #define EXT_CSD_HS_TIMING 185 /* R/W */ 193 #define EXT_CSD_REV 192 /* RO */ 194 #define EXT_CSD_CARD_TYPE 196 /* RO */ 195 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 196 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 197 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 198 #define EXT_CSD_BOOT_MULT 226 /* RO */ 199 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 200 201 /* 202 * EXT_CSD field definitions 203 */ 204 205 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 206 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 207 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 208 209 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 210 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 211 #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \ 212 EXT_CSD_CARD_TYPE_52) 213 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ 214 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ 215 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 216 EXT_CSD_CARD_TYPE_HS200_1_2V) 217 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) /* Card can run at 200MHz DDR, 1.8V */ 218 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) /* Card can run at 200MHz DDR, 1.2V */ 219 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 220 EXT_CSD_CARD_TYPE_HS400_1_2V) 221 #define EXT_CSD_CARD_TYPE_HS400ES BIT(8) /* Card can run at HS400ES */ 222 223 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 224 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 225 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 226 | EXT_CSD_CARD_TYPE_DDR_1_2V) 227 228 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 229 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 230 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 231 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 232 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 233 234 #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ 235 #define EXT_CSD_TIMING_HS 1 /* High speed */ 236 #define EXT_CSD_TIMING_HS200 2 /* HS200 */ 237 #define EXT_CSD_TIMING_HS400 3 /* HS400 */ 238 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ 239 240 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 241 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 242 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 243 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 244 245 #define EXT_CSD_BOOT_ACK(x) (x << 6) 246 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 247 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 248 249 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) 250 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) 251 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) 252 253 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 254 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 255 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 256 257 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 258 259 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 260 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 261 262 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 263 264 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 265 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 266 267 #define R1_ILLEGAL_COMMAND (1 << 22) 268 #define R1_APP_CMD (1 << 5) 269 270 #define MMC_RSP_PRESENT (1 << 0) 271 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 272 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 273 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 274 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 275 276 #define MMC_RSP_NONE (0) 277 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 278 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 279 MMC_RSP_BUSY) 280 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 281 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 282 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 283 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 284 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 285 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 286 287 #define MMCPART_NOAVAILABLE (0xff) 288 #define PART_ACCESS_MASK (0x7) 289 #define PART_SUPPORT (0x1) 290 #define ENHNCD_SUPPORT (0x2) 291 #define PART_ENH_ATTRIB (0x1f) 292 293 /* Maximum block size for MMC */ 294 #define MMC_MAX_BLOCK_LEN 512 295 296 /* The number of MMC physical partitions. These consist of: 297 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 298 */ 299 #define MMC_NUM_BOOT_PARTITION 2 300 #define MMC_PART_RPMB 3 /* RPMB partition number */ 301 302 /* Sizes of RPMB data frame */ 303 #define RPMB_SZ_STUFF 196 304 #define RPMB_SZ_MAC 32 305 #define RPMB_SZ_DATA 256 306 #define RPMB_SZ_NONCE 16 307 308 /* Structure of RPMB data frame. */ 309 struct s_rpmb { 310 unsigned char stuff[RPMB_SZ_STUFF]; 311 unsigned char mac[RPMB_SZ_MAC]; 312 unsigned char data[RPMB_SZ_DATA]; 313 unsigned char nonce[RPMB_SZ_NONCE]; 314 unsigned int write_counter; 315 unsigned short address; 316 unsigned short block_count; 317 unsigned short result; 318 unsigned short request; 319 } __packed; 320 321 struct s_rpmb_verify { 322 unsigned char data[RPMB_SZ_DATA]; 323 unsigned char nonce[RPMB_SZ_NONCE]; 324 unsigned int write_counter; 325 unsigned short address; 326 unsigned short block_count; 327 unsigned short result; 328 unsigned short request; 329 } __packed; 330 331 int init_rpmb(void); 332 int finish_rpmb(void); 333 int do_readcounter(struct s_rpmb *requestpackets); 334 int do_programkey(struct s_rpmb *requestpackets); 335 int do_authenticatedread(struct s_rpmb *requestpackets, uint16_t block_count); 336 int do_authenticatedwrite(struct s_rpmb *requestpackets); 337 struct mmc *do_returnmmc(void); 338 339 int read_counter(struct mmc *mmc, struct s_rpmb *requestpackets); 340 int program_key(struct mmc *mmc, struct s_rpmb *requestpackets); 341 int authenticated_read 342 (struct mmc *mmc, struct s_rpmb *requestpackets, uint16_t block_count); 343 int authenticated_write(struct mmc *mmc, struct s_rpmb *requestpackets); 344 345 /* Driver model support */ 346 347 /** 348 * struct mmc_uclass_priv - Holds information about a device used by the uclass 349 */ 350 struct mmc_uclass_priv { 351 struct mmc *mmc; 352 }; 353 354 /** 355 * mmc_get_mmc_dev() - get the MMC struct pointer for a device 356 * 357 * Provided that the device is already probed and ready for use, this value 358 * will be available. 359 * 360 * @dev: Device 361 * @return associated mmc struct pointer if available, else NULL 362 */ 363 struct mmc *mmc_get_mmc_dev(struct udevice *dev); 364 365 /* End of driver model support */ 366 367 struct mmc_cid { 368 unsigned long psn; 369 unsigned short oid; 370 unsigned char mid; 371 unsigned char prv; 372 unsigned char mdt; 373 char pnm[7]; 374 }; 375 376 struct mmc_cmd { 377 ushort cmdidx; 378 uint resp_type; 379 uint cmdarg; 380 uint response[4]; 381 }; 382 383 struct mmc_data { 384 union { 385 char *dest; 386 const char *src; /* src buffers don't get written to */ 387 }; 388 uint flags; 389 uint blocks; 390 uint blocksize; 391 }; 392 393 /* forward decl. */ 394 struct mmc; 395 396 #if CONFIG_IS_ENABLED(DM_MMC) 397 struct dm_mmc_ops { 398 /** 399 * send_cmd() - Send a command to the MMC device 400 * 401 * @dev: Device to receive the command 402 * @cmd: Command to send 403 * @data: Additional data to send/receive 404 * @return 0 if OK, -ve on error 405 */ 406 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, 407 struct mmc_data *data); 408 409 /** 410 * card_busy() - Query the card device status 411 * 412 * @dev: Device to update 413 * @return true if card device is busy 414 */ 415 bool (*card_busy)(struct udevice *dev); 416 417 /** 418 * set_ios() - Set the I/O speed/width for an MMC device 419 * 420 * @dev: Device to update 421 * @return 0 if OK, -ve on error 422 */ 423 int (*set_ios)(struct udevice *dev); 424 425 /** 426 * get_cd() - See whether a card is present 427 * 428 * @dev: Device to check 429 * @return 0 if not present, 1 if present, -ve on error 430 */ 431 int (*get_cd)(struct udevice *dev); 432 433 /** 434 * get_wp() - See whether a card has write-protect enabled 435 * 436 * @dev: Device to check 437 * @return 0 if write-enabled, 1 if write-protected, -ve on error 438 */ 439 int (*get_wp)(struct udevice *dev); 440 441 /** 442 * execute_tuning() - Find the optimal sampling point of a data 443 * input signals. 444 * 445 * @dev: Device to check 446 * @opcode: The tuning command opcode value is different 447 * for SD and eMMC cards 448 * @return 0 if write-enabled, 1 if write-protected, -ve on error 449 */ 450 int (*execute_tuning)(struct udevice *dev, u32 opcode); 451 }; 452 453 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) 454 455 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 456 struct mmc_data *data); 457 int dm_mmc_set_ios(struct udevice *dev); 458 int dm_mmc_get_cd(struct udevice *dev); 459 int dm_mmc_get_wp(struct udevice *dev); 460 461 /* Transition functions for compatibility */ 462 bool mmc_card_busy(struct mmc *mmc); 463 bool mmc_can_card_busy(struct mmc *mmc); 464 int mmc_set_ios(struct mmc *mmc); 465 int mmc_getcd(struct mmc *mmc); 466 int mmc_getwp(struct mmc *mmc); 467 468 #else 469 struct mmc_ops { 470 bool (*card_busy)(struct mmc *mmc); 471 int (*send_cmd)(struct mmc *mmc, 472 struct mmc_cmd *cmd, struct mmc_data *data); 473 int (*set_ios)(struct mmc *mmc); 474 int (*init)(struct mmc *mmc); 475 int (*getcd)(struct mmc *mmc); 476 int (*getwp)(struct mmc *mmc); 477 int (*execute_tuning)(struct udevice *dev, u32 opcode); 478 }; 479 #endif 480 481 struct mmc_config { 482 const char *name; 483 #if !CONFIG_IS_ENABLED(DM_MMC) 484 const struct mmc_ops *ops; 485 #endif 486 uint host_caps; 487 uint voltages; 488 uint f_min; 489 uint f_max; 490 uint b_max; 491 unsigned char part_type; 492 }; 493 494 struct sd_ssr { 495 unsigned int au; /* In sectors */ 496 unsigned int erase_timeout; /* In milliseconds */ 497 unsigned int erase_offset; /* In milliseconds */ 498 }; 499 500 /* 501 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device 502 * with mmc_get_mmc_dev(). 503 * 504 * TODO struct mmc should be in mmc_private but it's hard to fix right now 505 */ 506 struct mmc { 507 #if !CONFIG_IS_ENABLED(BLK) 508 struct list_head link; 509 #endif 510 const struct mmc_config *cfg; /* provided configuration */ 511 uint version; 512 void *priv; 513 uint has_init; 514 int high_capacity; 515 uint bus_width; 516 517 #define MMC_BUS_WIDTH_1BIT 1 518 #define MMC_BUS_WIDTH_4BIT 4 519 #define MMC_BUS_WIDTH_8BIT 8 520 521 uint timing; 522 523 #define MMC_TIMING_LEGACY 0 524 #define MMC_TIMING_MMC_HS 1 525 #define MMC_TIMING_SD_HS 2 526 #define MMC_TIMING_UHS_SDR12 3 527 #define MMC_TIMING_UHS_SDR25 4 528 #define MMC_TIMING_UHS_SDR50 5 529 #define MMC_TIMING_UHS_SDR104 6 530 #define MMC_TIMING_UHS_DDR50 7 531 #define MMC_TIMING_MMC_DDR52 8 532 #define MMC_TIMING_MMC_HS200 9 533 #define MMC_TIMING_MMC_HS400 10 534 #define MMC_TIMING_MMC_HS400ES 11 535 536 uint clock; 537 538 #define MMC_HIGH_26_MAX_DTR 26000000 539 #define MMC_HIGH_52_MAX_DTR 52000000 540 #define MMC_HIGH_DDR_MAX_DTR 52000000 541 #define MMC_HS200_MAX_DTR 200000000 542 543 uint card_caps; 544 uint ocr; 545 uint dsr; 546 uint dsr_imp; 547 uint scr[2]; 548 uint csd[4]; 549 uint cid[4]; 550 ushort rca; 551 u8 part_support; 552 u8 part_attr; 553 u8 wr_rel_set; 554 u8 part_config; 555 uint read_bl_len; 556 uint write_bl_len; 557 uint erase_grp_size; /* in 512-byte sectors */ 558 uint hc_wp_grp_size; /* in 512-byte sectors */ 559 struct sd_ssr ssr; /* SD status register */ 560 u64 capacity; 561 u64 capacity_user; 562 u64 capacity_boot; 563 u64 capacity_rpmb; 564 u64 capacity_gp[4]; 565 u64 enh_user_start; 566 u64 enh_user_size; 567 #if !CONFIG_IS_ENABLED(BLK) 568 struct blk_desc block_dev; 569 #endif 570 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 571 char init_in_progress; /* 1 if we have done mmc_start_init() */ 572 char preinit; /* start init as early as possible */ 573 #if CONFIG_IS_ENABLED(DM_MMC) 574 struct udevice *dev; /* Device for this MMC controller */ 575 #endif 576 }; 577 578 struct mmc_hwpart_conf { 579 struct { 580 uint enh_start; /* in 512-byte sectors */ 581 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 582 unsigned wr_rel_change : 1; 583 unsigned wr_rel_set : 1; 584 } user; 585 struct { 586 uint size; /* in 512-byte sectors */ 587 unsigned enhanced : 1; 588 unsigned wr_rel_change : 1; 589 unsigned wr_rel_set : 1; 590 } gp_part[4]; 591 }; 592 593 enum mmc_hwpart_conf_mode { 594 MMC_HWPART_CONF_CHECK, 595 MMC_HWPART_CONF_SET, 596 MMC_HWPART_CONF_COMPLETE, 597 }; 598 599 static inline bool mmc_card_hs(struct mmc *mmc) 600 { 601 return (mmc->timing == MMC_TIMING_MMC_HS) || 602 (mmc->timing == MMC_TIMING_SD_HS); 603 } 604 605 static inline bool mmc_card_ddr(struct mmc *mmc) 606 { 607 return (mmc->timing == MMC_TIMING_UHS_DDR50) || 608 (mmc->timing == MMC_TIMING_MMC_DDR52) || 609 (mmc->timing == MMC_TIMING_MMC_HS400) || 610 (mmc->timing == MMC_TIMING_MMC_HS400ES); 611 } 612 613 static inline bool mmc_card_hs200(struct mmc *mmc) 614 { 615 return mmc->timing == MMC_TIMING_MMC_HS200; 616 } 617 618 static inline bool mmc_card_ddr52(struct mmc *mmc) 619 { 620 return mmc->timing == MMC_TIMING_MMC_DDR52; 621 } 622 623 static inline bool mmc_card_hs400(struct mmc *mmc) 624 { 625 return mmc->timing == MMC_TIMING_MMC_HS400; 626 } 627 628 static inline bool mmc_card_hs400es(struct mmc *mmc) 629 { 630 return mmc->timing == MMC_TIMING_MMC_HS400ES; 631 } 632 633 int mmc_send_tuning(struct mmc *mmc, u32 opcode); 634 635 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 636 637 /** 638 * mmc_bind() - Set up a new MMC device ready for probing 639 * 640 * A child block device is bound with the IF_TYPE_MMC interface type. This 641 * allows the device to be used with CONFIG_BLK 642 * 643 * @dev: MMC device to set up 644 * @mmc: MMC struct 645 * @cfg: MMC configuration 646 * @return 0 if OK, -ve on error 647 */ 648 int mmc_bind(struct udevice *dev, struct mmc *mmc, 649 const struct mmc_config *cfg); 650 void mmc_destroy(struct mmc *mmc); 651 652 /** 653 * mmc_unbind() - Unbind a MMC device's child block device 654 * 655 * @dev: MMC device 656 * @return 0 if OK, -ve on error 657 */ 658 int mmc_unbind(struct udevice *dev); 659 int mmc_initialize(bd_t *bis); 660 int mmc_init(struct mmc *mmc); 661 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 662 void mmc_set_clock(struct mmc *mmc, uint clock); 663 struct mmc *find_mmc_device(int dev_num); 664 int mmc_set_dev(int dev_num); 665 void print_mmc_devices(char separator); 666 667 /** 668 * get_mmc_num() - get the total MMC device number 669 * 670 * @return 0 if there is no MMC device, else the number of devices 671 */ 672 int get_mmc_num(void); 673 int mmc_switch_part(struct mmc *mmc, unsigned int part_num); 674 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 675 enum mmc_hwpart_conf_mode mode); 676 677 #if !CONFIG_IS_ENABLED(DM_MMC) 678 int mmc_getcd(struct mmc *mmc); 679 int board_mmc_getcd(struct mmc *mmc); 680 int mmc_getwp(struct mmc *mmc); 681 int board_mmc_getwp(struct mmc *mmc); 682 #endif 683 684 int mmc_set_dsr(struct mmc *mmc, u16 val); 685 /* Function to change the size of boot partition and rpmb partitions */ 686 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 687 unsigned long rpmbsize); 688 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 689 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 690 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 691 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 692 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 693 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 694 /* Functions to read / write the RPMB partition */ 695 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 696 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 697 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 698 unsigned short cnt, unsigned char *key); 699 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 700 unsigned short cnt, unsigned char *key); 701 #ifdef CONFIG_CMD_BKOPS_ENABLE 702 int mmc_set_bkops_enable(struct mmc *mmc); 703 #endif 704 705 /** 706 * Start device initialization and return immediately; it does not block on 707 * polling OCR (operation condition register) status. Then you should call 708 * mmc_init, which would block on polling OCR status and complete the device 709 * initializatin. 710 * 711 * @param mmc Pointer to a MMC device struct 712 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 713 */ 714 int mmc_start_init(struct mmc *mmc); 715 716 /** 717 * Set preinit flag of mmc device. 718 * 719 * This will cause the device to be pre-inited during mmc_initialize(), 720 * which may save boot time if the device is not accessed until later. 721 * Some eMMC devices take 200-300ms to init, but unfortunately they 722 * must be sent a series of commands to even get them to start preparing 723 * for operation. 724 * 725 * @param mmc Pointer to a MMC device struct 726 * @param preinit preinit flag value 727 */ 728 void mmc_set_preinit(struct mmc *mmc, int preinit); 729 730 #ifdef CONFIG_MMC_SPI 731 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 732 #else 733 #define mmc_host_is_spi(mmc) 0 734 #endif 735 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 736 737 void board_mmc_power_init(void); 738 int board_mmc_init(bd_t *bis); 739 int cpu_mmc_init(bd_t *bis); 740 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 741 int mmc_get_env_dev(void); 742 743 /* Set block count limit because of 16 bit register limit on some hardware*/ 744 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 745 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 746 #endif 747 748 /** 749 * mmc_get_blk_desc() - Get the block descriptor for an MMC device 750 * 751 * @mmc: MMC device 752 * @return block device if found, else NULL 753 */ 754 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); 755 756 #endif /* _MMC_H_ */ 757 758