1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/sizes.h> 15 #include <linux/compiler.h> 16 #include <part.h> 17 18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 19 #define SD_VERSION_SD (1U << 31) 20 #define MMC_VERSION_MMC (1U << 30) 21 22 #define MAKE_SDMMC_VERSION(a, b, c) \ 23 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 24 #define MAKE_SD_VERSION(a, b, c) \ 25 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 26 #define MAKE_MMC_VERSION(a, b, c) \ 27 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 28 29 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 30 (((u32)(x) >> 16) & 0xff) 31 #define EXTRACT_SDMMC_MINOR_VERSION(x) \ 32 (((u32)(x) >> 8) & 0xff) 33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 34 ((u32)(x) & 0xff) 35 36 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 37 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 38 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 39 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 40 41 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 42 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 43 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 44 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 45 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 46 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 47 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 48 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 49 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 50 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 51 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 52 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 53 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) 54 55 #define MMC_MODE_HS (1 << 0) 56 #define MMC_MODE_HS_52MHz (1 << 1) 57 #define MMC_MODE_4BIT (1 << 2) 58 #define MMC_MODE_8BIT (1 << 3) 59 #define MMC_MODE_SPI (1 << 4) 60 #define MMC_MODE_DDR_52MHz (1 << 5) 61 #define MMC_MODE_HS200 (1 << 6) 62 #define MMC_MODE_HS400 (1 << 7) 63 #define MMC_MODE_HS400ES (1 << 8) 64 65 #define SD_DATA_4BIT 0x00040000 66 67 #define IS_SD(x) ((x)->version & SD_VERSION_SD) 68 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 69 70 #define MMC_DATA_READ 1 71 #define MMC_DATA_WRITE 2 72 73 #define MMC_CMD_GO_IDLE_STATE 0 74 #define MMC_CMD_SEND_OP_COND 1 75 #define MMC_CMD_ALL_SEND_CID 2 76 #define MMC_CMD_SET_RELATIVE_ADDR 3 77 #define MMC_CMD_SET_DSR 4 78 #define MMC_CMD_SWITCH 6 79 #define MMC_CMD_SELECT_CARD 7 80 #define MMC_CMD_SEND_EXT_CSD 8 81 #define MMC_CMD_SEND_CSD 9 82 #define MMC_CMD_SEND_CID 10 83 #define MMC_CMD_STOP_TRANSMISSION 12 84 #define MMC_CMD_SEND_STATUS 13 85 #define MMC_CMD_SET_BLOCKLEN 16 86 #define MMC_CMD_READ_SINGLE_BLOCK 17 87 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 88 #define MMC_SEND_TUNING_BLOCK 19 89 #define MMC_SEND_TUNING_BLOCK_HS200 21 90 #define MMC_CMD_SET_BLOCK_COUNT 23 91 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 92 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 93 #define MMC_CMD_ERASE_GROUP_START 35 94 #define MMC_CMD_ERASE_GROUP_END 36 95 #define MMC_CMD_ERASE 38 96 #define MMC_CMD_APP_CMD 55 97 #define MMC_CMD_SPI_READ_OCR 58 98 #define MMC_CMD_SPI_CRC_ON_OFF 59 99 #define MMC_CMD_RES_MAN 62 100 101 #define MMC_CMD62_ARG1 0xefac62ec 102 #define MMC_CMD62_ARG2 0xcbaea7 103 104 105 #define SD_CMD_SEND_RELATIVE_ADDR 3 106 #define SD_CMD_SWITCH_FUNC 6 107 #define SD_CMD_SEND_IF_COND 8 108 #define SD_CMD_SWITCH_UHS18V 11 109 110 #define SD_CMD_APP_SET_BUS_WIDTH 6 111 #define SD_CMD_APP_SD_STATUS 13 112 #define SD_CMD_ERASE_WR_BLK_START 32 113 #define SD_CMD_ERASE_WR_BLK_END 33 114 #define SD_CMD_APP_SEND_OP_COND 41 115 #define SD_CMD_APP_SEND_SCR 51 116 117 /* SCR definitions in different words */ 118 #define SD_HIGHSPEED_BUSY 0x00020000 119 #define SD_HIGHSPEED_SUPPORTED 0x00020000 120 121 #define OCR_BUSY 0x80000000 122 #define OCR_HCS 0x40000000 123 #define OCR_VOLTAGE_MASK 0x007FFF80 124 #define OCR_ACCESS_MODE 0x60000000 125 126 #define MMC_ERASE_ARG 0x00000000 127 #define MMC_SECURE_ERASE_ARG 0x80000000 128 #define MMC_TRIM_ARG 0x00000001 129 #define MMC_DISCARD_ARG 0x00000003 130 #define MMC_SECURE_TRIM1_ARG 0x80000001 131 #define MMC_SECURE_TRIM2_ARG 0x80008000 132 133 #define MMC_STATUS_MASK (~0x0206BF7F) 134 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 135 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 136 #define MMC_STATUS_CURR_STATE (0xf << 9) 137 #define MMC_STATUS_ERROR (1 << 19) 138 139 #define MMC_STATE_PRG (7 << 9) 140 141 #define MMC_VDD_165_195_SHIFT 7 142 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 143 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 144 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 145 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 146 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 147 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 148 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 149 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 150 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 151 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 152 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 153 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 154 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 155 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 156 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 157 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 158 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 159 160 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 161 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 162 addressed by index which are 163 1 in value field */ 164 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 165 addressed by index, which are 166 1 in value field */ 167 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 168 169 #define SD_SWITCH_CHECK 0 170 #define SD_SWITCH_SWITCH 1 171 172 /* 173 * EXT_CSD fields 174 */ 175 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 176 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 177 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 178 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 179 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 180 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 181 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 182 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 183 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ 184 #define EXT_CSD_WR_REL_PARAM 166 /* R */ 185 #define EXT_CSD_WR_REL_SET 167 /* R/W */ 186 #define EXT_CSD_RPMB_MULT 168 /* RO */ 187 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 188 #define EXT_CSD_BOOT_BUS_WIDTH 177 189 #define EXT_CSD_PART_CONF 179 /* R/W */ 190 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 191 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ 192 #define EXT_CSD_HS_TIMING 185 /* R/W */ 193 #define EXT_CSD_REV 192 /* RO */ 194 #define EXT_CSD_CARD_TYPE 196 /* RO */ 195 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 196 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 197 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 198 #define EXT_CSD_BOOT_MULT 226 /* RO */ 199 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ 200 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 201 202 /* 203 * EXT_CSD field definitions 204 */ 205 206 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 207 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 208 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 209 210 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 211 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 212 #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \ 213 EXT_CSD_CARD_TYPE_52) 214 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ 215 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ 216 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 217 EXT_CSD_CARD_TYPE_HS200_1_2V) 218 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) /* Card can run at 200MHz DDR, 1.8V */ 219 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) /* Card can run at 200MHz DDR, 1.2V */ 220 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 221 EXT_CSD_CARD_TYPE_HS400_1_2V) 222 #define EXT_CSD_CARD_TYPE_HS400ES BIT(8) /* Card can run at HS400ES */ 223 224 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 225 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 226 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 227 | EXT_CSD_CARD_TYPE_DDR_1_2V) 228 229 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 230 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 231 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 232 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 233 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 234 235 #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ 236 #define EXT_CSD_TIMING_HS 1 /* High speed */ 237 #define EXT_CSD_TIMING_HS200 2 /* HS200 */ 238 #define EXT_CSD_TIMING_HS400 3 /* HS400 */ 239 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ 240 241 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 242 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 243 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 244 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 245 246 #define EXT_CSD_BOOT_ACK(x) (x << 6) 247 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 248 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 249 250 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) 251 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) 252 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) 253 254 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 255 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 256 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 257 258 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 259 260 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 261 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 262 263 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 264 265 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 266 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 267 268 #define R1_ILLEGAL_COMMAND (1 << 22) 269 #define R1_APP_CMD (1 << 5) 270 271 #define MMC_RSP_PRESENT (1 << 0) 272 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 273 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 274 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 275 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 276 277 #define EXT_CSD_SEC_ER_EN BIT(0) 278 #define EXT_CSD_SEC_BD_BLK_EN BIT(2) 279 #define EXT_CSD_SEC_GB_CL_EN BIT(4) 280 #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ 281 282 #define MMC_RSP_NONE (0) 283 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 284 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 285 MMC_RSP_BUSY) 286 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 287 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 288 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 289 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 290 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 291 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 292 293 #define MMCPART_NOAVAILABLE (0xff) 294 #define PART_ACCESS_MASK (0x7) 295 #define PART_SUPPORT (0x1) 296 #define ENHNCD_SUPPORT (0x2) 297 #define PART_ENH_ATTRIB (0x1f) 298 299 /* Maximum block size for MMC */ 300 #define MMC_MAX_BLOCK_LEN 512 301 302 /* The number of MMC physical partitions. These consist of: 303 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 304 */ 305 #define MMC_NUM_BOOT_PARTITION 2 306 #define MMC_PART_RPMB 3 /* RPMB partition number */ 307 308 /* Sizes of RPMB data frame */ 309 #define RPMB_SZ_STUFF 196 310 #define RPMB_SZ_MAC 32 311 #define RPMB_SZ_DATA 256 312 #define RPMB_SZ_NONCE 16 313 314 /* Structure of RPMB data frame. */ 315 struct s_rpmb { 316 unsigned char stuff[RPMB_SZ_STUFF]; 317 unsigned char mac[RPMB_SZ_MAC]; 318 unsigned char data[RPMB_SZ_DATA]; 319 unsigned char nonce[RPMB_SZ_NONCE]; 320 unsigned int write_counter; 321 unsigned short address; 322 unsigned short block_count; 323 unsigned short result; 324 unsigned short request; 325 } __packed; 326 327 struct s_rpmb_verify { 328 unsigned char data[RPMB_SZ_DATA]; 329 unsigned char nonce[RPMB_SZ_NONCE]; 330 unsigned int write_counter; 331 unsigned short address; 332 unsigned short block_count; 333 unsigned short result; 334 unsigned short request; 335 } __packed; 336 337 int init_rpmb(void); 338 int finish_rpmb(void); 339 int do_readcounter(struct s_rpmb *requestpackets); 340 int do_programkey(struct s_rpmb *requestpackets); 341 int do_authenticatedread(struct s_rpmb *requestpackets, uint16_t block_count); 342 int do_authenticatedwrite(struct s_rpmb *requestpackets); 343 struct mmc *do_returnmmc(void); 344 345 int read_counter(struct mmc *mmc, struct s_rpmb *requestpackets); 346 int program_key(struct mmc *mmc, struct s_rpmb *requestpackets); 347 int authenticated_read 348 (struct mmc *mmc, struct s_rpmb *requestpackets, uint16_t block_count); 349 int authenticated_write(struct mmc *mmc, struct s_rpmb *requestpackets); 350 351 /* Driver model support */ 352 353 /** 354 * struct mmc_uclass_priv - Holds information about a device used by the uclass 355 */ 356 struct mmc_uclass_priv { 357 struct mmc *mmc; 358 }; 359 360 struct emmc_esr { 361 unsigned int mmc_can_trim; 362 }; 363 364 /** 365 * mmc_get_mmc_dev() - get the MMC struct pointer for a device 366 * 367 * Provided that the device is already probed and ready for use, this value 368 * will be available. 369 * 370 * @dev: Device 371 * @return associated mmc struct pointer if available, else NULL 372 */ 373 struct mmc *mmc_get_mmc_dev(struct udevice *dev); 374 375 /* End of driver model support */ 376 377 struct mmc_cid { 378 unsigned long psn; 379 unsigned short oid; 380 unsigned char mid; 381 unsigned char prv; 382 unsigned char mdt; 383 char pnm[7]; 384 }; 385 386 struct mmc_cmd { 387 ushort cmdidx; 388 uint resp_type; 389 uint cmdarg; 390 uint response[4]; 391 }; 392 393 struct mmc_data { 394 union { 395 char *dest; 396 const char *src; /* src buffers don't get written to */ 397 }; 398 uint flags; 399 uint blocks; 400 uint blocksize; 401 }; 402 403 /* forward decl. */ 404 struct mmc; 405 406 #if CONFIG_IS_ENABLED(DM_MMC) 407 struct dm_mmc_ops { 408 /** 409 * send_cmd() - Send a command to the MMC device 410 * 411 * @dev: Device to receive the command 412 * @cmd: Command to send 413 * @data: Additional data to send/receive 414 * @return 0 if OK, -ve on error 415 */ 416 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, 417 struct mmc_data *data); 418 419 /** 420 * card_busy() - Query the card device status 421 * 422 * @dev: Device to update 423 * @return true if card device is busy 424 */ 425 bool (*card_busy)(struct udevice *dev); 426 427 /** 428 * set_ios() - Set the I/O speed/width for an MMC device 429 * 430 * @dev: Device to update 431 * @return 0 if OK, -ve on error 432 */ 433 int (*set_ios)(struct udevice *dev); 434 435 /** 436 * get_cd() - See whether a card is present 437 * 438 * @dev: Device to check 439 * @return 0 if not present, 1 if present, -ve on error 440 */ 441 int (*get_cd)(struct udevice *dev); 442 443 /** 444 * get_wp() - See whether a card has write-protect enabled 445 * 446 * @dev: Device to check 447 * @return 0 if write-enabled, 1 if write-protected, -ve on error 448 */ 449 int (*get_wp)(struct udevice *dev); 450 451 /** 452 * execute_tuning() - Find the optimal sampling point of a data 453 * input signals. 454 * 455 * @dev: Device to check 456 * @opcode: The tuning command opcode value is different 457 * for SD and eMMC cards 458 * @return 0 if write-enabled, 1 if write-protected, -ve on error 459 */ 460 int (*execute_tuning)(struct udevice *dev, u32 opcode); 461 }; 462 463 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) 464 465 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 466 struct mmc_data *data); 467 int dm_mmc_set_ios(struct udevice *dev); 468 int dm_mmc_get_cd(struct udevice *dev); 469 int dm_mmc_get_wp(struct udevice *dev); 470 471 /* Transition functions for compatibility */ 472 bool mmc_card_busy(struct mmc *mmc); 473 bool mmc_can_card_busy(struct mmc *mmc); 474 int mmc_set_ios(struct mmc *mmc); 475 int mmc_getcd(struct mmc *mmc); 476 int mmc_getwp(struct mmc *mmc); 477 478 #else 479 struct mmc_ops { 480 bool (*card_busy)(struct mmc *mmc); 481 int (*send_cmd)(struct mmc *mmc, 482 struct mmc_cmd *cmd, struct mmc_data *data); 483 int (*set_ios)(struct mmc *mmc); 484 int (*init)(struct mmc *mmc); 485 int (*getcd)(struct mmc *mmc); 486 int (*getwp)(struct mmc *mmc); 487 int (*execute_tuning)(struct udevice *dev, u32 opcode); 488 }; 489 #endif 490 491 struct mmc_config { 492 const char *name; 493 #if !CONFIG_IS_ENABLED(DM_MMC) 494 const struct mmc_ops *ops; 495 #endif 496 uint host_caps; 497 uint voltages; 498 uint f_min; 499 uint f_max; 500 uint b_max; 501 unsigned char part_type; 502 }; 503 504 struct sd_ssr { 505 unsigned int au; /* In sectors */ 506 unsigned int erase_timeout; /* In milliseconds */ 507 unsigned int erase_offset; /* In milliseconds */ 508 }; 509 510 /* 511 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device 512 * with mmc_get_mmc_dev(). 513 * 514 * TODO struct mmc should be in mmc_private but it's hard to fix right now 515 */ 516 struct mmc { 517 #if !CONFIG_IS_ENABLED(BLK) 518 struct list_head link; 519 #endif 520 const struct mmc_config *cfg; /* provided configuration */ 521 uint version; 522 void *priv; 523 uint has_init; 524 int high_capacity; 525 uint bus_width; 526 527 #define MMC_BUS_WIDTH_1BIT 1 528 #define MMC_BUS_WIDTH_4BIT 4 529 #define MMC_BUS_WIDTH_8BIT 8 530 531 uint timing; 532 533 #define MMC_TIMING_LEGACY 0 534 #define MMC_TIMING_MMC_HS 1 535 #define MMC_TIMING_SD_HS 2 536 #define MMC_TIMING_UHS_SDR12 3 537 #define MMC_TIMING_UHS_SDR25 4 538 #define MMC_TIMING_UHS_SDR50 5 539 #define MMC_TIMING_UHS_SDR104 6 540 #define MMC_TIMING_UHS_DDR50 7 541 #define MMC_TIMING_MMC_DDR52 8 542 #define MMC_TIMING_MMC_HS200 9 543 #define MMC_TIMING_MMC_HS400 10 544 #define MMC_TIMING_MMC_HS400ES 11 545 546 uint clock; 547 548 #define MMC_HIGH_26_MAX_DTR 26000000 549 #define MMC_HIGH_52_MAX_DTR 52000000 550 #define MMC_HIGH_DDR_MAX_DTR 52000000 551 #define MMC_HS200_MAX_DTR 200000000 552 553 uint card_caps; 554 uint ocr; 555 uint dsr; 556 uint dsr_imp; 557 uint scr[2]; 558 uint csd[4]; 559 uint cid[4]; 560 ushort rca; 561 u8 part_support; 562 u8 part_attr; 563 u8 wr_rel_set; 564 u8 part_config; 565 uint read_bl_len; 566 uint write_bl_len; 567 uint erase_grp_size; /* in 512-byte sectors */ 568 uint hc_wp_grp_size; /* in 512-byte sectors */ 569 int default_phase; /* set the default sample clock phase */ 570 uint init_retry; /* re-init mmc when error occur */ 571 struct sd_ssr ssr; /* SD status register */ 572 struct emmc_esr esr; /* emmc status register */ 573 u64 capacity; 574 u64 capacity_user; 575 u64 capacity_boot; 576 u64 capacity_rpmb; 577 u64 capacity_gp[4]; 578 u64 enh_user_start; 579 u64 enh_user_size; 580 #if !CONFIG_IS_ENABLED(BLK) 581 struct blk_desc block_dev; 582 #endif 583 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 584 char init_in_progress; /* 1 if we have done mmc_start_init() */ 585 char preinit; /* start init as early as possible */ 586 #if CONFIG_IS_ENABLED(DM_MMC) 587 struct udevice *dev; /* Device for this MMC controller */ 588 #endif 589 }; 590 591 struct mmc_hwpart_conf { 592 struct { 593 uint enh_start; /* in 512-byte sectors */ 594 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 595 unsigned wr_rel_change : 1; 596 unsigned wr_rel_set : 1; 597 } user; 598 struct { 599 uint size; /* in 512-byte sectors */ 600 unsigned enhanced : 1; 601 unsigned wr_rel_change : 1; 602 unsigned wr_rel_set : 1; 603 } gp_part[4]; 604 }; 605 606 enum mmc_hwpart_conf_mode { 607 MMC_HWPART_CONF_CHECK, 608 MMC_HWPART_CONF_SET, 609 MMC_HWPART_CONF_COMPLETE, 610 }; 611 612 static inline bool mmc_card_hs(struct mmc *mmc) 613 { 614 return (mmc->timing == MMC_TIMING_MMC_HS) || 615 (mmc->timing == MMC_TIMING_SD_HS); 616 } 617 618 static inline bool mmc_card_ddr(struct mmc *mmc) 619 { 620 return (mmc->timing == MMC_TIMING_UHS_DDR50) || 621 (mmc->timing == MMC_TIMING_MMC_DDR52) || 622 (mmc->timing == MMC_TIMING_MMC_HS400) || 623 (mmc->timing == MMC_TIMING_MMC_HS400ES); 624 } 625 626 static inline bool mmc_card_hs200(struct mmc *mmc) 627 { 628 return mmc->timing == MMC_TIMING_MMC_HS200; 629 } 630 631 static inline bool mmc_card_ddr52(struct mmc *mmc) 632 { 633 return mmc->timing == MMC_TIMING_MMC_DDR52; 634 } 635 636 static inline bool mmc_card_hs400(struct mmc *mmc) 637 { 638 return mmc->timing == MMC_TIMING_MMC_HS400; 639 } 640 641 static inline bool mmc_card_hs400es(struct mmc *mmc) 642 { 643 return mmc->timing == MMC_TIMING_MMC_HS400ES; 644 } 645 646 int mmc_send_tuning(struct mmc *mmc, u32 opcode); 647 648 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 649 650 /** 651 * mmc_bind() - Set up a new MMC device ready for probing 652 * 653 * A child block device is bound with the IF_TYPE_MMC interface type. This 654 * allows the device to be used with CONFIG_BLK 655 * 656 * @dev: MMC device to set up 657 * @mmc: MMC struct 658 * @cfg: MMC configuration 659 * @return 0 if OK, -ve on error 660 */ 661 int mmc_bind(struct udevice *dev, struct mmc *mmc, 662 const struct mmc_config *cfg); 663 void mmc_destroy(struct mmc *mmc); 664 665 /** 666 * mmc_unbind() - Unbind a MMC device's child block device 667 * 668 * @dev: MMC device 669 * @return 0 if OK, -ve on error 670 */ 671 int mmc_unbind(struct udevice *dev); 672 int mmc_initialize(bd_t *bis); 673 int mmc_init(struct mmc *mmc); 674 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 675 void mmc_set_clock(struct mmc *mmc, uint clock); 676 struct mmc *find_mmc_device(int dev_num); 677 int mmc_set_dev(int dev_num); 678 void print_mmc_devices(char separator); 679 680 /** 681 * get_mmc_num() - get the total MMC device number 682 * 683 * @return 0 if there is no MMC device, else the number of devices 684 */ 685 int get_mmc_num(void); 686 int mmc_switch_part(struct mmc *mmc, unsigned int part_num); 687 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 688 enum mmc_hwpart_conf_mode mode); 689 690 #if !CONFIG_IS_ENABLED(DM_MMC) 691 int mmc_getcd(struct mmc *mmc); 692 int board_mmc_getcd(struct mmc *mmc); 693 int mmc_getwp(struct mmc *mmc); 694 int board_mmc_getwp(struct mmc *mmc); 695 #endif 696 697 int mmc_set_dsr(struct mmc *mmc, u16 val); 698 /* Function to change the size of boot partition and rpmb partitions */ 699 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 700 unsigned long rpmbsize); 701 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 702 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 703 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 704 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 705 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 706 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 707 /* Functions to read / write the RPMB partition */ 708 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 709 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 710 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 711 unsigned short cnt, unsigned char *key); 712 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 713 unsigned short cnt, unsigned char *key); 714 #ifdef CONFIG_CMD_BKOPS_ENABLE 715 int mmc_set_bkops_enable(struct mmc *mmc); 716 #endif 717 718 /** 719 * Start device initialization and return immediately; it does not block on 720 * polling OCR (operation condition register) status. Then you should call 721 * mmc_init, which would block on polling OCR status and complete the device 722 * initializatin. 723 * 724 * @param mmc Pointer to a MMC device struct 725 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 726 */ 727 int mmc_start_init(struct mmc *mmc); 728 729 /** 730 * Set preinit flag of mmc device. 731 * 732 * This will cause the device to be pre-inited during mmc_initialize(), 733 * which may save boot time if the device is not accessed until later. 734 * Some eMMC devices take 200-300ms to init, but unfortunately they 735 * must be sent a series of commands to even get them to start preparing 736 * for operation. 737 * 738 * @param mmc Pointer to a MMC device struct 739 * @param preinit preinit flag value 740 */ 741 void mmc_set_preinit(struct mmc *mmc, int preinit); 742 743 #ifdef CONFIG_MMC_SPI 744 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 745 #else 746 #define mmc_host_is_spi(mmc) 0 747 #endif 748 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 749 750 void board_mmc_power_init(void); 751 int board_mmc_init(bd_t *bis); 752 int cpu_mmc_init(bd_t *bis); 753 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 754 int mmc_get_env_dev(void); 755 756 /* Set block count limit because of 16 bit register limit on some hardware*/ 757 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 758 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 759 #endif 760 761 /** 762 * mmc_get_blk_desc() - Get the block descriptor for an MMC device 763 * 764 * @mmc: MMC device 765 * @return block device if found, else NULL 766 */ 767 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); 768 769 #endif /* _MMC_H_ */ 770 771