1 /* 2 * Copyright 2008,2010 Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based (loosely) on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _MMC_H_ 11 #define _MMC_H_ 12 13 #include <linux/list.h> 14 #include <linux/sizes.h> 15 #include <linux/compiler.h> 16 #include <part.h> 17 18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ 19 #define SD_VERSION_SD (1U << 31) 20 #define MMC_VERSION_MMC (1U << 30) 21 22 #define MAKE_SDMMC_VERSION(a, b, c) \ 23 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) 24 #define MAKE_SD_VERSION(a, b, c) \ 25 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) 26 #define MAKE_MMC_VERSION(a, b, c) \ 27 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) 28 29 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ 30 (((u32)(x) >> 16) & 0xff) 31 #define EXTRACT_SDMMC_MINOR_VERSION(x) \ 32 (((u32)(x) >> 8) & 0xff) 33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ 34 ((u32)(x) & 0xff) 35 36 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) 37 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) 38 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) 39 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) 40 41 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) 42 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) 43 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) 44 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) 45 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) 46 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) 47 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) 48 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) 49 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) 50 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) 51 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) 52 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) 53 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) 54 55 #define MMC_MODE_HS (1 << 0) 56 #define MMC_MODE_HS_52MHz (1 << 1) 57 #define MMC_MODE_4BIT (1 << 2) 58 #define MMC_MODE_8BIT (1 << 3) 59 #define MMC_MODE_SPI (1 << 4) 60 #define MMC_MODE_DDR_52MHz (1 << 5) 61 #define MMC_MODE_HS200 (1 << 6) 62 #define MMC_MODE_HS400 (1 << 7) 63 #define MMC_MODE_HS400ES (1 << 8) 64 65 #define SD_DATA_4BIT 0x00040000 66 67 #define IS_SD(x) ((x)->version & SD_VERSION_SD) 68 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) 69 70 #define MMC_DATA_READ 1 71 #define MMC_DATA_WRITE 2 72 73 #define MMC_CMD_GO_IDLE_STATE 0 74 #define MMC_CMD_SEND_OP_COND 1 75 #define MMC_CMD_ALL_SEND_CID 2 76 #define MMC_CMD_SET_RELATIVE_ADDR 3 77 #define MMC_CMD_SET_DSR 4 78 #define MMC_CMD_SWITCH 6 79 #define MMC_CMD_SELECT_CARD 7 80 #define MMC_CMD_SEND_EXT_CSD 8 81 #define MMC_CMD_SEND_CSD 9 82 #define MMC_CMD_SEND_CID 10 83 #define MMC_CMD_STOP_TRANSMISSION 12 84 #define MMC_CMD_SEND_STATUS 13 85 #define MMC_CMD_SET_BLOCKLEN 16 86 #define MMC_CMD_READ_SINGLE_BLOCK 17 87 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 88 #define MMC_CMD_SET_BLOCK_COUNT 23 89 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 90 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 91 #define MMC_CMD_ERASE_GROUP_START 35 92 #define MMC_CMD_ERASE_GROUP_END 36 93 #define MMC_CMD_ERASE 38 94 #define MMC_CMD_APP_CMD 55 95 #define MMC_CMD_SPI_READ_OCR 58 96 #define MMC_CMD_SPI_CRC_ON_OFF 59 97 #define MMC_CMD_RES_MAN 62 98 99 #define MMC_CMD62_ARG1 0xefac62ec 100 #define MMC_CMD62_ARG2 0xcbaea7 101 102 103 #define SD_CMD_SEND_RELATIVE_ADDR 3 104 #define SD_CMD_SWITCH_FUNC 6 105 #define SD_CMD_SEND_IF_COND 8 106 #define SD_CMD_SWITCH_UHS18V 11 107 108 #define SD_CMD_APP_SET_BUS_WIDTH 6 109 #define SD_CMD_APP_SD_STATUS 13 110 #define SD_CMD_ERASE_WR_BLK_START 32 111 #define SD_CMD_ERASE_WR_BLK_END 33 112 #define SD_CMD_APP_SEND_OP_COND 41 113 #define SD_CMD_APP_SEND_SCR 51 114 115 /* SCR definitions in different words */ 116 #define SD_HIGHSPEED_BUSY 0x00020000 117 #define SD_HIGHSPEED_SUPPORTED 0x00020000 118 119 #define OCR_BUSY 0x80000000 120 #define OCR_HCS 0x40000000 121 #define OCR_VOLTAGE_MASK 0x007FFF80 122 #define OCR_ACCESS_MODE 0x60000000 123 124 #define MMC_ERASE_ARG 0x00000000 125 #define MMC_SECURE_ERASE_ARG 0x80000000 126 #define MMC_TRIM_ARG 0x00000001 127 #define MMC_DISCARD_ARG 0x00000003 128 #define MMC_SECURE_TRIM1_ARG 0x80000001 129 #define MMC_SECURE_TRIM2_ARG 0x80008000 130 131 #define MMC_STATUS_MASK (~0x0206BF7F) 132 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 133 #define MMC_STATUS_RDY_FOR_DATA (1 << 8) 134 #define MMC_STATUS_CURR_STATE (0xf << 9) 135 #define MMC_STATUS_ERROR (1 << 19) 136 137 #define MMC_STATE_PRG (7 << 9) 138 139 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 140 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 141 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 142 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 143 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 144 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 145 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 146 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 147 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 148 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 149 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 150 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 151 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 152 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 153 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 154 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 155 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 156 157 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 158 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 159 addressed by index which are 160 1 in value field */ 161 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 162 addressed by index, which are 163 1 in value field */ 164 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 165 166 #define SD_SWITCH_CHECK 0 167 #define SD_SWITCH_SWITCH 1 168 169 /* 170 * EXT_CSD fields 171 */ 172 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ 173 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ 174 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 175 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ 176 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ 177 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ 178 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ 179 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 180 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ 181 #define EXT_CSD_WR_REL_PARAM 166 /* R */ 182 #define EXT_CSD_WR_REL_SET 167 /* R/W */ 183 #define EXT_CSD_RPMB_MULT 168 /* RO */ 184 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 185 #define EXT_CSD_BOOT_BUS_WIDTH 177 186 #define EXT_CSD_PART_CONF 179 /* R/W */ 187 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 188 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ 189 #define EXT_CSD_HS_TIMING 185 /* R/W */ 190 #define EXT_CSD_REV 192 /* RO */ 191 #define EXT_CSD_CARD_TYPE 196 /* RO */ 192 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 193 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 194 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 195 #define EXT_CSD_BOOT_MULT 226 /* RO */ 196 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 197 198 /* 199 * EXT_CSD field definitions 200 */ 201 202 #define EXT_CSD_CMD_SET_NORMAL (1 << 0) 203 #define EXT_CSD_CMD_SET_SECURE (1 << 1) 204 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) 205 206 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ 207 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ 208 #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \ 209 EXT_CSD_CARD_TYPE_52) 210 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ 211 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ 212 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 213 EXT_CSD_CARD_TYPE_HS200_1_2V) 214 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) /* Card can run at 200MHz DDR, 1.8V */ 215 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) /* Card can run at 200MHz DDR, 1.2V */ 216 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 217 EXT_CSD_CARD_TYPE_HS400_1_2V) 218 #define EXT_CSD_CARD_TYPE_HS400ES BIT(8) /* Card can run at HS400ES */ 219 220 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) 221 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) 222 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 223 | EXT_CSD_CARD_TYPE_DDR_1_2V) 224 225 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 226 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 227 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 228 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 229 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 230 231 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) 232 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) 233 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) 234 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) 235 236 #define EXT_CSD_BOOT_ACK(x) (x << 6) 237 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) 238 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) 239 240 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) 241 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) 242 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) 243 244 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) 245 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) 246 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) 247 248 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) 249 250 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ 251 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ 252 253 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ 254 255 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ 256 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ 257 258 #define R1_ILLEGAL_COMMAND (1 << 22) 259 #define R1_APP_CMD (1 << 5) 260 261 #define MMC_RSP_PRESENT (1 << 0) 262 #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 263 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 264 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 265 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 266 267 #define MMC_RSP_NONE (0) 268 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 269 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 270 MMC_RSP_BUSY) 271 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 272 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 273 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 274 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 275 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 276 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 277 278 #define MMCPART_NOAVAILABLE (0xff) 279 #define PART_ACCESS_MASK (0x7) 280 #define PART_SUPPORT (0x1) 281 #define ENHNCD_SUPPORT (0x2) 282 #define PART_ENH_ATTRIB (0x1f) 283 284 /* Maximum block size for MMC */ 285 #define MMC_MAX_BLOCK_LEN 512 286 287 /* The number of MMC physical partitions. These consist of: 288 * boot partitions (2), general purpose partitions (4) in MMC v4.4. 289 */ 290 #define MMC_NUM_BOOT_PARTITION 2 291 #define MMC_PART_RPMB 3 /* RPMB partition number */ 292 293 /* Driver model support */ 294 295 /** 296 * struct mmc_uclass_priv - Holds information about a device used by the uclass 297 */ 298 struct mmc_uclass_priv { 299 struct mmc *mmc; 300 }; 301 302 /** 303 * mmc_get_mmc_dev() - get the MMC struct pointer for a device 304 * 305 * Provided that the device is already probed and ready for use, this value 306 * will be available. 307 * 308 * @dev: Device 309 * @return associated mmc struct pointer if available, else NULL 310 */ 311 struct mmc *mmc_get_mmc_dev(struct udevice *dev); 312 313 /* End of driver model support */ 314 315 struct mmc_cid { 316 unsigned long psn; 317 unsigned short oid; 318 unsigned char mid; 319 unsigned char prv; 320 unsigned char mdt; 321 char pnm[7]; 322 }; 323 324 struct mmc_cmd { 325 ushort cmdidx; 326 uint resp_type; 327 uint cmdarg; 328 uint response[4]; 329 }; 330 331 struct mmc_data { 332 union { 333 char *dest; 334 const char *src; /* src buffers don't get written to */ 335 }; 336 uint flags; 337 uint blocks; 338 uint blocksize; 339 }; 340 341 /* forward decl. */ 342 struct mmc; 343 344 #if CONFIG_IS_ENABLED(DM_MMC) 345 struct dm_mmc_ops { 346 /** 347 * send_cmd() - Send a command to the MMC device 348 * 349 * @dev: Device to receive the command 350 * @cmd: Command to send 351 * @data: Additional data to send/receive 352 * @return 0 if OK, -ve on error 353 */ 354 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, 355 struct mmc_data *data); 356 357 /** 358 * set_ios() - Set the I/O speed/width for an MMC device 359 * 360 * @dev: Device to update 361 * @return 0 if OK, -ve on error 362 */ 363 int (*set_ios)(struct udevice *dev); 364 365 /** 366 * get_cd() - See whether a card is present 367 * 368 * @dev: Device to check 369 * @return 0 if not present, 1 if present, -ve on error 370 */ 371 int (*get_cd)(struct udevice *dev); 372 373 /** 374 * get_wp() - See whether a card has write-protect enabled 375 * 376 * @dev: Device to check 377 * @return 0 if write-enabled, 1 if write-protected, -ve on error 378 */ 379 int (*get_wp)(struct udevice *dev); 380 }; 381 382 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) 383 384 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 385 struct mmc_data *data); 386 int dm_mmc_set_ios(struct udevice *dev); 387 int dm_mmc_get_cd(struct udevice *dev); 388 int dm_mmc_get_wp(struct udevice *dev); 389 390 /* Transition functions for compatibility */ 391 int mmc_set_ios(struct mmc *mmc); 392 int mmc_getcd(struct mmc *mmc); 393 int mmc_getwp(struct mmc *mmc); 394 395 #else 396 struct mmc_ops { 397 int (*send_cmd)(struct mmc *mmc, 398 struct mmc_cmd *cmd, struct mmc_data *data); 399 int (*set_ios)(struct mmc *mmc); 400 int (*init)(struct mmc *mmc); 401 int (*getcd)(struct mmc *mmc); 402 int (*getwp)(struct mmc *mmc); 403 }; 404 #endif 405 406 struct mmc_config { 407 const char *name; 408 #if !CONFIG_IS_ENABLED(DM_MMC) 409 const struct mmc_ops *ops; 410 #endif 411 uint host_caps; 412 uint voltages; 413 uint f_min; 414 uint f_max; 415 uint b_max; 416 unsigned char part_type; 417 }; 418 419 struct sd_ssr { 420 unsigned int au; /* In sectors */ 421 unsigned int erase_timeout; /* In milliseconds */ 422 unsigned int erase_offset; /* In milliseconds */ 423 }; 424 425 /* 426 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device 427 * with mmc_get_mmc_dev(). 428 * 429 * TODO struct mmc should be in mmc_private but it's hard to fix right now 430 */ 431 struct mmc { 432 #if !CONFIG_IS_ENABLED(BLK) 433 struct list_head link; 434 #endif 435 const struct mmc_config *cfg; /* provided configuration */ 436 uint version; 437 void *priv; 438 uint has_init; 439 int high_capacity; 440 uint bus_width; 441 uint clock; 442 uint card_caps; 443 uint ocr; 444 uint dsr; 445 uint dsr_imp; 446 uint scr[2]; 447 uint csd[4]; 448 uint cid[4]; 449 ushort rca; 450 u8 part_support; 451 u8 part_attr; 452 u8 wr_rel_set; 453 u8 part_config; 454 uint tran_speed; 455 uint read_bl_len; 456 uint write_bl_len; 457 uint erase_grp_size; /* in 512-byte sectors */ 458 uint hc_wp_grp_size; /* in 512-byte sectors */ 459 struct sd_ssr ssr; /* SD status register */ 460 u64 capacity; 461 u64 capacity_user; 462 u64 capacity_boot; 463 u64 capacity_rpmb; 464 u64 capacity_gp[4]; 465 u64 enh_user_start; 466 u64 enh_user_size; 467 #if !CONFIG_IS_ENABLED(BLK) 468 struct blk_desc block_dev; 469 #endif 470 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 471 char init_in_progress; /* 1 if we have done mmc_start_init() */ 472 char preinit; /* start init as early as possible */ 473 int ddr_mode; 474 #if CONFIG_IS_ENABLED(DM_MMC) 475 struct udevice *dev; /* Device for this MMC controller */ 476 #endif 477 }; 478 479 struct mmc_hwpart_conf { 480 struct { 481 uint enh_start; /* in 512-byte sectors */ 482 uint enh_size; /* in 512-byte sectors, if 0 no enh area */ 483 unsigned wr_rel_change : 1; 484 unsigned wr_rel_set : 1; 485 } user; 486 struct { 487 uint size; /* in 512-byte sectors */ 488 unsigned enhanced : 1; 489 unsigned wr_rel_change : 1; 490 unsigned wr_rel_set : 1; 491 } gp_part[4]; 492 }; 493 494 enum mmc_hwpart_conf_mode { 495 MMC_HWPART_CONF_CHECK, 496 MMC_HWPART_CONF_SET, 497 MMC_HWPART_CONF_COMPLETE, 498 }; 499 500 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); 501 502 /** 503 * mmc_bind() - Set up a new MMC device ready for probing 504 * 505 * A child block device is bound with the IF_TYPE_MMC interface type. This 506 * allows the device to be used with CONFIG_BLK 507 * 508 * @dev: MMC device to set up 509 * @mmc: MMC struct 510 * @cfg: MMC configuration 511 * @return 0 if OK, -ve on error 512 */ 513 int mmc_bind(struct udevice *dev, struct mmc *mmc, 514 const struct mmc_config *cfg); 515 void mmc_destroy(struct mmc *mmc); 516 517 /** 518 * mmc_unbind() - Unbind a MMC device's child block device 519 * 520 * @dev: MMC device 521 * @return 0 if OK, -ve on error 522 */ 523 int mmc_unbind(struct udevice *dev); 524 int mmc_initialize(bd_t *bis); 525 int mmc_init(struct mmc *mmc); 526 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 527 void mmc_set_clock(struct mmc *mmc, uint clock); 528 struct mmc *find_mmc_device(int dev_num); 529 int mmc_set_dev(int dev_num); 530 void print_mmc_devices(char separator); 531 532 /** 533 * get_mmc_num() - get the total MMC device number 534 * 535 * @return 0 if there is no MMC device, else the number of devices 536 */ 537 int get_mmc_num(void); 538 int mmc_switch_part(struct mmc *mmc, unsigned int part_num); 539 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, 540 enum mmc_hwpart_conf_mode mode); 541 542 #if !CONFIG_IS_ENABLED(DM_MMC) 543 int mmc_getcd(struct mmc *mmc); 544 int board_mmc_getcd(struct mmc *mmc); 545 int mmc_getwp(struct mmc *mmc); 546 int board_mmc_getwp(struct mmc *mmc); 547 #endif 548 549 int mmc_set_dsr(struct mmc *mmc, u16 val); 550 /* Function to change the size of boot partition and rpmb partitions */ 551 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 552 unsigned long rpmbsize); 553 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ 554 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); 555 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ 556 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); 557 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ 558 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); 559 /* Functions to read / write the RPMB partition */ 560 int mmc_rpmb_set_key(struct mmc *mmc, void *key); 561 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); 562 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, 563 unsigned short cnt, unsigned char *key); 564 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, 565 unsigned short cnt, unsigned char *key); 566 #ifdef CONFIG_CMD_BKOPS_ENABLE 567 int mmc_set_bkops_enable(struct mmc *mmc); 568 #endif 569 570 /** 571 * Start device initialization and return immediately; it does not block on 572 * polling OCR (operation condition register) status. Then you should call 573 * mmc_init, which would block on polling OCR status and complete the device 574 * initializatin. 575 * 576 * @param mmc Pointer to a MMC device struct 577 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. 578 */ 579 int mmc_start_init(struct mmc *mmc); 580 581 /** 582 * Set preinit flag of mmc device. 583 * 584 * This will cause the device to be pre-inited during mmc_initialize(), 585 * which may save boot time if the device is not accessed until later. 586 * Some eMMC devices take 200-300ms to init, but unfortunately they 587 * must be sent a series of commands to even get them to start preparing 588 * for operation. 589 * 590 * @param mmc Pointer to a MMC device struct 591 * @param preinit preinit flag value 592 */ 593 void mmc_set_preinit(struct mmc *mmc, int preinit); 594 595 #ifdef CONFIG_MMC_SPI 596 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) 597 #else 598 #define mmc_host_is_spi(mmc) 0 599 #endif 600 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); 601 602 void board_mmc_power_init(void); 603 int board_mmc_init(bd_t *bis); 604 int cpu_mmc_init(bd_t *bis); 605 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); 606 int mmc_get_env_dev(void); 607 608 /* Set block count limit because of 16 bit register limit on some hardware*/ 609 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT 610 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 611 #endif 612 613 /** 614 * mmc_get_blk_desc() - Get the block descriptor for an MMC device 615 * 616 * @mmc: MMC device 617 * @return block device if found, else NULL 618 */ 619 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); 620 621 #endif /* _MMC_H_ */ 622