171f95118Swdenk /* 24a6ee172SJerry Huang * Copyright 2008,2010 Freescale Semiconductor, Inc 3272cc70bSAndy Fleming * Andy Fleming 4272cc70bSAndy Fleming * 5272cc70bSAndy Fleming * Based (loosely) on the Linux code 671f95118Swdenk * 771f95118Swdenk * See file CREDITS for list of people who contributed to this 871f95118Swdenk * project. 971f95118Swdenk * 1071f95118Swdenk * This program is free software; you can redistribute it and/or 1171f95118Swdenk * modify it under the terms of the GNU General Public License as 1271f95118Swdenk * published by the Free Software Foundation; either version 2 of 1371f95118Swdenk * the License, or (at your option) any later version. 1471f95118Swdenk * 1571f95118Swdenk * This program is distributed in the hope that it will be useful, 1671f95118Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 1771f95118Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1871f95118Swdenk * GNU General Public License for more details. 1971f95118Swdenk * 2071f95118Swdenk * You should have received a copy of the GNU General Public License 2171f95118Swdenk * along with this program; if not, write to the Free Software 2271f95118Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2371f95118Swdenk * MA 02111-1307 USA 2471f95118Swdenk */ 2571f95118Swdenk 2671f95118Swdenk #ifndef _MMC_H_ 2771f95118Swdenk #define _MMC_H_ 2871f95118Swdenk 29272cc70bSAndy Fleming #include <linux/list.h> 30272cc70bSAndy Fleming 31272cc70bSAndy Fleming #define SD_VERSION_SD 0x20000 32272cc70bSAndy Fleming #define SD_VERSION_2 (SD_VERSION_SD | 0x20) 33272cc70bSAndy Fleming #define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) 34272cc70bSAndy Fleming #define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) 35272cc70bSAndy Fleming #define MMC_VERSION_MMC 0x10000 36272cc70bSAndy Fleming #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) 37272cc70bSAndy Fleming #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) 38272cc70bSAndy Fleming #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) 39272cc70bSAndy Fleming #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) 40272cc70bSAndy Fleming #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) 41272cc70bSAndy Fleming #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) 42272cc70bSAndy Fleming 43272cc70bSAndy Fleming #define MMC_MODE_HS 0x001 44272cc70bSAndy Fleming #define MMC_MODE_HS_52MHz 0x010 45272cc70bSAndy Fleming #define MMC_MODE_4BIT 0x100 46272cc70bSAndy Fleming #define MMC_MODE_8BIT 0x200 47272cc70bSAndy Fleming 48272cc70bSAndy Fleming #define SD_DATA_4BIT 0x00040000 49272cc70bSAndy Fleming 5079b91de9SAlbin Tonnerre #define IS_SD(x) (x->version & SD_VERSION_SD) 51272cc70bSAndy Fleming 52272cc70bSAndy Fleming #define MMC_DATA_READ 1 53272cc70bSAndy Fleming #define MMC_DATA_WRITE 2 54272cc70bSAndy Fleming 55272cc70bSAndy Fleming #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ 56272cc70bSAndy Fleming #define UNUSABLE_ERR -17 /* Unusable Card */ 57272cc70bSAndy Fleming #define COMM_ERR -18 /* Communications Error */ 58272cc70bSAndy Fleming #define TIMEOUT -19 59272cc70bSAndy Fleming 60341188b9SHaavard Skinnemoen #define MMC_CMD_GO_IDLE_STATE 0 61341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_OP_COND 1 62341188b9SHaavard Skinnemoen #define MMC_CMD_ALL_SEND_CID 2 63341188b9SHaavard Skinnemoen #define MMC_CMD_SET_RELATIVE_ADDR 3 64341188b9SHaavard Skinnemoen #define MMC_CMD_SET_DSR 4 65272cc70bSAndy Fleming #define MMC_CMD_SWITCH 6 66341188b9SHaavard Skinnemoen #define MMC_CMD_SELECT_CARD 7 67272cc70bSAndy Fleming #define MMC_CMD_SEND_EXT_CSD 8 68341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_CSD 9 69341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_CID 10 70272cc70bSAndy Fleming #define MMC_CMD_STOP_TRANSMISSION 12 71341188b9SHaavard Skinnemoen #define MMC_CMD_SEND_STATUS 13 72341188b9SHaavard Skinnemoen #define MMC_CMD_SET_BLOCKLEN 16 73341188b9SHaavard Skinnemoen #define MMC_CMD_READ_SINGLE_BLOCK 17 74341188b9SHaavard Skinnemoen #define MMC_CMD_READ_MULTIPLE_BLOCK 18 75272cc70bSAndy Fleming #define MMC_CMD_WRITE_SINGLE_BLOCK 24 76272cc70bSAndy Fleming #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 77341188b9SHaavard Skinnemoen #define MMC_CMD_APP_CMD 55 78341188b9SHaavard Skinnemoen 79341188b9SHaavard Skinnemoen #define SD_CMD_SEND_RELATIVE_ADDR 3 80272cc70bSAndy Fleming #define SD_CMD_SWITCH_FUNC 6 81341188b9SHaavard Skinnemoen #define SD_CMD_SEND_IF_COND 8 82341188b9SHaavard Skinnemoen 83341188b9SHaavard Skinnemoen #define SD_CMD_APP_SET_BUS_WIDTH 6 84341188b9SHaavard Skinnemoen #define SD_CMD_APP_SEND_OP_COND 41 85272cc70bSAndy Fleming #define SD_CMD_APP_SEND_SCR 51 86272cc70bSAndy Fleming 87272cc70bSAndy Fleming /* SCR definitions in different words */ 88272cc70bSAndy Fleming #define SD_HIGHSPEED_BUSY 0x00020000 89272cc70bSAndy Fleming #define SD_HIGHSPEED_SUPPORTED 0x00020000 90272cc70bSAndy Fleming 91272cc70bSAndy Fleming #define MMC_HS_TIMING 0x00000100 92272cc70bSAndy Fleming #define MMC_HS_52MHZ 0x2 93272cc70bSAndy Fleming 940b453ffeSRabin Vincent #define OCR_BUSY 0x80000000 95272cc70bSAndy Fleming #define OCR_HCS 0x40000000 96272cc70bSAndy Fleming 97272cc70bSAndy Fleming #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 98272cc70bSAndy Fleming #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 99272cc70bSAndy Fleming #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 100272cc70bSAndy Fleming #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 101272cc70bSAndy Fleming #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 102272cc70bSAndy Fleming #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 103272cc70bSAndy Fleming #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 104272cc70bSAndy Fleming #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 105272cc70bSAndy Fleming #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 106272cc70bSAndy Fleming #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 107272cc70bSAndy Fleming #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 108272cc70bSAndy Fleming #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 109272cc70bSAndy Fleming #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 110272cc70bSAndy Fleming #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 111272cc70bSAndy Fleming #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 112272cc70bSAndy Fleming #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 113272cc70bSAndy Fleming #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 114272cc70bSAndy Fleming 115272cc70bSAndy Fleming #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 116272cc70bSAndy Fleming #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte 117272cc70bSAndy Fleming addressed by index which are 118272cc70bSAndy Fleming 1 in value field */ 119272cc70bSAndy Fleming #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte 120272cc70bSAndy Fleming addressed by index, which are 121272cc70bSAndy Fleming 1 in value field */ 122272cc70bSAndy Fleming #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ 123272cc70bSAndy Fleming 124272cc70bSAndy Fleming #define SD_SWITCH_CHECK 0 125272cc70bSAndy Fleming #define SD_SWITCH_SWITCH 1 126272cc70bSAndy Fleming 127272cc70bSAndy Fleming /* 128272cc70bSAndy Fleming * EXT_CSD fields 129272cc70bSAndy Fleming */ 130272cc70bSAndy Fleming 131272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 132272cc70bSAndy Fleming #define EXT_CSD_HS_TIMING 185 /* R/W */ 133272cc70bSAndy Fleming #define EXT_CSD_CARD_TYPE 196 /* RO */ 134272cc70bSAndy Fleming #define EXT_CSD_REV 192 /* RO */ 135272cc70bSAndy Fleming #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 136272cc70bSAndy Fleming 137272cc70bSAndy Fleming /* 138272cc70bSAndy Fleming * EXT_CSD field definitions 139272cc70bSAndy Fleming */ 140272cc70bSAndy Fleming 141272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_NORMAL (1<<0) 142272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_SECURE (1<<1) 143272cc70bSAndy Fleming #define EXT_CSD_CMD_SET_CPSECURE (1<<2) 144272cc70bSAndy Fleming 145272cc70bSAndy Fleming #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ 146272cc70bSAndy Fleming #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ 147272cc70bSAndy Fleming 148272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 149272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 150272cc70bSAndy Fleming #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 151341188b9SHaavard Skinnemoen 1521de97f98SAndy Fleming #define R1_ILLEGAL_COMMAND (1 << 22) 1531de97f98SAndy Fleming #define R1_APP_CMD (1 << 5) 1541de97f98SAndy Fleming 155272cc70bSAndy Fleming #define MMC_RSP_PRESENT (1 << 0) 156272cc70bSAndy Fleming #define MMC_RSP_136 (1 << 1) /* 136 bit response */ 157272cc70bSAndy Fleming #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ 158272cc70bSAndy Fleming #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ 159272cc70bSAndy Fleming #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ 160272cc70bSAndy Fleming 161272cc70bSAndy Fleming #define MMC_RSP_NONE (0) 162272cc70bSAndy Fleming #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 163272cc70bSAndy Fleming #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ 164272cc70bSAndy Fleming MMC_RSP_BUSY) 165272cc70bSAndy Fleming #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) 166272cc70bSAndy Fleming #define MMC_RSP_R3 (MMC_RSP_PRESENT) 167272cc70bSAndy Fleming #define MMC_RSP_R4 (MMC_RSP_PRESENT) 168272cc70bSAndy Fleming #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 169272cc70bSAndy Fleming #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 170272cc70bSAndy Fleming #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) 171272cc70bSAndy Fleming 17271f95118Swdenk 1731de97f98SAndy Fleming struct mmc_cid { 1741de97f98SAndy Fleming unsigned long psn; 1751de97f98SAndy Fleming unsigned short oid; 1761de97f98SAndy Fleming unsigned char mid; 1771de97f98SAndy Fleming unsigned char prv; 1781de97f98SAndy Fleming unsigned char mdt; 1791de97f98SAndy Fleming char pnm[7]; 1801de97f98SAndy Fleming }; 1811de97f98SAndy Fleming 1821592ef85SReinhard Meyer /* 1831592ef85SReinhard Meyer * WARNING! 1841592ef85SReinhard Meyer * 1851592ef85SReinhard Meyer * This structure is used by atmel_mci.c only. 1861592ef85SReinhard Meyer * It works for the AVR32 architecture but NOT 1871592ef85SReinhard Meyer * for ARM/AT91 architectures. 1881592ef85SReinhard Meyer * Its use is highly depreciated. 1891592ef85SReinhard Meyer * After the atmel_mci.c driver for AVR32 has 1901592ef85SReinhard Meyer * been replaced this structure will be removed. 1911592ef85SReinhard Meyer */ 1921de97f98SAndy Fleming struct mmc_csd 1931de97f98SAndy Fleming { 1941de97f98SAndy Fleming u8 csd_structure:2, 1951de97f98SAndy Fleming spec_vers:4, 1961de97f98SAndy Fleming rsvd1:2; 1971de97f98SAndy Fleming u8 taac; 1981de97f98SAndy Fleming u8 nsac; 1991de97f98SAndy Fleming u8 tran_speed; 2001de97f98SAndy Fleming u16 ccc:12, 2011de97f98SAndy Fleming read_bl_len:4; 2021de97f98SAndy Fleming u64 read_bl_partial:1, 2031de97f98SAndy Fleming write_blk_misalign:1, 2041de97f98SAndy Fleming read_blk_misalign:1, 2051de97f98SAndy Fleming dsr_imp:1, 2061de97f98SAndy Fleming rsvd2:2, 2071de97f98SAndy Fleming c_size:12, 2081de97f98SAndy Fleming vdd_r_curr_min:3, 2091de97f98SAndy Fleming vdd_r_curr_max:3, 2101de97f98SAndy Fleming vdd_w_curr_min:3, 2111de97f98SAndy Fleming vdd_w_curr_max:3, 2121de97f98SAndy Fleming c_size_mult:3, 2131de97f98SAndy Fleming sector_size:5, 2141de97f98SAndy Fleming erase_grp_size:5, 2151de97f98SAndy Fleming wp_grp_size:5, 2161de97f98SAndy Fleming wp_grp_enable:1, 2171de97f98SAndy Fleming default_ecc:2, 2181de97f98SAndy Fleming r2w_factor:3, 2191de97f98SAndy Fleming write_bl_len:4, 2201de97f98SAndy Fleming write_bl_partial:1, 2211de97f98SAndy Fleming rsvd3:5; 2221de97f98SAndy Fleming u8 file_format_grp:1, 2231de97f98SAndy Fleming copy:1, 2241de97f98SAndy Fleming perm_write_protect:1, 2251de97f98SAndy Fleming tmp_write_protect:1, 2261de97f98SAndy Fleming file_format:2, 2271de97f98SAndy Fleming ecc:2; 2281de97f98SAndy Fleming u8 crc:7; 2291de97f98SAndy Fleming u8 one:1; 2301de97f98SAndy Fleming }; 2311de97f98SAndy Fleming 232272cc70bSAndy Fleming struct mmc_cmd { 233272cc70bSAndy Fleming ushort cmdidx; 234272cc70bSAndy Fleming uint resp_type; 235272cc70bSAndy Fleming uint cmdarg; 2360b453ffeSRabin Vincent uint response[4]; 237272cc70bSAndy Fleming uint flags; 238272cc70bSAndy Fleming }; 239272cc70bSAndy Fleming 240272cc70bSAndy Fleming struct mmc_data { 241272cc70bSAndy Fleming union { 242272cc70bSAndy Fleming char *dest; 243272cc70bSAndy Fleming const char *src; /* src buffers don't get written to */ 244272cc70bSAndy Fleming }; 245272cc70bSAndy Fleming uint flags; 246272cc70bSAndy Fleming uint blocks; 247272cc70bSAndy Fleming uint blocksize; 248272cc70bSAndy Fleming }; 249272cc70bSAndy Fleming 250272cc70bSAndy Fleming struct mmc { 251272cc70bSAndy Fleming struct list_head link; 252272cc70bSAndy Fleming char name[32]; 253272cc70bSAndy Fleming void *priv; 254272cc70bSAndy Fleming uint voltages; 255272cc70bSAndy Fleming uint version; 256272cc70bSAndy Fleming uint f_min; 257272cc70bSAndy Fleming uint f_max; 258272cc70bSAndy Fleming int high_capacity; 259272cc70bSAndy Fleming uint bus_width; 260272cc70bSAndy Fleming uint clock; 261272cc70bSAndy Fleming uint card_caps; 262272cc70bSAndy Fleming uint host_caps; 263272cc70bSAndy Fleming uint ocr; 264272cc70bSAndy Fleming uint scr[2]; 265272cc70bSAndy Fleming uint csd[4]; 2660b453ffeSRabin Vincent uint cid[4]; 267272cc70bSAndy Fleming ushort rca; 268272cc70bSAndy Fleming uint tran_speed; 269272cc70bSAndy Fleming uint read_bl_len; 270272cc70bSAndy Fleming uint write_bl_len; 271272cc70bSAndy Fleming u64 capacity; 272272cc70bSAndy Fleming block_dev_desc_t block_dev; 273272cc70bSAndy Fleming int (*send_cmd)(struct mmc *mmc, 274272cc70bSAndy Fleming struct mmc_cmd *cmd, struct mmc_data *data); 275272cc70bSAndy Fleming void (*set_ios)(struct mmc *mmc); 276272cc70bSAndy Fleming int (*init)(struct mmc *mmc); 277*57418d21SSandeep Paulraj #ifdef CONFIG_MMC_MBLOCK 278*57418d21SSandeep Paulraj uint b_max; 279*57418d21SSandeep Paulraj #endif 280272cc70bSAndy Fleming }; 281272cc70bSAndy Fleming 282272cc70bSAndy Fleming int mmc_register(struct mmc *mmc); 283272cc70bSAndy Fleming int mmc_initialize(bd_t *bis); 284272cc70bSAndy Fleming int mmc_init(struct mmc *mmc); 285272cc70bSAndy Fleming int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); 2864a6ee172SJerry Huang void mmc_set_clock(struct mmc *mmc, uint clock); 287272cc70bSAndy Fleming struct mmc *find_mmc_device(int dev_num); 28889716964SSteve Sakoman int mmc_set_dev(int dev_num); 289272cc70bSAndy Fleming void print_mmc_devices(char separator); 29011fdade2SStefano Babic int board_mmc_getcd(u8 *cd, struct mmc *mmc); 291272cc70bSAndy Fleming 2921592ef85SReinhard Meyer #ifdef CONFIG_GENERIC_MMC 2931592ef85SReinhard Meyer int atmel_mci_init(void *regs); 2941592ef85SReinhard Meyer #else 295272cc70bSAndy Fleming int mmc_legacy_init(int verbose); 296272cc70bSAndy Fleming #endif 2971592ef85SReinhard Meyer 29871f95118Swdenk #endif /* _MMC_H_ */ 299