1 /*----------------------------------------------------------------------------+ 2 | 3 | This source code has been made available to you by IBM on an AS-IS 4 | basis. Anyone receiving this source is licensed under IBM 5 | copyrights to use it in any way he or she deems fit, including 6 | copying it, modifying it, compiling it, and redistributing it either 7 | with or without modifications. No license under IBM patents or 8 | patent applications is to be implied by the copyright license. 9 | 10 | Any user of this software should understand that IBM cannot provide 11 | technical support for this software and will not be responsible for 12 | any consequences resulting from the use of this software. 13 | 14 | Any person who transfers this source code or any derivative work 15 | must include the IBM copyright notice, this paragraph, and the 16 | preceding two paragraphs in the transferred software. 17 | 18 | COPYRIGHT I B M CORPORATION 1999 19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 20 +----------------------------------------------------------------------------*/ 21 /*----------------------------------------------------------------------------+ 22 | 23 | File Name: miiphy.h 24 | 25 | Function: Include file defining PHY registers. 26 | 27 | Author: Mark Wisner 28 | 29 | Change Activity- 30 | 31 | Date Description of Change BY 32 | --------- --------------------- --- 33 | 04-May-99 Created MKW 34 | 07-Jul-99 Added full duplex support MKW 35 | 08-Sep-01 Tweaks gvb 36 | 37 +----------------------------------------------------------------------------*/ 38 #ifndef _miiphy_h_ 39 #define _miiphy_h_ 40 41 #include <net.h> 42 43 int miiphy_read(char *devname, unsigned char addr, unsigned char reg, 44 unsigned short *value); 45 int miiphy_write(char *devname, unsigned char addr, unsigned char reg, 46 unsigned short value); 47 int miiphy_info(char *devname, unsigned char addr, unsigned int *oui, 48 unsigned char *model, unsigned char *rev); 49 int miiphy_reset(char *devname, unsigned char addr); 50 int miiphy_speed(char *devname, unsigned char addr); 51 int miiphy_duplex(char *devname, unsigned char addr); 52 #ifdef CFG_FAULT_ECHO_LINK_DOWN 53 int miiphy_link(char *devname, unsigned char addr); 54 #endif 55 56 void miiphy_register(char *devname, 57 int (* read)(char *devname, unsigned char addr, 58 unsigned char reg, unsigned short *value), 59 int (* write)(char *devname, unsigned char addr, 60 unsigned char reg, unsigned short value)); 61 62 int miiphy_set_current_dev(char *devname); 63 char *miiphy_get_current_dev(void); 64 65 void miiphy_listdev(void); 66 67 #define BB_MII_DEVNAME "bbmii" 68 69 int bb_miiphy_read (char *devname, unsigned char addr, 70 unsigned char reg, unsigned short *value); 71 int bb_miiphy_write (char *devname, unsigned char addr, 72 unsigned char reg, unsigned short value); 73 74 /* phy seed setup */ 75 #define AUTO 99 76 #define _1000BASET 1000 77 #define _100BASET 100 78 #define _10BASET 10 79 #define HALF 22 80 #define FULL 44 81 82 /* phy register offsets */ 83 #define PHY_BMCR 0x00 84 #define PHY_BMSR 0x01 85 #define PHY_PHYIDR1 0x02 86 #define PHY_PHYIDR2 0x03 87 #define PHY_ANAR 0x04 88 #define PHY_ANLPAR 0x05 89 #define PHY_ANER 0x06 90 #define PHY_ANNPTR 0x07 91 #define PHY_ANLPNP 0x08 92 #define PHY_1000BTCR 0x09 93 #define PHY_1000BTSR 0x0A 94 #define PHY_PHYSTS 0x10 95 #define PHY_MIPSCR 0x11 96 #define PHY_MIPGSR 0x12 97 #define PHY_DCR 0x13 98 #define PHY_FCSCR 0x14 99 #define PHY_RECR 0x15 100 #define PHY_PCSR 0x16 101 #define PHY_LBR 0x17 102 #define PHY_10BTSCR 0x18 103 #define PHY_PHYCTRL 0x19 104 105 /* PHY BMCR */ 106 #define PHY_BMCR_RESET 0x8000 107 #define PHY_BMCR_LOOP 0x4000 108 #define PHY_BMCR_100MB 0x2000 109 #define PHY_BMCR_AUTON 0x1000 110 #define PHY_BMCR_POWD 0x0800 111 #define PHY_BMCR_ISO 0x0400 112 #define PHY_BMCR_RST_NEG 0x0200 113 #define PHY_BMCR_DPLX 0x0100 114 #define PHY_BMCR_COL_TST 0x0080 115 116 #define PHY_BMCR_SPEED_MASK 0x2040 117 #define PHY_BMCR_1000_MBPS 0x0040 118 #define PHY_BMCR_100_MBPS 0x2000 119 #define PHY_BMCR_10_MBPS 0x0000 120 121 /* phy BMSR */ 122 #define PHY_BMSR_100T4 0x8000 123 #define PHY_BMSR_100TXF 0x4000 124 #define PHY_BMSR_100TXH 0x2000 125 #define PHY_BMSR_10TF 0x1000 126 #define PHY_BMSR_10TH 0x0800 127 #define PHY_BMSR_PRE_SUP 0x0040 128 #define PHY_BMSR_AUTN_COMP 0x0020 129 #define PHY_BMSR_RF 0x0010 130 #define PHY_BMSR_AUTN_ABLE 0x0008 131 #define PHY_BMSR_LS 0x0004 132 #define PHY_BMSR_JD 0x0002 133 #define PHY_BMSR_EXT 0x0001 134 135 /*phy ANLPAR */ 136 #define PHY_ANLPAR_NP 0x8000 137 #define PHY_ANLPAR_ACK 0x4000 138 #define PHY_ANLPAR_RF 0x2000 139 #define PHY_ANLPAR_T4 0x0200 140 #define PHY_ANLPAR_TXFD 0x0100 141 #define PHY_ANLPAR_TX 0x0080 142 #define PHY_ANLPAR_10FD 0x0040 143 #define PHY_ANLPAR_10 0x0020 144 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ 145 146 #define PHY_ANLPAR_PSB_MASK 0x001f 147 #define PHY_ANLPAR_PSB_802_3 0x0001 148 #define PHY_ANLPAR_PSB_802_9 0x0002 149 150 /* PHY_1000BTSR */ 151 #define PHY_1000BTSR_MSCF 0x8000 152 #define PHY_1000BTSR_MSCR 0x4000 153 #define PHY_1000BTSR_LRS 0x2000 154 #define PHY_1000BTSR_RRS 0x1000 155 #define PHY_1000BTSR_1000FD 0x0800 156 #define PHY_1000BTSR_1000HD 0x0400 157 158 #endif 159