xref: /rk3399_rockchip-uboot/include/miiphy.h (revision 214ec6bbd1688bcec2ca0eac7343b370ee3d8a31)
1*214ec6bbSwdenk /*----------------------------------------------------------------------------+
2*214ec6bbSwdenk |
3*214ec6bbSwdenk |       This source code has been made available to you by IBM on an AS-IS
4*214ec6bbSwdenk |       basis.  Anyone receiving this source is licensed under IBM
5*214ec6bbSwdenk |       copyrights to use it in any way he or she deems fit, including
6*214ec6bbSwdenk |       copying it, modifying it, compiling it, and redistributing it either
7*214ec6bbSwdenk |       with or without modifications.  No license under IBM patents or
8*214ec6bbSwdenk |       patent applications is to be implied by the copyright license.
9*214ec6bbSwdenk |
10*214ec6bbSwdenk |       Any user of this software should understand that IBM cannot provide
11*214ec6bbSwdenk |       technical support for this software and will not be responsible for
12*214ec6bbSwdenk |       any consequences resulting from the use of this software.
13*214ec6bbSwdenk |
14*214ec6bbSwdenk |       Any person who transfers this source code or any derivative work
15*214ec6bbSwdenk |       must include the IBM copyright notice, this paragraph, and the
16*214ec6bbSwdenk |       preceding two paragraphs in the transferred software.
17*214ec6bbSwdenk |
18*214ec6bbSwdenk |       COPYRIGHT   I B M   CORPORATION 1999
19*214ec6bbSwdenk |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
20*214ec6bbSwdenk +----------------------------------------------------------------------------*/
21*214ec6bbSwdenk /*----------------------------------------------------------------------------+
22*214ec6bbSwdenk |
23*214ec6bbSwdenk |  File Name:   miiphy.h
24*214ec6bbSwdenk |
25*214ec6bbSwdenk |  Function:    Include file defining PHY registers.
26*214ec6bbSwdenk |
27*214ec6bbSwdenk |  Author:      Mark Wisner
28*214ec6bbSwdenk |
29*214ec6bbSwdenk |  Change Activity-
30*214ec6bbSwdenk |
31*214ec6bbSwdenk |  Date        Description of Change                                       BY
32*214ec6bbSwdenk |  ---------   ---------------------                                       ---
33*214ec6bbSwdenk |  04-May-99   Created                                                     MKW
34*214ec6bbSwdenk |  07-Jul-99   Added full duplex support                                   MKW
35*214ec6bbSwdenk |  08-Sep-01   Tweaks                                                      gvb
36*214ec6bbSwdenk |
37*214ec6bbSwdenk +----------------------------------------------------------------------------*/
38*214ec6bbSwdenk #ifndef _miiphy_h_
39*214ec6bbSwdenk #define _miiphy_h_
40*214ec6bbSwdenk 
41*214ec6bbSwdenk 
42*214ec6bbSwdenk int  miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
43*214ec6bbSwdenk int  miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
44*214ec6bbSwdenk int  miiphy_info(unsigned char addr, unsigned int  *oui, unsigned char *model,
45*214ec6bbSwdenk                  unsigned char *rev);
46*214ec6bbSwdenk int  miiphy_reset(unsigned char addr);
47*214ec6bbSwdenk int  miiphy_speed(unsigned char addr);
48*214ec6bbSwdenk int  miiphy_duplex(unsigned char addr);
49*214ec6bbSwdenk 
50*214ec6bbSwdenk 
51*214ec6bbSwdenk /* phy seed setup */
52*214ec6bbSwdenk #define AUTO     99
53*214ec6bbSwdenk #define _100BASET 100
54*214ec6bbSwdenk #define _10BASET  10
55*214ec6bbSwdenk #define HALF   22
56*214ec6bbSwdenk #define FULL   44
57*214ec6bbSwdenk 
58*214ec6bbSwdenk /* phy register offsets */
59*214ec6bbSwdenk #define PHY_BMCR 		0x00
60*214ec6bbSwdenk #define PHY_BMSR		0x01
61*214ec6bbSwdenk #define PHY_PHYIDR1 	0x02
62*214ec6bbSwdenk #define PHY_PHYIDR2	0x03
63*214ec6bbSwdenk #define PHY_ANAR		0x04
64*214ec6bbSwdenk #define PHY_ANLPAR	0x05
65*214ec6bbSwdenk #define PHY_ANER		0x06
66*214ec6bbSwdenk #define PHY_ANNPTR	0x07
67*214ec6bbSwdenk #define PHY_PHYSTS	0x10
68*214ec6bbSwdenk #define PHY_MIPSCR	0x11
69*214ec6bbSwdenk #define PHY_MIPGSR	0x12
70*214ec6bbSwdenk #define PHY_DCR		0x13
71*214ec6bbSwdenk #define PHY_FCSCR		0x14
72*214ec6bbSwdenk #define PHY_RECR		0x15
73*214ec6bbSwdenk #define PHY_PCSR		0x16
74*214ec6bbSwdenk #define PHY_LBR		0x17
75*214ec6bbSwdenk #define PHY_10BTSCR	0x18
76*214ec6bbSwdenk #define PHY_PHYCTRL	0x19
77*214ec6bbSwdenk 
78*214ec6bbSwdenk /* PHY BMCR */
79*214ec6bbSwdenk #define PHY_BMCR_RESET  	0x8000
80*214ec6bbSwdenk #define PHY_BMCR_LOOP  	 	0x4000
81*214ec6bbSwdenk #define PHY_BMCR_100MB		0x2000
82*214ec6bbSwdenk #define PHY_BMCR_AUTON		0x1000
83*214ec6bbSwdenk #define PHY_BMCR_POWD		0x0800
84*214ec6bbSwdenk #define PHY_BMCR_ISO		0x0400
85*214ec6bbSwdenk #define PHY_BMCR_RST_NEG	0x0200
86*214ec6bbSwdenk #define PHY_BMCR_DPLX		0x0100
87*214ec6bbSwdenk #define PHY_BMCR_COL_TST	0x0080
88*214ec6bbSwdenk 
89*214ec6bbSwdenk /* phy BMSR */
90*214ec6bbSwdenk #define PHY_BMSR_100T4		0x8000
91*214ec6bbSwdenk #define PHY_BMSR_100TXF		0x4000
92*214ec6bbSwdenk #define PHY_BMSR_100TXH		0x2000
93*214ec6bbSwdenk #define PHY_BMSR_10TF		0x1000
94*214ec6bbSwdenk #define PHY_BMSR_10TH		0x0800
95*214ec6bbSwdenk #define PHY_BMSR_PRE_SUP	0x0040
96*214ec6bbSwdenk #define PHY_BMSR_AUTN_COMP	0x0020
97*214ec6bbSwdenk #define PHY_BMSR_RF		0x0010
98*214ec6bbSwdenk #define PHY_BMSR_AUTN_ABLE	0x0008
99*214ec6bbSwdenk #define PHY_BMSR_LS		0x0004
100*214ec6bbSwdenk #define PHY_BMSR_JD		0x0002
101*214ec6bbSwdenk #define PHY_BMSR_EXT		0x0001
102*214ec6bbSwdenk 
103*214ec6bbSwdenk /*phy ANLPAR */
104*214ec6bbSwdenk #define PHY_ANLPAR_NP		0x8000
105*214ec6bbSwdenk #define PHY_ANLPAR_ACK		0x4000
106*214ec6bbSwdenk #define PHY_ANLPAR_RF         0x2000
107*214ec6bbSwdenk #define PHY_ANLPAR_T4         0x0200
108*214ec6bbSwdenk #define PHY_ANLPAR_TXFD       0x0100
109*214ec6bbSwdenk #define PHY_ANLPAR_TX         0x0080
110*214ec6bbSwdenk #define PHY_ANLPAR_10FD		0x0040
111*214ec6bbSwdenk #define PHY_ANLPAR_10         0x0020
112*214ec6bbSwdenk #define PHY_ANLPAR_100        0x0380        /* we can run at 100 */
113*214ec6bbSwdenk #endif
114