1 /* 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 3 * Steven J. Hill <sjhill@realitydiluted.com> 4 * Thomas Gleixner <tglx@linutronix.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * Info: 9 * Contains standard defines and IDs for NAND flash devices 10 * 11 * Changelog: 12 * See git changelog. 13 */ 14 #ifndef __LINUX_MTD_RAWNAND_H 15 #define __LINUX_MTD_RAWNAND_H 16 17 #include <config.h> 18 19 #include <linux/compat.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/flashchip.h> 22 #include <linux/mtd/bbm.h> 23 24 struct mtd_info; 25 struct nand_chip; 26 struct nand_flash_dev; 27 struct device_node; 28 29 /* Get the flash and manufacturer id and lookup if the type is supported. */ 30 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 31 struct nand_chip *chip, 32 int *maf_id, int *dev_id, 33 struct nand_flash_dev *type); 34 35 /* Scan and identify a NAND device */ 36 extern int nand_scan(struct mtd_info *mtd, int max_chips); 37 /* 38 * Separate phases of nand_scan(), allowing board driver to intervene 39 * and override command or ECC setup according to flash type. 40 */ 41 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 42 struct nand_flash_dev *table); 43 extern int nand_scan_tail(struct mtd_info *mtd); 44 45 /* Free resources held by the NAND device */ 46 extern void nand_release(struct mtd_info *mtd); 47 48 /* Internal helper for board drivers which need to override command function */ 49 extern void nand_wait_ready(struct mtd_info *mtd); 50 51 /* 52 * This constant declares the max. oobsize / page, which 53 * is supported now. If you add a chip with bigger oobsize/page 54 * adjust this accordingly. 55 */ 56 #define NAND_MAX_OOBSIZE 1664 57 #define NAND_MAX_PAGESIZE 16384 58 59 /* 60 * Constants for hardware specific CLE/ALE/NCE function 61 * 62 * These are bits which can be or'ed to set/clear multiple 63 * bits in one go. 64 */ 65 /* Select the chip by setting nCE to low */ 66 #define NAND_NCE 0x01 67 /* Select the command latch by setting CLE to high */ 68 #define NAND_CLE 0x02 69 /* Select the address latch by setting ALE to high */ 70 #define NAND_ALE 0x04 71 72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 74 #define NAND_CTRL_CHANGE 0x80 75 76 /* 77 * Standard NAND flash commands 78 */ 79 #define NAND_CMD_READ0 0 80 #define NAND_CMD_READ1 1 81 #define NAND_CMD_RNDOUT 5 82 #define NAND_CMD_PAGEPROG 0x10 83 #define NAND_CMD_READOOB 0x50 84 #define NAND_CMD_ERASE1 0x60 85 #define NAND_CMD_STATUS 0x70 86 #define NAND_CMD_SEQIN 0x80 87 #define NAND_CMD_RNDIN 0x85 88 #define NAND_CMD_READID 0x90 89 #define NAND_CMD_ERASE2 0xd0 90 #define NAND_CMD_PARAM 0xec 91 #define NAND_CMD_GET_FEATURES 0xee 92 #define NAND_CMD_SET_FEATURES 0xef 93 #define NAND_CMD_RESET 0xff 94 95 #define NAND_CMD_LOCK 0x2a 96 #define NAND_CMD_UNLOCK1 0x23 97 #define NAND_CMD_UNLOCK2 0x24 98 99 /* Extended commands for large page devices */ 100 #define NAND_CMD_READSTART 0x30 101 #define NAND_CMD_RNDOUTSTART 0xE0 102 #define NAND_CMD_CACHEDPROG 0x15 103 104 /* Extended commands for AG-AND device */ 105 /* 106 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 107 * there is no way to distinguish that from NAND_CMD_READ0 108 * until the remaining sequence of commands has been completed 109 * so add a high order bit and mask it off in the command. 110 */ 111 #define NAND_CMD_DEPLETE1 0x100 112 #define NAND_CMD_DEPLETE2 0x38 113 #define NAND_CMD_STATUS_MULTI 0x71 114 #define NAND_CMD_STATUS_ERROR 0x72 115 /* multi-bank error status (banks 0-3) */ 116 #define NAND_CMD_STATUS_ERROR0 0x73 117 #define NAND_CMD_STATUS_ERROR1 0x74 118 #define NAND_CMD_STATUS_ERROR2 0x75 119 #define NAND_CMD_STATUS_ERROR3 0x76 120 #define NAND_CMD_STATUS_RESET 0x7f 121 #define NAND_CMD_STATUS_CLEAR 0xff 122 123 #define NAND_CMD_NONE -1 124 125 /* Status bits */ 126 #define NAND_STATUS_FAIL 0x01 127 #define NAND_STATUS_FAIL_N1 0x02 128 #define NAND_STATUS_TRUE_READY 0x20 129 #define NAND_STATUS_READY 0x40 130 #define NAND_STATUS_WP 0x80 131 132 #define NAND_DATA_IFACE_CHECK_ONLY -1 133 134 /* 135 * Constants for ECC_MODES 136 */ 137 typedef enum { 138 NAND_ECC_NONE, 139 NAND_ECC_SOFT, 140 NAND_ECC_HW, 141 NAND_ECC_HW_SYNDROME, 142 NAND_ECC_HW_OOB_FIRST, 143 NAND_ECC_SOFT_BCH, 144 } nand_ecc_modes_t; 145 146 /* 147 * Constants for Hardware ECC 148 */ 149 /* Reset Hardware ECC for read */ 150 #define NAND_ECC_READ 0 151 /* Reset Hardware ECC for write */ 152 #define NAND_ECC_WRITE 1 153 /* Enable Hardware ECC before syndrome is read back from flash */ 154 #define NAND_ECC_READSYN 2 155 156 /* 157 * Enable generic NAND 'page erased' check. This check is only done when 158 * ecc.correct() returns -EBADMSG. 159 * Set this flag if your implementation does not fix bitflips in erased 160 * pages and you want to rely on the default implementation. 161 */ 162 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 163 #define NAND_ECC_MAXIMIZE BIT(1) 164 /* 165 * If your controller already sends the required NAND commands when 166 * reading or writing a page, then the framework is not supposed to 167 * send READ0 and SEQIN/PAGEPROG respectively. 168 */ 169 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 170 171 /* Bit mask for flags passed to do_nand_read_ecc */ 172 #define NAND_GET_DEVICE 0x80 173 174 175 /* 176 * Option constants for bizarre disfunctionality and real 177 * features. 178 */ 179 /* Buswidth is 16 bit */ 180 #define NAND_BUSWIDTH_16 0x00000002 181 /* Device supports partial programming without padding */ 182 #define NAND_NO_PADDING 0x00000004 183 /* Chip has cache program function */ 184 #define NAND_CACHEPRG 0x00000008 185 /* Chip has copy back function */ 186 #define NAND_COPYBACK 0x00000010 187 /* 188 * Chip requires ready check on read (for auto-incremented sequential read). 189 * True only for small page devices; large page devices do not support 190 * autoincrement. 191 */ 192 #define NAND_NEED_READRDY 0x00000100 193 194 /* Chip does not allow subpage writes */ 195 #define NAND_NO_SUBPAGE_WRITE 0x00000200 196 197 /* Device is one of 'new' xD cards that expose fake nand command set */ 198 #define NAND_BROKEN_XD 0x00000400 199 200 /* Device behaves just like nand, but is readonly */ 201 #define NAND_ROM 0x00000800 202 203 /* Device supports subpage reads */ 204 #define NAND_SUBPAGE_READ 0x00001000 205 206 /* 207 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 208 * patterns. 209 */ 210 #define NAND_NEED_SCRAMBLING 0x00002000 211 212 /* Device needs 3rd row address cycle */ 213 #define NAND_ROW_ADDR_3 0x00004000 214 215 /* Options valid for Samsung large page devices */ 216 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 217 218 /* Macros to identify the above */ 219 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 220 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 221 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 222 223 /* Non chip related options */ 224 /* This option skips the bbt scan during initialization. */ 225 #define NAND_SKIP_BBTSCAN 0x00010000 226 /* 227 * This option is defined if the board driver allocates its own buffers 228 * (e.g. because it needs them DMA-coherent). 229 */ 230 #define NAND_OWN_BUFFERS 0x00020000 231 /* Chip may not exist, so silence any errors in scan */ 232 #define NAND_SCAN_SILENT_NODEV 0x00040000 233 /* 234 * Autodetect nand buswidth with readid/onfi. 235 * This suppose the driver will configure the hardware in 8 bits mode 236 * when calling nand_scan_ident, and update its configuration 237 * before calling nand_scan_tail. 238 */ 239 #define NAND_BUSWIDTH_AUTO 0x00080000 240 /* 241 * This option could be defined by controller drivers to protect against 242 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 243 */ 244 #define NAND_USE_BOUNCE_BUFFER 0x00100000 245 246 /* Options set by nand scan */ 247 /* bbt has already been read */ 248 #define NAND_BBT_SCANNED 0x40000000 249 /* Nand scan has allocated controller struct */ 250 #define NAND_CONTROLLER_ALLOC 0x80000000 251 252 /* Cell info constants */ 253 #define NAND_CI_CHIPNR_MSK 0x03 254 #define NAND_CI_CELLTYPE_MSK 0x0C 255 #define NAND_CI_CELLTYPE_SHIFT 2 256 257 /* ONFI features */ 258 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 259 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 260 261 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 262 #define ONFI_TIMING_MODE_0 (1 << 0) 263 #define ONFI_TIMING_MODE_1 (1 << 1) 264 #define ONFI_TIMING_MODE_2 (1 << 2) 265 #define ONFI_TIMING_MODE_3 (1 << 3) 266 #define ONFI_TIMING_MODE_4 (1 << 4) 267 #define ONFI_TIMING_MODE_5 (1 << 5) 268 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 269 270 /* ONFI feature address */ 271 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 272 273 /* Vendor-specific feature address (Micron) */ 274 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 275 276 /* ONFI subfeature parameters length */ 277 #define ONFI_SUBFEATURE_PARAM_LEN 4 278 279 /* ONFI optional commands SET/GET FEATURES supported? */ 280 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 281 282 struct nand_onfi_params { 283 /* rev info and features block */ 284 /* 'O' 'N' 'F' 'I' */ 285 u8 sig[4]; 286 __le16 revision; 287 __le16 features; 288 __le16 opt_cmd; 289 u8 reserved0[2]; 290 __le16 ext_param_page_length; /* since ONFI 2.1 */ 291 u8 num_of_param_pages; /* since ONFI 2.1 */ 292 u8 reserved1[17]; 293 294 /* manufacturer information block */ 295 char manufacturer[12]; 296 char model[20]; 297 u8 jedec_id; 298 __le16 date_code; 299 u8 reserved2[13]; 300 301 /* memory organization block */ 302 __le32 byte_per_page; 303 __le16 spare_bytes_per_page; 304 __le32 data_bytes_per_ppage; 305 __le16 spare_bytes_per_ppage; 306 __le32 pages_per_block; 307 __le32 blocks_per_lun; 308 u8 lun_count; 309 u8 addr_cycles; 310 u8 bits_per_cell; 311 __le16 bb_per_lun; 312 __le16 block_endurance; 313 u8 guaranteed_good_blocks; 314 __le16 guaranteed_block_endurance; 315 u8 programs_per_page; 316 u8 ppage_attr; 317 u8 ecc_bits; 318 u8 interleaved_bits; 319 u8 interleaved_ops; 320 u8 reserved3[13]; 321 322 /* electrical parameter block */ 323 u8 io_pin_capacitance_max; 324 __le16 async_timing_mode; 325 __le16 program_cache_timing_mode; 326 __le16 t_prog; 327 __le16 t_bers; 328 __le16 t_r; 329 __le16 t_ccs; 330 __le16 src_sync_timing_mode; 331 u8 src_ssync_features; 332 __le16 clk_pin_capacitance_typ; 333 __le16 io_pin_capacitance_typ; 334 __le16 input_pin_capacitance_typ; 335 u8 input_pin_capacitance_max; 336 u8 driver_strength_support; 337 __le16 t_int_r; 338 __le16 t_adl; 339 u8 reserved4[8]; 340 341 /* vendor */ 342 __le16 vendor_revision; 343 u8 vendor[88]; 344 345 __le16 crc; 346 } __packed; 347 348 #define ONFI_CRC_BASE 0x4F4E 349 350 /* Extended ECC information Block Definition (since ONFI 2.1) */ 351 struct onfi_ext_ecc_info { 352 u8 ecc_bits; 353 u8 codeword_size; 354 __le16 bb_per_lun; 355 __le16 block_endurance; 356 u8 reserved[2]; 357 } __packed; 358 359 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 360 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 361 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 362 struct onfi_ext_section { 363 u8 type; 364 u8 length; 365 } __packed; 366 367 #define ONFI_EXT_SECTION_MAX 8 368 369 /* Extended Parameter Page Definition (since ONFI 2.1) */ 370 struct onfi_ext_param_page { 371 __le16 crc; 372 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 373 u8 reserved0[10]; 374 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 375 376 /* 377 * The actual size of the Extended Parameter Page is in 378 * @ext_param_page_length of nand_onfi_params{}. 379 * The following are the variable length sections. 380 * So we do not add any fields below. Please see the ONFI spec. 381 */ 382 } __packed; 383 384 struct nand_onfi_vendor_micron { 385 u8 two_plane_read; 386 u8 read_cache; 387 u8 read_unique_id; 388 u8 dq_imped; 389 u8 dq_imped_num_settings; 390 u8 dq_imped_feat_addr; 391 u8 rb_pulldown_strength; 392 u8 rb_pulldown_strength_feat_addr; 393 u8 rb_pulldown_strength_num_settings; 394 u8 otp_mode; 395 u8 otp_page_start; 396 u8 otp_data_prot_addr; 397 u8 otp_num_pages; 398 u8 otp_feat_addr; 399 u8 read_retry_options; 400 u8 reserved[72]; 401 u8 param_revision; 402 } __packed; 403 404 struct jedec_ecc_info { 405 u8 ecc_bits; 406 u8 codeword_size; 407 __le16 bb_per_lun; 408 __le16 block_endurance; 409 u8 reserved[2]; 410 } __packed; 411 412 /* JEDEC features */ 413 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 414 415 struct nand_jedec_params { 416 /* rev info and features block */ 417 /* 'J' 'E' 'S' 'D' */ 418 u8 sig[4]; 419 __le16 revision; 420 __le16 features; 421 u8 opt_cmd[3]; 422 __le16 sec_cmd; 423 u8 num_of_param_pages; 424 u8 reserved0[18]; 425 426 /* manufacturer information block */ 427 char manufacturer[12]; 428 char model[20]; 429 u8 jedec_id[6]; 430 u8 reserved1[10]; 431 432 /* memory organization block */ 433 __le32 byte_per_page; 434 __le16 spare_bytes_per_page; 435 u8 reserved2[6]; 436 __le32 pages_per_block; 437 __le32 blocks_per_lun; 438 u8 lun_count; 439 u8 addr_cycles; 440 u8 bits_per_cell; 441 u8 programs_per_page; 442 u8 multi_plane_addr; 443 u8 multi_plane_op_attr; 444 u8 reserved3[38]; 445 446 /* electrical parameter block */ 447 __le16 async_sdr_speed_grade; 448 __le16 toggle_ddr_speed_grade; 449 __le16 sync_ddr_speed_grade; 450 u8 async_sdr_features; 451 u8 toggle_ddr_features; 452 u8 sync_ddr_features; 453 __le16 t_prog; 454 __le16 t_bers; 455 __le16 t_r; 456 __le16 t_r_multi_plane; 457 __le16 t_ccs; 458 __le16 io_pin_capacitance_typ; 459 __le16 input_pin_capacitance_typ; 460 __le16 clk_pin_capacitance_typ; 461 u8 driver_strength_support; 462 __le16 t_adl; 463 u8 reserved4[36]; 464 465 /* ECC and endurance block */ 466 u8 guaranteed_good_blocks; 467 __le16 guaranteed_block_endurance; 468 struct jedec_ecc_info ecc_info[4]; 469 u8 reserved5[29]; 470 471 /* reserved */ 472 u8 reserved6[148]; 473 474 /* vendor */ 475 __le16 vendor_rev_num; 476 u8 reserved7[88]; 477 478 /* CRC for Parameter Page */ 479 __le16 crc; 480 } __packed; 481 482 /** 483 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 484 * @lock: protection lock 485 * @active: the mtd device which holds the controller currently 486 * @wq: wait queue to sleep on if a NAND operation is in 487 * progress used instead of the per chip wait queue 488 * when a hw controller is available. 489 */ 490 struct nand_hw_control { 491 spinlock_t lock; 492 struct nand_chip *active; 493 }; 494 495 /** 496 * struct nand_ecc_step_info - ECC step information of ECC engine 497 * @stepsize: data bytes per ECC step 498 * @strengths: array of supported strengths 499 * @nstrengths: number of supported strengths 500 */ 501 struct nand_ecc_step_info { 502 int stepsize; 503 const int *strengths; 504 int nstrengths; 505 }; 506 507 /** 508 * struct nand_ecc_caps - capability of ECC engine 509 * @stepinfos: array of ECC step information 510 * @nstepinfos: number of ECC step information 511 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 512 */ 513 struct nand_ecc_caps { 514 const struct nand_ecc_step_info *stepinfos; 515 int nstepinfos; 516 int (*calc_ecc_bytes)(int step_size, int strength); 517 }; 518 519 /** 520 * struct nand_ecc_ctrl - Control structure for ECC 521 * @mode: ECC mode 522 * @steps: number of ECC steps per page 523 * @size: data bytes per ECC step 524 * @bytes: ECC bytes per step 525 * @strength: max number of correctible bits per ECC step 526 * @total: total number of ECC bytes per page 527 * @prepad: padding information for syndrome based ECC generators 528 * @postpad: padding information for syndrome based ECC generators 529 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 530 * @layout: ECC layout control struct pointer 531 * @priv: pointer to private ECC control data 532 * @hwctl: function to control hardware ECC generator. Must only 533 * be provided if an hardware ECC is available 534 * @calculate: function for ECC calculation or readback from ECC hardware 535 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 536 * Should return a positive number representing the number of 537 * corrected bitflips, -EBADMSG if the number of bitflips exceed 538 * ECC strength, or any other error code if the error is not 539 * directly related to correction. 540 * If -EBADMSG is returned the input buffers should be left 541 * untouched. 542 * @read_page_raw: function to read a raw page without ECC. This function 543 * should hide the specific layout used by the ECC 544 * controller and always return contiguous in-band and 545 * out-of-band data even if they're not stored 546 * contiguously on the NAND chip (e.g. 547 * NAND_ECC_HW_SYNDROME interleaves in-band and 548 * out-of-band data). 549 * @write_page_raw: function to write a raw page without ECC. This function 550 * should hide the specific layout used by the ECC 551 * controller and consider the passed data as contiguous 552 * in-band and out-of-band data. ECC controller is 553 * responsible for doing the appropriate transformations 554 * to adapt to its specific layout (e.g. 555 * NAND_ECC_HW_SYNDROME interleaves in-band and 556 * out-of-band data). 557 * @read_page: function to read a page according to the ECC generator 558 * requirements; returns maximum number of bitflips corrected in 559 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 560 * @read_subpage: function to read parts of the page covered by ECC; 561 * returns same as read_page() 562 * @write_subpage: function to write parts of the page covered by ECC. 563 * @write_page: function to write a page according to the ECC generator 564 * requirements. 565 * @write_oob_raw: function to write chip OOB data without ECC 566 * @read_oob_raw: function to read chip OOB data without ECC 567 * @read_oob: function to read chip OOB data 568 * @write_oob: function to write chip OOB data 569 */ 570 struct nand_ecc_ctrl { 571 nand_ecc_modes_t mode; 572 int steps; 573 int size; 574 int bytes; 575 int total; 576 int strength; 577 int prepad; 578 int postpad; 579 unsigned int options; 580 struct nand_ecclayout *layout; 581 void *priv; 582 void (*hwctl)(struct mtd_info *mtd, int mode); 583 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 584 uint8_t *ecc_code); 585 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 586 uint8_t *calc_ecc); 587 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 588 uint8_t *buf, int oob_required, int page); 589 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 590 const uint8_t *buf, int oob_required, int page); 591 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 592 uint8_t *buf, int oob_required, int page); 593 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 594 uint32_t offs, uint32_t len, uint8_t *buf, int page); 595 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 596 uint32_t offset, uint32_t data_len, 597 const uint8_t *data_buf, int oob_required, int page); 598 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 599 const uint8_t *buf, int oob_required, int page); 600 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 601 int page); 602 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 603 int page); 604 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 605 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 606 int page); 607 }; 608 609 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 610 { 611 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 612 } 613 614 /** 615 * struct nand_buffers - buffer structure for read/write 616 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 617 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 618 * @databuf: buffer pointer for data, size is (page size + oobsize). 619 * 620 * Do not change the order of buffers. databuf and oobrbuf must be in 621 * consecutive order. 622 */ 623 struct nand_buffers { 624 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 625 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 626 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 627 ARCH_DMA_MINALIGN)]; 628 }; 629 630 /** 631 * struct nand_sdr_timings - SDR NAND chip timings 632 * 633 * This struct defines the timing requirements of a SDR NAND chip. 634 * These information can be found in every NAND datasheets and the timings 635 * meaning are described in the ONFI specifications: 636 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 637 * Parameters) 638 * 639 * All these timings are expressed in picoseconds. 640 * 641 * @tBERS_max: Block erase time 642 * @tCCS_min: Change column setup time 643 * @tPROG_max: Page program time 644 * @tR_max: Page read time 645 * @tALH_min: ALE hold time 646 * @tADL_min: ALE to data loading time 647 * @tALS_min: ALE setup time 648 * @tAR_min: ALE to RE# delay 649 * @tCEA_max: CE# access time 650 * @tCEH_min: CE# high hold time 651 * @tCH_min: CE# hold time 652 * @tCHZ_max: CE# high to output hi-Z 653 * @tCLH_min: CLE hold time 654 * @tCLR_min: CLE to RE# delay 655 * @tCLS_min: CLE setup time 656 * @tCOH_min: CE# high to output hold 657 * @tCS_min: CE# setup time 658 * @tDH_min: Data hold time 659 * @tDS_min: Data setup time 660 * @tFEAT_max: Busy time for Set Features and Get Features 661 * @tIR_min: Output hi-Z to RE# low 662 * @tITC_max: Interface and Timing Mode Change time 663 * @tRC_min: RE# cycle time 664 * @tREA_max: RE# access time 665 * @tREH_min: RE# high hold time 666 * @tRHOH_min: RE# high to output hold 667 * @tRHW_min: RE# high to WE# low 668 * @tRHZ_max: RE# high to output hi-Z 669 * @tRLOH_min: RE# low to output hold 670 * @tRP_min: RE# pulse width 671 * @tRR_min: Ready to RE# low (data only) 672 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 673 * rising edge of R/B#. 674 * @tWB_max: WE# high to SR[6] low 675 * @tWC_min: WE# cycle time 676 * @tWH_min: WE# high hold time 677 * @tWHR_min: WE# high to RE# low 678 * @tWP_min: WE# pulse width 679 * @tWW_min: WP# transition to WE# low 680 */ 681 struct nand_sdr_timings { 682 u64 tBERS_max; 683 u32 tCCS_min; 684 u64 tPROG_max; 685 u64 tR_max; 686 u32 tALH_min; 687 u32 tADL_min; 688 u32 tALS_min; 689 u32 tAR_min; 690 u32 tCEA_max; 691 u32 tCEH_min; 692 u32 tCH_min; 693 u32 tCHZ_max; 694 u32 tCLH_min; 695 u32 tCLR_min; 696 u32 tCLS_min; 697 u32 tCOH_min; 698 u32 tCS_min; 699 u32 tDH_min; 700 u32 tDS_min; 701 u32 tFEAT_max; 702 u32 tIR_min; 703 u32 tITC_max; 704 u32 tRC_min; 705 u32 tREA_max; 706 u32 tREH_min; 707 u32 tRHOH_min; 708 u32 tRHW_min; 709 u32 tRHZ_max; 710 u32 tRLOH_min; 711 u32 tRP_min; 712 u32 tRR_min; 713 u64 tRST_max; 714 u32 tWB_max; 715 u32 tWC_min; 716 u32 tWH_min; 717 u32 tWHR_min; 718 u32 tWP_min; 719 u32 tWW_min; 720 }; 721 722 /** 723 * enum nand_data_interface_type - NAND interface timing type 724 * @NAND_SDR_IFACE: Single Data Rate interface 725 */ 726 enum nand_data_interface_type { 727 NAND_SDR_IFACE, 728 }; 729 730 /** 731 * struct nand_data_interface - NAND interface timing 732 * @type: type of the timing 733 * @timings: The timing, type according to @type 734 */ 735 struct nand_data_interface { 736 enum nand_data_interface_type type; 737 union { 738 struct nand_sdr_timings sdr; 739 } timings; 740 }; 741 742 /** 743 * nand_get_sdr_timings - get SDR timing from data interface 744 * @conf: The data interface 745 */ 746 static inline const struct nand_sdr_timings * 747 nand_get_sdr_timings(const struct nand_data_interface *conf) 748 { 749 if (conf->type != NAND_SDR_IFACE) 750 return ERR_PTR(-EINVAL); 751 752 return &conf->timings.sdr; 753 } 754 755 /** 756 * struct nand_chip - NAND Private Flash Chip Data 757 * @mtd: MTD device registered to the MTD framework 758 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 759 * flash device 760 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 761 * flash device. 762 * @flash_node: [BOARDSPECIFIC] device node describing this instance 763 * @read_byte: [REPLACEABLE] read one byte from the chip 764 * @read_word: [REPLACEABLE] read one word from the chip 765 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 766 * low 8 I/O lines 767 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 768 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 769 * @select_chip: [REPLACEABLE] select chip nr 770 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 771 * @block_markbad: [REPLACEABLE] mark a block bad 772 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 773 * ALE/CLE/nCE. Also used to write command and address 774 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 775 * device ready/busy line. If set to NULL no access to 776 * ready/busy is available and the ready/busy information 777 * is read from the chip status register. 778 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 779 * commands to the chip. 780 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 781 * ready. 782 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 783 * setting the read-retry mode. Mostly needed for MLC NAND. 784 * @ecc: [BOARDSPECIFIC] ECC control structure 785 * @buffers: buffer structure for read/write 786 * @buf_align: minimum buffer alignment required by a platform 787 * @hwcontrol: platform-specific hardware control structure 788 * @erase: [REPLACEABLE] erase function 789 * @scan_bbt: [REPLACEABLE] function to scan bad block table 790 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 791 * data from array to read regs (tR). 792 * @state: [INTERN] the current state of the NAND device 793 * @oob_poi: "poison value buffer," used for laying out OOB data 794 * before writing 795 * @page_shift: [INTERN] number of address bits in a page (column 796 * address bits). 797 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 798 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 799 * @chip_shift: [INTERN] number of address bits in one chip 800 * @options: [BOARDSPECIFIC] various chip options. They can partly 801 * be set to inform nand_scan about special functionality. 802 * See the defines for further explanation. 803 * @bbt_options: [INTERN] bad block specific options. All options used 804 * here must come from bbm.h. By default, these options 805 * will be copied to the appropriate nand_bbt_descr's. 806 * @badblockpos: [INTERN] position of the bad block marker in the oob 807 * area. 808 * @badblockbits: [INTERN] minimum number of set bits in a good block's 809 * bad block marker position; i.e., BBM == 11110111b is 810 * not bad when badblockbits == 7 811 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 812 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 813 * Minimum amount of bit errors per @ecc_step_ds guaranteed 814 * to be correctable. If unknown, set to zero. 815 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 816 * also from the datasheet. It is the recommended ECC step 817 * size, if known; if unknown, set to zero. 818 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 819 * set to the actually used ONFI mode if the chip is 820 * ONFI compliant or deduced from the datasheet if 821 * the NAND chip is not ONFI compliant. 822 * @numchips: [INTERN] number of physical chips 823 * @chipsize: [INTERN] the size of one chip for multichip arrays 824 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 825 * @pagebuf: [INTERN] holds the pagenumber which is currently in 826 * data_buf. 827 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 828 * currently in data_buf. 829 * @subpagesize: [INTERN] holds the subpagesize 830 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 831 * non 0 if ONFI supported. 832 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 833 * non 0 if JEDEC supported. 834 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 835 * supported, 0 otherwise. 836 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 837 * supported, 0 otherwise. 838 * @read_retries: [INTERN] the number of read retry modes supported 839 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 840 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 841 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 842 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 843 * means the configuration should not be applied but 844 * only checked. 845 * @bbt: [INTERN] bad block table pointer 846 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 847 * lookup. 848 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 849 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 850 * bad block scan. 851 * @controller: [REPLACEABLE] a pointer to a hardware controller 852 * structure which is shared among multiple independent 853 * devices. 854 * @priv: [OPTIONAL] pointer to private chip data 855 * @write_page: [REPLACEABLE] High-level page write function 856 */ 857 858 struct nand_chip { 859 struct mtd_info mtd; 860 void __iomem *IO_ADDR_R; 861 void __iomem *IO_ADDR_W; 862 863 int flash_node; 864 865 uint8_t (*read_byte)(struct mtd_info *mtd); 866 u16 (*read_word)(struct mtd_info *mtd); 867 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 868 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 869 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 870 void (*select_chip)(struct mtd_info *mtd, int chip); 871 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 872 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 873 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 874 int (*dev_ready)(struct mtd_info *mtd); 875 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 876 int page_addr); 877 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 878 int (*erase)(struct mtd_info *mtd, int page); 879 int (*scan_bbt)(struct mtd_info *mtd); 880 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 881 uint32_t offset, int data_len, const uint8_t *buf, 882 int oob_required, int page, int raw); 883 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 884 int feature_addr, uint8_t *subfeature_para); 885 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 886 int feature_addr, uint8_t *subfeature_para); 887 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 888 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 889 const struct nand_data_interface *conf); 890 891 892 int chip_delay; 893 unsigned int options; 894 unsigned int bbt_options; 895 896 int page_shift; 897 int phys_erase_shift; 898 int bbt_erase_shift; 899 int chip_shift; 900 int numchips; 901 uint64_t chipsize; 902 int pagemask; 903 int pagebuf; 904 unsigned int pagebuf_bitflips; 905 int subpagesize; 906 uint8_t bits_per_cell; 907 uint16_t ecc_strength_ds; 908 uint16_t ecc_step_ds; 909 int onfi_timing_mode_default; 910 int badblockpos; 911 int badblockbits; 912 913 int onfi_version; 914 int jedec_version; 915 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 916 struct nand_onfi_params onfi_params; 917 #endif 918 struct nand_jedec_params jedec_params; 919 920 struct nand_data_interface *data_interface; 921 922 int read_retries; 923 924 flstate_t state; 925 926 uint8_t *oob_poi; 927 struct nand_hw_control *controller; 928 struct nand_ecclayout *ecclayout; 929 930 struct nand_ecc_ctrl ecc; 931 struct nand_buffers *buffers; 932 unsigned long buf_align; 933 struct nand_hw_control hwcontrol; 934 935 uint8_t *bbt; 936 struct nand_bbt_descr *bbt_td; 937 struct nand_bbt_descr *bbt_md; 938 939 struct nand_bbt_descr *badblock_pattern; 940 941 void *priv; 942 }; 943 944 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 945 { 946 return container_of(mtd, struct nand_chip, mtd); 947 } 948 949 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 950 { 951 return &chip->mtd; 952 } 953 954 static inline void *nand_get_controller_data(struct nand_chip *chip) 955 { 956 return chip->priv; 957 } 958 959 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 960 { 961 chip->priv = priv; 962 } 963 964 /* 965 * NAND Flash Manufacturer ID Codes 966 */ 967 #define NAND_MFR_TOSHIBA 0x98 968 #define NAND_MFR_SAMSUNG 0xec 969 #define NAND_MFR_FUJITSU 0x04 970 #define NAND_MFR_NATIONAL 0x8f 971 #define NAND_MFR_RENESAS 0x07 972 #define NAND_MFR_STMICRO 0x20 973 #define NAND_MFR_HYNIX 0xad 974 #define NAND_MFR_MICRON 0x2c 975 #define NAND_MFR_AMD 0x01 976 #define NAND_MFR_MACRONIX 0xc2 977 #define NAND_MFR_EON 0x92 978 #define NAND_MFR_SANDISK 0x45 979 #define NAND_MFR_INTEL 0x89 980 #define NAND_MFR_ATO 0x9b 981 982 /* The maximum expected count of bytes in the NAND ID sequence */ 983 #define NAND_MAX_ID_LEN 8 984 985 /* 986 * A helper for defining older NAND chips where the second ID byte fully 987 * defined the chip, including the geometry (chip size, eraseblock size, page 988 * size). All these chips have 512 bytes NAND page size. 989 */ 990 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 991 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 992 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 993 994 /* 995 * A helper for defining newer chips which report their page size and 996 * eraseblock size via the extended ID bytes. 997 * 998 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 999 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1000 * device ID now only represented a particular total chip size (and voltage, 1001 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1002 * using the same device ID. 1003 */ 1004 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1005 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1006 .options = (opts) } 1007 1008 #define NAND_ECC_INFO(_strength, _step) \ 1009 { .strength_ds = (_strength), .step_ds = (_step) } 1010 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1011 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1012 1013 /** 1014 * struct nand_flash_dev - NAND Flash Device ID Structure 1015 * @name: a human-readable name of the NAND chip 1016 * @dev_id: the device ID (the second byte of the full chip ID array) 1017 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1018 * memory address as @id[0]) 1019 * @dev_id: device ID part of the full chip ID array (refers the same memory 1020 * address as @id[1]) 1021 * @id: full device ID array 1022 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1023 * well as the eraseblock size) is determined from the extended NAND 1024 * chip ID array) 1025 * @chipsize: total chip size in MiB 1026 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1027 * @options: stores various chip bit options 1028 * @id_len: The valid length of the @id. 1029 * @oobsize: OOB size 1030 * @ecc: ECC correctability and step information from the datasheet. 1031 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1032 * @ecc_strength_ds in nand_chip{}. 1033 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1034 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1035 * For example, the "4bit ECC for each 512Byte" can be set with 1036 * NAND_ECC_INFO(4, 512). 1037 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1038 * reset. Should be deduced from timings described 1039 * in the datasheet. 1040 * 1041 */ 1042 struct nand_flash_dev { 1043 char *name; 1044 union { 1045 struct { 1046 uint8_t mfr_id; 1047 uint8_t dev_id; 1048 }; 1049 uint8_t id[NAND_MAX_ID_LEN]; 1050 }; 1051 unsigned int pagesize; 1052 unsigned int chipsize; 1053 unsigned int erasesize; 1054 unsigned int options; 1055 uint16_t id_len; 1056 uint16_t oobsize; 1057 struct { 1058 uint16_t strength_ds; 1059 uint16_t step_ds; 1060 } ecc; 1061 int onfi_timing_mode_default; 1062 }; 1063 1064 /** 1065 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1066 * @name: Manufacturer name 1067 * @id: manufacturer ID code of device. 1068 */ 1069 struct nand_manufacturers { 1070 int id; 1071 char *name; 1072 }; 1073 1074 extern struct nand_flash_dev nand_flash_ids[]; 1075 extern struct nand_manufacturers nand_manuf_ids[]; 1076 1077 extern int nand_default_bbt(struct mtd_info *mtd); 1078 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1079 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1080 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1081 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1082 int allowbbt); 1083 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1084 size_t *retlen, uint8_t *buf); 1085 1086 /* 1087 * Constants for oob configuration 1088 */ 1089 #define NAND_SMALL_BADBLOCK_POS 5 1090 #define NAND_LARGE_BADBLOCK_POS 0 1091 1092 /** 1093 * struct platform_nand_chip - chip level device structure 1094 * @nr_chips: max. number of chips to scan for 1095 * @chip_offset: chip number offset 1096 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1097 * @partitions: mtd partition list 1098 * @chip_delay: R/B delay value in us 1099 * @options: Option flags, e.g. 16bit buswidth 1100 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1101 * @part_probe_types: NULL-terminated array of probe types 1102 */ 1103 struct platform_nand_chip { 1104 int nr_chips; 1105 int chip_offset; 1106 int nr_partitions; 1107 struct mtd_partition *partitions; 1108 int chip_delay; 1109 unsigned int options; 1110 unsigned int bbt_options; 1111 const char **part_probe_types; 1112 }; 1113 1114 /* Keep gcc happy */ 1115 struct platform_device; 1116 1117 /** 1118 * struct platform_nand_ctrl - controller level device structure 1119 * @probe: platform specific function to probe/setup hardware 1120 * @remove: platform specific function to remove/teardown hardware 1121 * @hwcontrol: platform specific hardware control structure 1122 * @dev_ready: platform specific function to read ready/busy pin 1123 * @select_chip: platform specific chip select function 1124 * @cmd_ctrl: platform specific function for controlling 1125 * ALE/CLE/nCE. Also used to write command and address 1126 * @write_buf: platform specific function for write buffer 1127 * @read_buf: platform specific function for read buffer 1128 * @read_byte: platform specific function to read one byte from chip 1129 * @priv: private data to transport driver specific settings 1130 * 1131 * All fields are optional and depend on the hardware driver requirements 1132 */ 1133 struct platform_nand_ctrl { 1134 int (*probe)(struct platform_device *pdev); 1135 void (*remove)(struct platform_device *pdev); 1136 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1137 int (*dev_ready)(struct mtd_info *mtd); 1138 void (*select_chip)(struct mtd_info *mtd, int chip); 1139 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1140 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1141 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1142 unsigned char (*read_byte)(struct mtd_info *mtd); 1143 void *priv; 1144 }; 1145 1146 /** 1147 * struct platform_nand_data - container structure for platform-specific data 1148 * @chip: chip level chip structure 1149 * @ctrl: controller level device structure 1150 */ 1151 struct platform_nand_data { 1152 struct platform_nand_chip chip; 1153 struct platform_nand_ctrl ctrl; 1154 }; 1155 1156 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1157 /* return the supported features. */ 1158 static inline int onfi_feature(struct nand_chip *chip) 1159 { 1160 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1161 } 1162 1163 /* return the supported asynchronous timing mode. */ 1164 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1165 { 1166 if (!chip->onfi_version) 1167 return ONFI_TIMING_MODE_UNKNOWN; 1168 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1169 } 1170 1171 /* return the supported synchronous timing mode. */ 1172 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1173 { 1174 if (!chip->onfi_version) 1175 return ONFI_TIMING_MODE_UNKNOWN; 1176 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1177 } 1178 #endif 1179 1180 int onfi_init_data_interface(struct nand_chip *chip, 1181 struct nand_data_interface *iface, 1182 enum nand_data_interface_type type, 1183 int timing_mode); 1184 1185 /* 1186 * Check if it is a SLC nand. 1187 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1188 * We do not distinguish the MLC and TLC now. 1189 */ 1190 static inline bool nand_is_slc(struct nand_chip *chip) 1191 { 1192 return chip->bits_per_cell == 1; 1193 } 1194 1195 /** 1196 * Check if the opcode's address should be sent only on the lower 8 bits 1197 * @command: opcode to check 1198 */ 1199 static inline int nand_opcode_8bits(unsigned int command) 1200 { 1201 switch (command) { 1202 case NAND_CMD_READID: 1203 case NAND_CMD_PARAM: 1204 case NAND_CMD_GET_FEATURES: 1205 case NAND_CMD_SET_FEATURES: 1206 return 1; 1207 default: 1208 break; 1209 } 1210 return 0; 1211 } 1212 1213 /* return the supported JEDEC features. */ 1214 static inline int jedec_feature(struct nand_chip *chip) 1215 { 1216 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1217 : 0; 1218 } 1219 1220 /* Standard NAND functions from nand_base.c */ 1221 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1222 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1223 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1224 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1225 uint8_t nand_read_byte(struct mtd_info *mtd); 1226 1227 /* get timing characteristics from ONFI timing mode. */ 1228 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1229 /* get data interface from ONFI timing mode 0, used after reset. */ 1230 const struct nand_data_interface *nand_get_default_data_interface(void); 1231 1232 int nand_check_erased_ecc_chunk(void *data, int datalen, 1233 void *ecc, int ecclen, 1234 void *extraoob, int extraooblen, 1235 int threshold); 1236 1237 int nand_check_ecc_caps(struct nand_chip *chip, 1238 const struct nand_ecc_caps *caps, int oobavail); 1239 1240 int nand_match_ecc_req(struct nand_chip *chip, 1241 const struct nand_ecc_caps *caps, int oobavail); 1242 1243 int nand_maximize_ecc(struct nand_chip *chip, 1244 const struct nand_ecc_caps *caps, int oobavail); 1245 1246 /* Reset and initialize a NAND device */ 1247 int nand_reset(struct nand_chip *chip, int chipnr); 1248 1249 /* NAND operation helpers */ 1250 int nand_reset_op(struct nand_chip *chip); 1251 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1252 unsigned int len); 1253 int nand_status_op(struct nand_chip *chip, u8 *status); 1254 int nand_exit_status_op(struct nand_chip *chip); 1255 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1256 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1257 unsigned int offset_in_page, void *buf, unsigned int len); 1258 int nand_change_read_column_op(struct nand_chip *chip, 1259 unsigned int offset_in_page, void *buf, 1260 unsigned int len, bool force_8bit); 1261 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1262 unsigned int offset_in_page, void *buf, unsigned int len); 1263 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1264 unsigned int offset_in_page, const void *buf, 1265 unsigned int len); 1266 int nand_prog_page_end_op(struct nand_chip *chip); 1267 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1268 unsigned int offset_in_page, const void *buf, 1269 unsigned int len); 1270 int nand_change_write_column_op(struct nand_chip *chip, 1271 unsigned int offset_in_page, const void *buf, 1272 unsigned int len, bool force_8bit); 1273 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1274 bool force_8bit); 1275 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1276 unsigned int len, bool force_8bit); 1277 1278 #endif /* __LINUX_MTD_RAWNAND_H */ 1279