1 /* 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 3 * Steven J. Hill <sjhill@realitydiluted.com> 4 * Thomas Gleixner <tglx@linutronix.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * Info: 9 * Contains standard defines and IDs for NAND flash devices 10 * 11 * Changelog: 12 * See git changelog. 13 */ 14 #ifndef __LINUX_MTD_RAWNAND_H 15 #define __LINUX_MTD_RAWNAND_H 16 17 #include <config.h> 18 19 #include <linux/compat.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/flashchip.h> 22 #include <linux/mtd/bbm.h> 23 24 struct mtd_info; 25 struct nand_flash_dev; 26 struct device_node; 27 28 /* Scan and identify a NAND device */ 29 extern int nand_scan(struct mtd_info *mtd, int max_chips); 30 /* 31 * Separate phases of nand_scan(), allowing board driver to intervene 32 * and override command or ECC setup according to flash type. 33 */ 34 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 35 struct nand_flash_dev *table); 36 extern int nand_scan_tail(struct mtd_info *mtd); 37 38 /* Free resources held by the NAND device */ 39 extern void nand_release(struct mtd_info *mtd); 40 41 /* Internal helper for board drivers which need to override command function */ 42 extern void nand_wait_ready(struct mtd_info *mtd); 43 44 /* 45 * This constant declares the max. oobsize / page, which 46 * is supported now. If you add a chip with bigger oobsize/page 47 * adjust this accordingly. 48 */ 49 #define NAND_MAX_OOBSIZE 1664 50 #define NAND_MAX_PAGESIZE 16384 51 52 /* 53 * Constants for hardware specific CLE/ALE/NCE function 54 * 55 * These are bits which can be or'ed to set/clear multiple 56 * bits in one go. 57 */ 58 /* Select the chip by setting nCE to low */ 59 #define NAND_NCE 0x01 60 /* Select the command latch by setting CLE to high */ 61 #define NAND_CLE 0x02 62 /* Select the address latch by setting ALE to high */ 63 #define NAND_ALE 0x04 64 65 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 66 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 67 #define NAND_CTRL_CHANGE 0x80 68 69 /* 70 * Standard NAND flash commands 71 */ 72 #define NAND_CMD_READ0 0 73 #define NAND_CMD_READ1 1 74 #define NAND_CMD_RNDOUT 5 75 #define NAND_CMD_PAGEPROG 0x10 76 #define NAND_CMD_READOOB 0x50 77 #define NAND_CMD_ERASE1 0x60 78 #define NAND_CMD_STATUS 0x70 79 #define NAND_CMD_SEQIN 0x80 80 #define NAND_CMD_RNDIN 0x85 81 #define NAND_CMD_READID 0x90 82 #define NAND_CMD_ERASE2 0xd0 83 #define NAND_CMD_PARAM 0xec 84 #define NAND_CMD_GET_FEATURES 0xee 85 #define NAND_CMD_SET_FEATURES 0xef 86 #define NAND_CMD_RESET 0xff 87 88 #define NAND_CMD_LOCK 0x2a 89 #define NAND_CMD_UNLOCK1 0x23 90 #define NAND_CMD_UNLOCK2 0x24 91 92 /* Extended commands for large page devices */ 93 #define NAND_CMD_READSTART 0x30 94 #define NAND_CMD_RNDOUTSTART 0xE0 95 #define NAND_CMD_CACHEDPROG 0x15 96 97 /* Extended commands for AG-AND device */ 98 /* 99 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 100 * there is no way to distinguish that from NAND_CMD_READ0 101 * until the remaining sequence of commands has been completed 102 * so add a high order bit and mask it off in the command. 103 */ 104 #define NAND_CMD_DEPLETE1 0x100 105 #define NAND_CMD_DEPLETE2 0x38 106 #define NAND_CMD_STATUS_MULTI 0x71 107 #define NAND_CMD_STATUS_ERROR 0x72 108 /* multi-bank error status (banks 0-3) */ 109 #define NAND_CMD_STATUS_ERROR0 0x73 110 #define NAND_CMD_STATUS_ERROR1 0x74 111 #define NAND_CMD_STATUS_ERROR2 0x75 112 #define NAND_CMD_STATUS_ERROR3 0x76 113 #define NAND_CMD_STATUS_RESET 0x7f 114 #define NAND_CMD_STATUS_CLEAR 0xff 115 116 #define NAND_CMD_NONE -1 117 118 /* Status bits */ 119 #define NAND_STATUS_FAIL 0x01 120 #define NAND_STATUS_FAIL_N1 0x02 121 #define NAND_STATUS_TRUE_READY 0x20 122 #define NAND_STATUS_READY 0x40 123 #define NAND_STATUS_WP 0x80 124 125 #define NAND_DATA_IFACE_CHECK_ONLY -1 126 127 /* 128 * Constants for ECC_MODES 129 */ 130 typedef enum { 131 NAND_ECC_NONE, 132 NAND_ECC_SOFT, 133 NAND_ECC_HW, 134 NAND_ECC_HW_SYNDROME, 135 NAND_ECC_HW_OOB_FIRST, 136 NAND_ECC_SOFT_BCH, 137 } nand_ecc_modes_t; 138 139 /* 140 * Constants for Hardware ECC 141 */ 142 /* Reset Hardware ECC for read */ 143 #define NAND_ECC_READ 0 144 /* Reset Hardware ECC for write */ 145 #define NAND_ECC_WRITE 1 146 /* Enable Hardware ECC before syndrome is read back from flash */ 147 #define NAND_ECC_READSYN 2 148 149 /* 150 * Enable generic NAND 'page erased' check. This check is only done when 151 * ecc.correct() returns -EBADMSG. 152 * Set this flag if your implementation does not fix bitflips in erased 153 * pages and you want to rely on the default implementation. 154 */ 155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 156 #define NAND_ECC_MAXIMIZE BIT(1) 157 /* 158 * If your controller already sends the required NAND commands when 159 * reading or writing a page, then the framework is not supposed to 160 * send READ0 and SEQIN/PAGEPROG respectively. 161 */ 162 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 163 164 /* Bit mask for flags passed to do_nand_read_ecc */ 165 #define NAND_GET_DEVICE 0x80 166 167 168 /* 169 * Option constants for bizarre disfunctionality and real 170 * features. 171 */ 172 /* Buswidth is 16 bit */ 173 #define NAND_BUSWIDTH_16 0x00000002 174 /* Device supports partial programming without padding */ 175 #define NAND_NO_PADDING 0x00000004 176 /* Chip has cache program function */ 177 #define NAND_CACHEPRG 0x00000008 178 /* Chip has copy back function */ 179 #define NAND_COPYBACK 0x00000010 180 /* 181 * Chip requires ready check on read (for auto-incremented sequential read). 182 * True only for small page devices; large page devices do not support 183 * autoincrement. 184 */ 185 #define NAND_NEED_READRDY 0x00000100 186 187 /* Chip does not allow subpage writes */ 188 #define NAND_NO_SUBPAGE_WRITE 0x00000200 189 190 /* Device is one of 'new' xD cards that expose fake nand command set */ 191 #define NAND_BROKEN_XD 0x00000400 192 193 /* Device behaves just like nand, but is readonly */ 194 #define NAND_ROM 0x00000800 195 196 /* Device supports subpage reads */ 197 #define NAND_SUBPAGE_READ 0x00001000 198 199 /* 200 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 201 * patterns. 202 */ 203 #define NAND_NEED_SCRAMBLING 0x00002000 204 205 /* Device needs 3rd row address cycle */ 206 #define NAND_ROW_ADDR_3 0x00004000 207 208 /* Options valid for Samsung large page devices */ 209 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 210 211 /* Macros to identify the above */ 212 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 213 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 214 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 215 216 /* Non chip related options */ 217 /* This option skips the bbt scan during initialization. */ 218 #define NAND_SKIP_BBTSCAN 0x00010000 219 /* 220 * This option is defined if the board driver allocates its own buffers 221 * (e.g. because it needs them DMA-coherent). 222 */ 223 #define NAND_OWN_BUFFERS 0x00020000 224 /* Chip may not exist, so silence any errors in scan */ 225 #define NAND_SCAN_SILENT_NODEV 0x00040000 226 /* 227 * Autodetect nand buswidth with readid/onfi. 228 * This suppose the driver will configure the hardware in 8 bits mode 229 * when calling nand_scan_ident, and update its configuration 230 * before calling nand_scan_tail. 231 */ 232 #define NAND_BUSWIDTH_AUTO 0x00080000 233 /* 234 * This option could be defined by controller drivers to protect against 235 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 236 */ 237 #define NAND_USE_BOUNCE_BUFFER 0x00100000 238 239 /* Options set by nand scan */ 240 /* bbt has already been read */ 241 #define NAND_BBT_SCANNED 0x40000000 242 /* Nand scan has allocated controller struct */ 243 #define NAND_CONTROLLER_ALLOC 0x80000000 244 245 /* Cell info constants */ 246 #define NAND_CI_CHIPNR_MSK 0x03 247 #define NAND_CI_CELLTYPE_MSK 0x0C 248 #define NAND_CI_CELLTYPE_SHIFT 2 249 250 /* Keep gcc happy */ 251 struct nand_chip; 252 253 /* ONFI features */ 254 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 255 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 256 257 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 258 #define ONFI_TIMING_MODE_0 (1 << 0) 259 #define ONFI_TIMING_MODE_1 (1 << 1) 260 #define ONFI_TIMING_MODE_2 (1 << 2) 261 #define ONFI_TIMING_MODE_3 (1 << 3) 262 #define ONFI_TIMING_MODE_4 (1 << 4) 263 #define ONFI_TIMING_MODE_5 (1 << 5) 264 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 265 266 /* ONFI feature address */ 267 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 268 269 /* Vendor-specific feature address (Micron) */ 270 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 271 272 /* ONFI subfeature parameters length */ 273 #define ONFI_SUBFEATURE_PARAM_LEN 4 274 275 /* ONFI optional commands SET/GET FEATURES supported? */ 276 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 277 278 struct nand_onfi_params { 279 /* rev info and features block */ 280 /* 'O' 'N' 'F' 'I' */ 281 u8 sig[4]; 282 __le16 revision; 283 __le16 features; 284 __le16 opt_cmd; 285 u8 reserved0[2]; 286 __le16 ext_param_page_length; /* since ONFI 2.1 */ 287 u8 num_of_param_pages; /* since ONFI 2.1 */ 288 u8 reserved1[17]; 289 290 /* manufacturer information block */ 291 char manufacturer[12]; 292 char model[20]; 293 u8 jedec_id; 294 __le16 date_code; 295 u8 reserved2[13]; 296 297 /* memory organization block */ 298 __le32 byte_per_page; 299 __le16 spare_bytes_per_page; 300 __le32 data_bytes_per_ppage; 301 __le16 spare_bytes_per_ppage; 302 __le32 pages_per_block; 303 __le32 blocks_per_lun; 304 u8 lun_count; 305 u8 addr_cycles; 306 u8 bits_per_cell; 307 __le16 bb_per_lun; 308 __le16 block_endurance; 309 u8 guaranteed_good_blocks; 310 __le16 guaranteed_block_endurance; 311 u8 programs_per_page; 312 u8 ppage_attr; 313 u8 ecc_bits; 314 u8 interleaved_bits; 315 u8 interleaved_ops; 316 u8 reserved3[13]; 317 318 /* electrical parameter block */ 319 u8 io_pin_capacitance_max; 320 __le16 async_timing_mode; 321 __le16 program_cache_timing_mode; 322 __le16 t_prog; 323 __le16 t_bers; 324 __le16 t_r; 325 __le16 t_ccs; 326 __le16 src_sync_timing_mode; 327 u8 src_ssync_features; 328 __le16 clk_pin_capacitance_typ; 329 __le16 io_pin_capacitance_typ; 330 __le16 input_pin_capacitance_typ; 331 u8 input_pin_capacitance_max; 332 u8 driver_strength_support; 333 __le16 t_int_r; 334 __le16 t_adl; 335 u8 reserved4[8]; 336 337 /* vendor */ 338 __le16 vendor_revision; 339 u8 vendor[88]; 340 341 __le16 crc; 342 } __packed; 343 344 #define ONFI_CRC_BASE 0x4F4E 345 346 /* Extended ECC information Block Definition (since ONFI 2.1) */ 347 struct onfi_ext_ecc_info { 348 u8 ecc_bits; 349 u8 codeword_size; 350 __le16 bb_per_lun; 351 __le16 block_endurance; 352 u8 reserved[2]; 353 } __packed; 354 355 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 356 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 357 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 358 struct onfi_ext_section { 359 u8 type; 360 u8 length; 361 } __packed; 362 363 #define ONFI_EXT_SECTION_MAX 8 364 365 /* Extended Parameter Page Definition (since ONFI 2.1) */ 366 struct onfi_ext_param_page { 367 __le16 crc; 368 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 369 u8 reserved0[10]; 370 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 371 372 /* 373 * The actual size of the Extended Parameter Page is in 374 * @ext_param_page_length of nand_onfi_params{}. 375 * The following are the variable length sections. 376 * So we do not add any fields below. Please see the ONFI spec. 377 */ 378 } __packed; 379 380 struct nand_onfi_vendor_micron { 381 u8 two_plane_read; 382 u8 read_cache; 383 u8 read_unique_id; 384 u8 dq_imped; 385 u8 dq_imped_num_settings; 386 u8 dq_imped_feat_addr; 387 u8 rb_pulldown_strength; 388 u8 rb_pulldown_strength_feat_addr; 389 u8 rb_pulldown_strength_num_settings; 390 u8 otp_mode; 391 u8 otp_page_start; 392 u8 otp_data_prot_addr; 393 u8 otp_num_pages; 394 u8 otp_feat_addr; 395 u8 read_retry_options; 396 u8 reserved[72]; 397 u8 param_revision; 398 } __packed; 399 400 struct jedec_ecc_info { 401 u8 ecc_bits; 402 u8 codeword_size; 403 __le16 bb_per_lun; 404 __le16 block_endurance; 405 u8 reserved[2]; 406 } __packed; 407 408 /* JEDEC features */ 409 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 410 411 struct nand_jedec_params { 412 /* rev info and features block */ 413 /* 'J' 'E' 'S' 'D' */ 414 u8 sig[4]; 415 __le16 revision; 416 __le16 features; 417 u8 opt_cmd[3]; 418 __le16 sec_cmd; 419 u8 num_of_param_pages; 420 u8 reserved0[18]; 421 422 /* manufacturer information block */ 423 char manufacturer[12]; 424 char model[20]; 425 u8 jedec_id[6]; 426 u8 reserved1[10]; 427 428 /* memory organization block */ 429 __le32 byte_per_page; 430 __le16 spare_bytes_per_page; 431 u8 reserved2[6]; 432 __le32 pages_per_block; 433 __le32 blocks_per_lun; 434 u8 lun_count; 435 u8 addr_cycles; 436 u8 bits_per_cell; 437 u8 programs_per_page; 438 u8 multi_plane_addr; 439 u8 multi_plane_op_attr; 440 u8 reserved3[38]; 441 442 /* electrical parameter block */ 443 __le16 async_sdr_speed_grade; 444 __le16 toggle_ddr_speed_grade; 445 __le16 sync_ddr_speed_grade; 446 u8 async_sdr_features; 447 u8 toggle_ddr_features; 448 u8 sync_ddr_features; 449 __le16 t_prog; 450 __le16 t_bers; 451 __le16 t_r; 452 __le16 t_r_multi_plane; 453 __le16 t_ccs; 454 __le16 io_pin_capacitance_typ; 455 __le16 input_pin_capacitance_typ; 456 __le16 clk_pin_capacitance_typ; 457 u8 driver_strength_support; 458 __le16 t_adl; 459 u8 reserved4[36]; 460 461 /* ECC and endurance block */ 462 u8 guaranteed_good_blocks; 463 __le16 guaranteed_block_endurance; 464 struct jedec_ecc_info ecc_info[4]; 465 u8 reserved5[29]; 466 467 /* reserved */ 468 u8 reserved6[148]; 469 470 /* vendor */ 471 __le16 vendor_rev_num; 472 u8 reserved7[88]; 473 474 /* CRC for Parameter Page */ 475 __le16 crc; 476 } __packed; 477 478 /** 479 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 480 * @lock: protection lock 481 * @active: the mtd device which holds the controller currently 482 * @wq: wait queue to sleep on if a NAND operation is in 483 * progress used instead of the per chip wait queue 484 * when a hw controller is available. 485 */ 486 struct nand_hw_control { 487 spinlock_t lock; 488 struct nand_chip *active; 489 }; 490 491 /** 492 * struct nand_ecc_step_info - ECC step information of ECC engine 493 * @stepsize: data bytes per ECC step 494 * @strengths: array of supported strengths 495 * @nstrengths: number of supported strengths 496 */ 497 struct nand_ecc_step_info { 498 int stepsize; 499 const int *strengths; 500 int nstrengths; 501 }; 502 503 /** 504 * struct nand_ecc_caps - capability of ECC engine 505 * @stepinfos: array of ECC step information 506 * @nstepinfos: number of ECC step information 507 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 508 */ 509 struct nand_ecc_caps { 510 const struct nand_ecc_step_info *stepinfos; 511 int nstepinfos; 512 int (*calc_ecc_bytes)(int step_size, int strength); 513 }; 514 515 /** 516 * struct nand_ecc_ctrl - Control structure for ECC 517 * @mode: ECC mode 518 * @steps: number of ECC steps per page 519 * @size: data bytes per ECC step 520 * @bytes: ECC bytes per step 521 * @strength: max number of correctible bits per ECC step 522 * @total: total number of ECC bytes per page 523 * @prepad: padding information for syndrome based ECC generators 524 * @postpad: padding information for syndrome based ECC generators 525 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 526 * @layout: ECC layout control struct pointer 527 * @priv: pointer to private ECC control data 528 * @hwctl: function to control hardware ECC generator. Must only 529 * be provided if an hardware ECC is available 530 * @calculate: function for ECC calculation or readback from ECC hardware 531 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 532 * Should return a positive number representing the number of 533 * corrected bitflips, -EBADMSG if the number of bitflips exceed 534 * ECC strength, or any other error code if the error is not 535 * directly related to correction. 536 * If -EBADMSG is returned the input buffers should be left 537 * untouched. 538 * @read_page_raw: function to read a raw page without ECC. This function 539 * should hide the specific layout used by the ECC 540 * controller and always return contiguous in-band and 541 * out-of-band data even if they're not stored 542 * contiguously on the NAND chip (e.g. 543 * NAND_ECC_HW_SYNDROME interleaves in-band and 544 * out-of-band data). 545 * @write_page_raw: function to write a raw page without ECC. This function 546 * should hide the specific layout used by the ECC 547 * controller and consider the passed data as contiguous 548 * in-band and out-of-band data. ECC controller is 549 * responsible for doing the appropriate transformations 550 * to adapt to its specific layout (e.g. 551 * NAND_ECC_HW_SYNDROME interleaves in-band and 552 * out-of-band data). 553 * @read_page: function to read a page according to the ECC generator 554 * requirements; returns maximum number of bitflips corrected in 555 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 556 * @read_subpage: function to read parts of the page covered by ECC; 557 * returns same as read_page() 558 * @write_subpage: function to write parts of the page covered by ECC. 559 * @write_page: function to write a page according to the ECC generator 560 * requirements. 561 * @write_oob_raw: function to write chip OOB data without ECC 562 * @read_oob_raw: function to read chip OOB data without ECC 563 * @read_oob: function to read chip OOB data 564 * @write_oob: function to write chip OOB data 565 */ 566 struct nand_ecc_ctrl { 567 nand_ecc_modes_t mode; 568 int steps; 569 int size; 570 int bytes; 571 int total; 572 int strength; 573 int prepad; 574 int postpad; 575 unsigned int options; 576 struct nand_ecclayout *layout; 577 void *priv; 578 void (*hwctl)(struct mtd_info *mtd, int mode); 579 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 580 uint8_t *ecc_code); 581 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 582 uint8_t *calc_ecc); 583 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 584 uint8_t *buf, int oob_required, int page); 585 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 586 const uint8_t *buf, int oob_required, int page); 587 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 588 uint8_t *buf, int oob_required, int page); 589 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 590 uint32_t offs, uint32_t len, uint8_t *buf, int page); 591 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 592 uint32_t offset, uint32_t data_len, 593 const uint8_t *data_buf, int oob_required, int page); 594 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 595 const uint8_t *buf, int oob_required, int page); 596 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 597 int page); 598 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 599 int page); 600 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 601 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 602 int page); 603 }; 604 605 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 606 { 607 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 608 } 609 610 /** 611 * struct nand_buffers - buffer structure for read/write 612 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 613 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 614 * @databuf: buffer pointer for data, size is (page size + oobsize). 615 * 616 * Do not change the order of buffers. databuf and oobrbuf must be in 617 * consecutive order. 618 */ 619 struct nand_buffers { 620 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 621 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 622 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 623 ARCH_DMA_MINALIGN)]; 624 }; 625 626 /** 627 * struct nand_sdr_timings - SDR NAND chip timings 628 * 629 * This struct defines the timing requirements of a SDR NAND chip. 630 * These information can be found in every NAND datasheets and the timings 631 * meaning are described in the ONFI specifications: 632 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 633 * Parameters) 634 * 635 * All these timings are expressed in picoseconds. 636 * 637 * @tBERS_max: Block erase time 638 * @tCCS_min: Change column setup time 639 * @tPROG_max: Page program time 640 * @tR_max: Page read time 641 * @tALH_min: ALE hold time 642 * @tADL_min: ALE to data loading time 643 * @tALS_min: ALE setup time 644 * @tAR_min: ALE to RE# delay 645 * @tCEA_max: CE# access time 646 * @tCEH_min: CE# high hold time 647 * @tCH_min: CE# hold time 648 * @tCHZ_max: CE# high to output hi-Z 649 * @tCLH_min: CLE hold time 650 * @tCLR_min: CLE to RE# delay 651 * @tCLS_min: CLE setup time 652 * @tCOH_min: CE# high to output hold 653 * @tCS_min: CE# setup time 654 * @tDH_min: Data hold time 655 * @tDS_min: Data setup time 656 * @tFEAT_max: Busy time for Set Features and Get Features 657 * @tIR_min: Output hi-Z to RE# low 658 * @tITC_max: Interface and Timing Mode Change time 659 * @tRC_min: RE# cycle time 660 * @tREA_max: RE# access time 661 * @tREH_min: RE# high hold time 662 * @tRHOH_min: RE# high to output hold 663 * @tRHW_min: RE# high to WE# low 664 * @tRHZ_max: RE# high to output hi-Z 665 * @tRLOH_min: RE# low to output hold 666 * @tRP_min: RE# pulse width 667 * @tRR_min: Ready to RE# low (data only) 668 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 669 * rising edge of R/B#. 670 * @tWB_max: WE# high to SR[6] low 671 * @tWC_min: WE# cycle time 672 * @tWH_min: WE# high hold time 673 * @tWHR_min: WE# high to RE# low 674 * @tWP_min: WE# pulse width 675 * @tWW_min: WP# transition to WE# low 676 */ 677 struct nand_sdr_timings { 678 u64 tBERS_max; 679 u32 tCCS_min; 680 u64 tPROG_max; 681 u64 tR_max; 682 u32 tALH_min; 683 u32 tADL_min; 684 u32 tALS_min; 685 u32 tAR_min; 686 u32 tCEA_max; 687 u32 tCEH_min; 688 u32 tCH_min; 689 u32 tCHZ_max; 690 u32 tCLH_min; 691 u32 tCLR_min; 692 u32 tCLS_min; 693 u32 tCOH_min; 694 u32 tCS_min; 695 u32 tDH_min; 696 u32 tDS_min; 697 u32 tFEAT_max; 698 u32 tIR_min; 699 u32 tITC_max; 700 u32 tRC_min; 701 u32 tREA_max; 702 u32 tREH_min; 703 u32 tRHOH_min; 704 u32 tRHW_min; 705 u32 tRHZ_max; 706 u32 tRLOH_min; 707 u32 tRP_min; 708 u32 tRR_min; 709 u64 tRST_max; 710 u32 tWB_max; 711 u32 tWC_min; 712 u32 tWH_min; 713 u32 tWHR_min; 714 u32 tWP_min; 715 u32 tWW_min; 716 }; 717 718 /** 719 * enum nand_data_interface_type - NAND interface timing type 720 * @NAND_SDR_IFACE: Single Data Rate interface 721 */ 722 enum nand_data_interface_type { 723 NAND_SDR_IFACE, 724 }; 725 726 /** 727 * struct nand_data_interface - NAND interface timing 728 * @type: type of the timing 729 * @timings: The timing, type according to @type 730 */ 731 struct nand_data_interface { 732 enum nand_data_interface_type type; 733 union { 734 struct nand_sdr_timings sdr; 735 } timings; 736 }; 737 738 /** 739 * nand_get_sdr_timings - get SDR timing from data interface 740 * @conf: The data interface 741 */ 742 static inline const struct nand_sdr_timings * 743 nand_get_sdr_timings(const struct nand_data_interface *conf) 744 { 745 if (conf->type != NAND_SDR_IFACE) 746 return ERR_PTR(-EINVAL); 747 748 return &conf->timings.sdr; 749 } 750 751 /** 752 * struct nand_chip - NAND Private Flash Chip Data 753 * @mtd: MTD device registered to the MTD framework 754 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 755 * flash device 756 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 757 * flash device. 758 * @flash_node: [BOARDSPECIFIC] device node describing this instance 759 * @read_byte: [REPLACEABLE] read one byte from the chip 760 * @read_word: [REPLACEABLE] read one word from the chip 761 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 762 * low 8 I/O lines 763 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 764 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 765 * @select_chip: [REPLACEABLE] select chip nr 766 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 767 * @block_markbad: [REPLACEABLE] mark a block bad 768 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 769 * ALE/CLE/nCE. Also used to write command and address 770 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 771 * device ready/busy line. If set to NULL no access to 772 * ready/busy is available and the ready/busy information 773 * is read from the chip status register. 774 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 775 * commands to the chip. 776 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 777 * ready. 778 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 779 * setting the read-retry mode. Mostly needed for MLC NAND. 780 * @ecc: [BOARDSPECIFIC] ECC control structure 781 * @buffers: buffer structure for read/write 782 * @buf_align: minimum buffer alignment required by a platform 783 * @hwcontrol: platform-specific hardware control structure 784 * @erase: [REPLACEABLE] erase function 785 * @scan_bbt: [REPLACEABLE] function to scan bad block table 786 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 787 * data from array to read regs (tR). 788 * @state: [INTERN] the current state of the NAND device 789 * @oob_poi: "poison value buffer," used for laying out OOB data 790 * before writing 791 * @page_shift: [INTERN] number of address bits in a page (column 792 * address bits). 793 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 794 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 795 * @chip_shift: [INTERN] number of address bits in one chip 796 * @options: [BOARDSPECIFIC] various chip options. They can partly 797 * be set to inform nand_scan about special functionality. 798 * See the defines for further explanation. 799 * @bbt_options: [INTERN] bad block specific options. All options used 800 * here must come from bbm.h. By default, these options 801 * will be copied to the appropriate nand_bbt_descr's. 802 * @badblockpos: [INTERN] position of the bad block marker in the oob 803 * area. 804 * @badblockbits: [INTERN] minimum number of set bits in a good block's 805 * bad block marker position; i.e., BBM == 11110111b is 806 * not bad when badblockbits == 7 807 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 808 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 809 * Minimum amount of bit errors per @ecc_step_ds guaranteed 810 * to be correctable. If unknown, set to zero. 811 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 812 * also from the datasheet. It is the recommended ECC step 813 * size, if known; if unknown, set to zero. 814 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 815 * set to the actually used ONFI mode if the chip is 816 * ONFI compliant or deduced from the datasheet if 817 * the NAND chip is not ONFI compliant. 818 * @numchips: [INTERN] number of physical chips 819 * @chipsize: [INTERN] the size of one chip for multichip arrays 820 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 821 * @pagebuf: [INTERN] holds the pagenumber which is currently in 822 * data_buf. 823 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 824 * currently in data_buf. 825 * @subpagesize: [INTERN] holds the subpagesize 826 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 827 * non 0 if ONFI supported. 828 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 829 * non 0 if JEDEC supported. 830 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 831 * supported, 0 otherwise. 832 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 833 * supported, 0 otherwise. 834 * @read_retries: [INTERN] the number of read retry modes supported 835 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 836 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 837 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 838 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 839 * means the configuration should not be applied but 840 * only checked. 841 * @bbt: [INTERN] bad block table pointer 842 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 843 * lookup. 844 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 845 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 846 * bad block scan. 847 * @controller: [REPLACEABLE] a pointer to a hardware controller 848 * structure which is shared among multiple independent 849 * devices. 850 * @priv: [OPTIONAL] pointer to private chip data 851 * @write_page: [REPLACEABLE] High-level page write function 852 */ 853 854 struct nand_chip { 855 struct mtd_info mtd; 856 void __iomem *IO_ADDR_R; 857 void __iomem *IO_ADDR_W; 858 859 int flash_node; 860 861 uint8_t (*read_byte)(struct mtd_info *mtd); 862 u16 (*read_word)(struct mtd_info *mtd); 863 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 864 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 865 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 866 void (*select_chip)(struct mtd_info *mtd, int chip); 867 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 868 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 869 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 870 int (*dev_ready)(struct mtd_info *mtd); 871 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 872 int page_addr); 873 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 874 int (*erase)(struct mtd_info *mtd, int page); 875 int (*scan_bbt)(struct mtd_info *mtd); 876 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 877 uint32_t offset, int data_len, const uint8_t *buf, 878 int oob_required, int page, int raw); 879 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 880 int feature_addr, uint8_t *subfeature_para); 881 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 882 int feature_addr, uint8_t *subfeature_para); 883 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 884 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 885 const struct nand_data_interface *conf); 886 887 888 int chip_delay; 889 unsigned int options; 890 unsigned int bbt_options; 891 892 int page_shift; 893 int phys_erase_shift; 894 int bbt_erase_shift; 895 int chip_shift; 896 int numchips; 897 uint64_t chipsize; 898 int pagemask; 899 int pagebuf; 900 unsigned int pagebuf_bitflips; 901 int subpagesize; 902 uint8_t bits_per_cell; 903 uint16_t ecc_strength_ds; 904 uint16_t ecc_step_ds; 905 int onfi_timing_mode_default; 906 int badblockpos; 907 int badblockbits; 908 909 int onfi_version; 910 int jedec_version; 911 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 912 struct nand_onfi_params onfi_params; 913 #endif 914 struct nand_jedec_params jedec_params; 915 916 struct nand_data_interface *data_interface; 917 918 int read_retries; 919 920 flstate_t state; 921 922 uint8_t *oob_poi; 923 struct nand_hw_control *controller; 924 struct nand_ecclayout *ecclayout; 925 926 struct nand_ecc_ctrl ecc; 927 struct nand_buffers *buffers; 928 unsigned long buf_align; 929 struct nand_hw_control hwcontrol; 930 931 uint8_t *bbt; 932 struct nand_bbt_descr *bbt_td; 933 struct nand_bbt_descr *bbt_md; 934 935 struct nand_bbt_descr *badblock_pattern; 936 937 void *priv; 938 }; 939 940 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 941 { 942 return container_of(mtd, struct nand_chip, mtd); 943 } 944 945 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 946 { 947 return &chip->mtd; 948 } 949 950 static inline void *nand_get_controller_data(struct nand_chip *chip) 951 { 952 return chip->priv; 953 } 954 955 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 956 { 957 chip->priv = priv; 958 } 959 960 /* 961 * NAND Flash Manufacturer ID Codes 962 */ 963 #define NAND_MFR_TOSHIBA 0x98 964 #define NAND_MFR_SAMSUNG 0xec 965 #define NAND_MFR_FUJITSU 0x04 966 #define NAND_MFR_NATIONAL 0x8f 967 #define NAND_MFR_RENESAS 0x07 968 #define NAND_MFR_STMICRO 0x20 969 #define NAND_MFR_HYNIX 0xad 970 #define NAND_MFR_MICRON 0x2c 971 #define NAND_MFR_AMD 0x01 972 #define NAND_MFR_MACRONIX 0xc2 973 #define NAND_MFR_EON 0x92 974 #define NAND_MFR_SANDISK 0x45 975 #define NAND_MFR_INTEL 0x89 976 #define NAND_MFR_ATO 0x9b 977 978 /* The maximum expected count of bytes in the NAND ID sequence */ 979 #define NAND_MAX_ID_LEN 8 980 981 /* 982 * A helper for defining older NAND chips where the second ID byte fully 983 * defined the chip, including the geometry (chip size, eraseblock size, page 984 * size). All these chips have 512 bytes NAND page size. 985 */ 986 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 987 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 988 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 989 990 /* 991 * A helper for defining newer chips which report their page size and 992 * eraseblock size via the extended ID bytes. 993 * 994 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 995 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 996 * device ID now only represented a particular total chip size (and voltage, 997 * buswidth), and the page size, eraseblock size, and OOB size could vary while 998 * using the same device ID. 999 */ 1000 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1001 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1002 .options = (opts) } 1003 1004 #define NAND_ECC_INFO(_strength, _step) \ 1005 { .strength_ds = (_strength), .step_ds = (_step) } 1006 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1007 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1008 1009 /** 1010 * struct nand_flash_dev - NAND Flash Device ID Structure 1011 * @name: a human-readable name of the NAND chip 1012 * @dev_id: the device ID (the second byte of the full chip ID array) 1013 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1014 * memory address as @id[0]) 1015 * @dev_id: device ID part of the full chip ID array (refers the same memory 1016 * address as @id[1]) 1017 * @id: full device ID array 1018 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1019 * well as the eraseblock size) is determined from the extended NAND 1020 * chip ID array) 1021 * @chipsize: total chip size in MiB 1022 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1023 * @options: stores various chip bit options 1024 * @id_len: The valid length of the @id. 1025 * @oobsize: OOB size 1026 * @ecc: ECC correctability and step information from the datasheet. 1027 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1028 * @ecc_strength_ds in nand_chip{}. 1029 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1030 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1031 * For example, the "4bit ECC for each 512Byte" can be set with 1032 * NAND_ECC_INFO(4, 512). 1033 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1034 * reset. Should be deduced from timings described 1035 * in the datasheet. 1036 * 1037 */ 1038 struct nand_flash_dev { 1039 char *name; 1040 union { 1041 struct { 1042 uint8_t mfr_id; 1043 uint8_t dev_id; 1044 }; 1045 uint8_t id[NAND_MAX_ID_LEN]; 1046 }; 1047 unsigned int pagesize; 1048 unsigned int chipsize; 1049 unsigned int erasesize; 1050 unsigned int options; 1051 uint16_t id_len; 1052 uint16_t oobsize; 1053 struct { 1054 uint16_t strength_ds; 1055 uint16_t step_ds; 1056 } ecc; 1057 int onfi_timing_mode_default; 1058 }; 1059 1060 /** 1061 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1062 * @name: Manufacturer name 1063 * @id: manufacturer ID code of device. 1064 */ 1065 struct nand_manufacturers { 1066 int id; 1067 char *name; 1068 }; 1069 1070 extern struct nand_flash_dev nand_flash_ids[]; 1071 extern struct nand_manufacturers nand_manuf_ids[]; 1072 1073 extern int nand_default_bbt(struct mtd_info *mtd); 1074 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1075 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1076 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1077 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1078 int allowbbt); 1079 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1080 size_t *retlen, uint8_t *buf); 1081 1082 /* 1083 * Constants for oob configuration 1084 */ 1085 #define NAND_SMALL_BADBLOCK_POS 5 1086 #define NAND_LARGE_BADBLOCK_POS 0 1087 1088 /** 1089 * struct platform_nand_chip - chip level device structure 1090 * @nr_chips: max. number of chips to scan for 1091 * @chip_offset: chip number offset 1092 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1093 * @partitions: mtd partition list 1094 * @chip_delay: R/B delay value in us 1095 * @options: Option flags, e.g. 16bit buswidth 1096 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1097 * @part_probe_types: NULL-terminated array of probe types 1098 */ 1099 struct platform_nand_chip { 1100 int nr_chips; 1101 int chip_offset; 1102 int nr_partitions; 1103 struct mtd_partition *partitions; 1104 int chip_delay; 1105 unsigned int options; 1106 unsigned int bbt_options; 1107 const char **part_probe_types; 1108 }; 1109 1110 /* Keep gcc happy */ 1111 struct platform_device; 1112 1113 /** 1114 * struct platform_nand_ctrl - controller level device structure 1115 * @probe: platform specific function to probe/setup hardware 1116 * @remove: platform specific function to remove/teardown hardware 1117 * @hwcontrol: platform specific hardware control structure 1118 * @dev_ready: platform specific function to read ready/busy pin 1119 * @select_chip: platform specific chip select function 1120 * @cmd_ctrl: platform specific function for controlling 1121 * ALE/CLE/nCE. Also used to write command and address 1122 * @write_buf: platform specific function for write buffer 1123 * @read_buf: platform specific function for read buffer 1124 * @read_byte: platform specific function to read one byte from chip 1125 * @priv: private data to transport driver specific settings 1126 * 1127 * All fields are optional and depend on the hardware driver requirements 1128 */ 1129 struct platform_nand_ctrl { 1130 int (*probe)(struct platform_device *pdev); 1131 void (*remove)(struct platform_device *pdev); 1132 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1133 int (*dev_ready)(struct mtd_info *mtd); 1134 void (*select_chip)(struct mtd_info *mtd, int chip); 1135 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1136 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1137 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1138 unsigned char (*read_byte)(struct mtd_info *mtd); 1139 void *priv; 1140 }; 1141 1142 /** 1143 * struct platform_nand_data - container structure for platform-specific data 1144 * @chip: chip level chip structure 1145 * @ctrl: controller level device structure 1146 */ 1147 struct platform_nand_data { 1148 struct platform_nand_chip chip; 1149 struct platform_nand_ctrl ctrl; 1150 }; 1151 1152 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1153 /* return the supported features. */ 1154 static inline int onfi_feature(struct nand_chip *chip) 1155 { 1156 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1157 } 1158 1159 /* return the supported asynchronous timing mode. */ 1160 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1161 { 1162 if (!chip->onfi_version) 1163 return ONFI_TIMING_MODE_UNKNOWN; 1164 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1165 } 1166 1167 /* return the supported synchronous timing mode. */ 1168 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1169 { 1170 if (!chip->onfi_version) 1171 return ONFI_TIMING_MODE_UNKNOWN; 1172 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1173 } 1174 #endif 1175 1176 int onfi_init_data_interface(struct nand_chip *chip, 1177 struct nand_data_interface *iface, 1178 enum nand_data_interface_type type, 1179 int timing_mode); 1180 1181 /* 1182 * Check if it is a SLC nand. 1183 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1184 * We do not distinguish the MLC and TLC now. 1185 */ 1186 static inline bool nand_is_slc(struct nand_chip *chip) 1187 { 1188 return chip->bits_per_cell == 1; 1189 } 1190 1191 /** 1192 * Check if the opcode's address should be sent only on the lower 8 bits 1193 * @command: opcode to check 1194 */ 1195 static inline int nand_opcode_8bits(unsigned int command) 1196 { 1197 switch (command) { 1198 case NAND_CMD_READID: 1199 case NAND_CMD_PARAM: 1200 case NAND_CMD_GET_FEATURES: 1201 case NAND_CMD_SET_FEATURES: 1202 return 1; 1203 default: 1204 break; 1205 } 1206 return 0; 1207 } 1208 1209 /* return the supported JEDEC features. */ 1210 static inline int jedec_feature(struct nand_chip *chip) 1211 { 1212 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1213 : 0; 1214 } 1215 1216 /* Standard NAND functions from nand_base.c */ 1217 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1218 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1219 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1220 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1221 uint8_t nand_read_byte(struct mtd_info *mtd); 1222 1223 /* get timing characteristics from ONFI timing mode. */ 1224 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1225 /* get data interface from ONFI timing mode 0, used after reset. */ 1226 const struct nand_data_interface *nand_get_default_data_interface(void); 1227 1228 int nand_check_erased_ecc_chunk(void *data, int datalen, 1229 void *ecc, int ecclen, 1230 void *extraoob, int extraooblen, 1231 int threshold); 1232 1233 int nand_check_ecc_caps(struct nand_chip *chip, 1234 const struct nand_ecc_caps *caps, int oobavail); 1235 1236 int nand_match_ecc_req(struct nand_chip *chip, 1237 const struct nand_ecc_caps *caps, int oobavail); 1238 1239 int nand_maximize_ecc(struct nand_chip *chip, 1240 const struct nand_ecc_caps *caps, int oobavail); 1241 1242 /* Reset and initialize a NAND device */ 1243 int nand_reset(struct nand_chip *chip, int chipnr); 1244 #endif /* __LINUX_MTD_RAWNAND_H */ 1245