1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #include <config.h> 20 21 #include <linux/compat.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 extern int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 extern int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Free resources held by the NAND device */ 41 extern void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 extern void nand_wait_ready(struct mtd_info *mtd); 45 46 /* 47 * This constant declares the max. oobsize / page, which 48 * is supported now. If you add a chip with bigger oobsize/page 49 * adjust this accordingly. 50 */ 51 #define NAND_MAX_OOBSIZE 1664 52 #define NAND_MAX_PAGESIZE 16384 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 /* Extended commands for AG-AND device */ 100 /* 101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 102 * there is no way to distinguish that from NAND_CMD_READ0 103 * until the remaining sequence of commands has been completed 104 * so add a high order bit and mask it off in the command. 105 */ 106 #define NAND_CMD_DEPLETE1 0x100 107 #define NAND_CMD_DEPLETE2 0x38 108 #define NAND_CMD_STATUS_MULTI 0x71 109 #define NAND_CMD_STATUS_ERROR 0x72 110 /* multi-bank error status (banks 0-3) */ 111 #define NAND_CMD_STATUS_ERROR0 0x73 112 #define NAND_CMD_STATUS_ERROR1 0x74 113 #define NAND_CMD_STATUS_ERROR2 0x75 114 #define NAND_CMD_STATUS_ERROR3 0x76 115 #define NAND_CMD_STATUS_RESET 0x7f 116 #define NAND_CMD_STATUS_CLEAR 0xff 117 118 #define NAND_CMD_NONE -1 119 120 /* Status bits */ 121 #define NAND_STATUS_FAIL 0x01 122 #define NAND_STATUS_FAIL_N1 0x02 123 #define NAND_STATUS_TRUE_READY 0x20 124 #define NAND_STATUS_READY 0x40 125 #define NAND_STATUS_WP 0x80 126 127 /* 128 * Constants for ECC_MODES 129 */ 130 typedef enum { 131 NAND_ECC_NONE, 132 NAND_ECC_SOFT, 133 NAND_ECC_HW, 134 NAND_ECC_HW_SYNDROME, 135 NAND_ECC_HW_OOB_FIRST, 136 NAND_ECC_SOFT_BCH, 137 } nand_ecc_modes_t; 138 139 /* 140 * Constants for Hardware ECC 141 */ 142 /* Reset Hardware ECC for read */ 143 #define NAND_ECC_READ 0 144 /* Reset Hardware ECC for write */ 145 #define NAND_ECC_WRITE 1 146 /* Enable Hardware ECC before syndrome is read back from flash */ 147 #define NAND_ECC_READSYN 2 148 149 /* 150 * Enable generic NAND 'page erased' check. This check is only done when 151 * ecc.correct() returns -EBADMSG. 152 * Set this flag if your implementation does not fix bitflips in erased 153 * pages and you want to rely on the default implementation. 154 */ 155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 156 #define NAND_ECC_MAXIMIZE BIT(1) 157 /* 158 * If your controller already sends the required NAND commands when 159 * reading or writing a page, then the framework is not supposed to 160 * send READ0 and SEQIN/PAGEPROG respectively. 161 */ 162 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 163 164 /* Bit mask for flags passed to do_nand_read_ecc */ 165 #define NAND_GET_DEVICE 0x80 166 167 168 /* 169 * Option constants for bizarre disfunctionality and real 170 * features. 171 */ 172 /* Buswidth is 16 bit */ 173 #define NAND_BUSWIDTH_16 0x00000002 174 /* Device supports partial programming without padding */ 175 #define NAND_NO_PADDING 0x00000004 176 /* Chip has cache program function */ 177 #define NAND_CACHEPRG 0x00000008 178 /* Chip has copy back function */ 179 #define NAND_COPYBACK 0x00000010 180 /* 181 * Chip requires ready check on read (for auto-incremented sequential read). 182 * True only for small page devices; large page devices do not support 183 * autoincrement. 184 */ 185 #define NAND_NEED_READRDY 0x00000100 186 187 /* Chip does not allow subpage writes */ 188 #define NAND_NO_SUBPAGE_WRITE 0x00000200 189 190 /* Device is one of 'new' xD cards that expose fake nand command set */ 191 #define NAND_BROKEN_XD 0x00000400 192 193 /* Device behaves just like nand, but is readonly */ 194 #define NAND_ROM 0x00000800 195 196 /* Device supports subpage reads */ 197 #define NAND_SUBPAGE_READ 0x00001000 198 199 /* 200 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 201 * patterns. 202 */ 203 #define NAND_NEED_SCRAMBLING 0x00002000 204 205 /* Options valid for Samsung large page devices */ 206 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 207 208 /* Macros to identify the above */ 209 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 210 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 211 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 212 213 /* Non chip related options */ 214 /* This option skips the bbt scan during initialization. */ 215 #define NAND_SKIP_BBTSCAN 0x00010000 216 /* 217 * This option is defined if the board driver allocates its own buffers 218 * (e.g. because it needs them DMA-coherent). 219 */ 220 #define NAND_OWN_BUFFERS 0x00020000 221 /* Chip may not exist, so silence any errors in scan */ 222 #define NAND_SCAN_SILENT_NODEV 0x00040000 223 /* 224 * Autodetect nand buswidth with readid/onfi. 225 * This suppose the driver will configure the hardware in 8 bits mode 226 * when calling nand_scan_ident, and update its configuration 227 * before calling nand_scan_tail. 228 */ 229 #define NAND_BUSWIDTH_AUTO 0x00080000 230 /* 231 * This option could be defined by controller drivers to protect against 232 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 233 */ 234 #define NAND_USE_BOUNCE_BUFFER 0x00100000 235 236 /* Options set by nand scan */ 237 /* bbt has already been read */ 238 #define NAND_BBT_SCANNED 0x40000000 239 /* Nand scan has allocated controller struct */ 240 #define NAND_CONTROLLER_ALLOC 0x80000000 241 242 /* Cell info constants */ 243 #define NAND_CI_CHIPNR_MSK 0x03 244 #define NAND_CI_CELLTYPE_MSK 0x0C 245 #define NAND_CI_CELLTYPE_SHIFT 2 246 247 /* Keep gcc happy */ 248 struct nand_chip; 249 250 /* ONFI features */ 251 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 252 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 253 254 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 255 #define ONFI_TIMING_MODE_0 (1 << 0) 256 #define ONFI_TIMING_MODE_1 (1 << 1) 257 #define ONFI_TIMING_MODE_2 (1 << 2) 258 #define ONFI_TIMING_MODE_3 (1 << 3) 259 #define ONFI_TIMING_MODE_4 (1 << 4) 260 #define ONFI_TIMING_MODE_5 (1 << 5) 261 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 262 263 /* ONFI feature address */ 264 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 265 266 /* Vendor-specific feature address (Micron) */ 267 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 268 269 /* ONFI subfeature parameters length */ 270 #define ONFI_SUBFEATURE_PARAM_LEN 4 271 272 /* ONFI optional commands SET/GET FEATURES supported? */ 273 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 274 275 struct nand_onfi_params { 276 /* rev info and features block */ 277 /* 'O' 'N' 'F' 'I' */ 278 u8 sig[4]; 279 __le16 revision; 280 __le16 features; 281 __le16 opt_cmd; 282 u8 reserved0[2]; 283 __le16 ext_param_page_length; /* since ONFI 2.1 */ 284 u8 num_of_param_pages; /* since ONFI 2.1 */ 285 u8 reserved1[17]; 286 287 /* manufacturer information block */ 288 char manufacturer[12]; 289 char model[20]; 290 u8 jedec_id; 291 __le16 date_code; 292 u8 reserved2[13]; 293 294 /* memory organization block */ 295 __le32 byte_per_page; 296 __le16 spare_bytes_per_page; 297 __le32 data_bytes_per_ppage; 298 __le16 spare_bytes_per_ppage; 299 __le32 pages_per_block; 300 __le32 blocks_per_lun; 301 u8 lun_count; 302 u8 addr_cycles; 303 u8 bits_per_cell; 304 __le16 bb_per_lun; 305 __le16 block_endurance; 306 u8 guaranteed_good_blocks; 307 __le16 guaranteed_block_endurance; 308 u8 programs_per_page; 309 u8 ppage_attr; 310 u8 ecc_bits; 311 u8 interleaved_bits; 312 u8 interleaved_ops; 313 u8 reserved3[13]; 314 315 /* electrical parameter block */ 316 u8 io_pin_capacitance_max; 317 __le16 async_timing_mode; 318 __le16 program_cache_timing_mode; 319 __le16 t_prog; 320 __le16 t_bers; 321 __le16 t_r; 322 __le16 t_ccs; 323 __le16 src_sync_timing_mode; 324 u8 src_ssync_features; 325 __le16 clk_pin_capacitance_typ; 326 __le16 io_pin_capacitance_typ; 327 __le16 input_pin_capacitance_typ; 328 u8 input_pin_capacitance_max; 329 u8 driver_strength_support; 330 __le16 t_int_r; 331 __le16 t_adl; 332 u8 reserved4[8]; 333 334 /* vendor */ 335 __le16 vendor_revision; 336 u8 vendor[88]; 337 338 __le16 crc; 339 } __packed; 340 341 #define ONFI_CRC_BASE 0x4F4E 342 343 /* Extended ECC information Block Definition (since ONFI 2.1) */ 344 struct onfi_ext_ecc_info { 345 u8 ecc_bits; 346 u8 codeword_size; 347 __le16 bb_per_lun; 348 __le16 block_endurance; 349 u8 reserved[2]; 350 } __packed; 351 352 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 353 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 354 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 355 struct onfi_ext_section { 356 u8 type; 357 u8 length; 358 } __packed; 359 360 #define ONFI_EXT_SECTION_MAX 8 361 362 /* Extended Parameter Page Definition (since ONFI 2.1) */ 363 struct onfi_ext_param_page { 364 __le16 crc; 365 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 366 u8 reserved0[10]; 367 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 368 369 /* 370 * The actual size of the Extended Parameter Page is in 371 * @ext_param_page_length of nand_onfi_params{}. 372 * The following are the variable length sections. 373 * So we do not add any fields below. Please see the ONFI spec. 374 */ 375 } __packed; 376 377 struct nand_onfi_vendor_micron { 378 u8 two_plane_read; 379 u8 read_cache; 380 u8 read_unique_id; 381 u8 dq_imped; 382 u8 dq_imped_num_settings; 383 u8 dq_imped_feat_addr; 384 u8 rb_pulldown_strength; 385 u8 rb_pulldown_strength_feat_addr; 386 u8 rb_pulldown_strength_num_settings; 387 u8 otp_mode; 388 u8 otp_page_start; 389 u8 otp_data_prot_addr; 390 u8 otp_num_pages; 391 u8 otp_feat_addr; 392 u8 read_retry_options; 393 u8 reserved[72]; 394 u8 param_revision; 395 } __packed; 396 397 struct jedec_ecc_info { 398 u8 ecc_bits; 399 u8 codeword_size; 400 __le16 bb_per_lun; 401 __le16 block_endurance; 402 u8 reserved[2]; 403 } __packed; 404 405 /* JEDEC features */ 406 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 407 408 struct nand_jedec_params { 409 /* rev info and features block */ 410 /* 'J' 'E' 'S' 'D' */ 411 u8 sig[4]; 412 __le16 revision; 413 __le16 features; 414 u8 opt_cmd[3]; 415 __le16 sec_cmd; 416 u8 num_of_param_pages; 417 u8 reserved0[18]; 418 419 /* manufacturer information block */ 420 char manufacturer[12]; 421 char model[20]; 422 u8 jedec_id[6]; 423 u8 reserved1[10]; 424 425 /* memory organization block */ 426 __le32 byte_per_page; 427 __le16 spare_bytes_per_page; 428 u8 reserved2[6]; 429 __le32 pages_per_block; 430 __le32 blocks_per_lun; 431 u8 lun_count; 432 u8 addr_cycles; 433 u8 bits_per_cell; 434 u8 programs_per_page; 435 u8 multi_plane_addr; 436 u8 multi_plane_op_attr; 437 u8 reserved3[38]; 438 439 /* electrical parameter block */ 440 __le16 async_sdr_speed_grade; 441 __le16 toggle_ddr_speed_grade; 442 __le16 sync_ddr_speed_grade; 443 u8 async_sdr_features; 444 u8 toggle_ddr_features; 445 u8 sync_ddr_features; 446 __le16 t_prog; 447 __le16 t_bers; 448 __le16 t_r; 449 __le16 t_r_multi_plane; 450 __le16 t_ccs; 451 __le16 io_pin_capacitance_typ; 452 __le16 input_pin_capacitance_typ; 453 __le16 clk_pin_capacitance_typ; 454 u8 driver_strength_support; 455 __le16 t_adl; 456 u8 reserved4[36]; 457 458 /* ECC and endurance block */ 459 u8 guaranteed_good_blocks; 460 __le16 guaranteed_block_endurance; 461 struct jedec_ecc_info ecc_info[4]; 462 u8 reserved5[29]; 463 464 /* reserved */ 465 u8 reserved6[148]; 466 467 /* vendor */ 468 __le16 vendor_rev_num; 469 u8 reserved7[88]; 470 471 /* CRC for Parameter Page */ 472 __le16 crc; 473 } __packed; 474 475 /** 476 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 477 * @lock: protection lock 478 * @active: the mtd device which holds the controller currently 479 * @wq: wait queue to sleep on if a NAND operation is in 480 * progress used instead of the per chip wait queue 481 * when a hw controller is available. 482 */ 483 struct nand_hw_control { 484 spinlock_t lock; 485 struct nand_chip *active; 486 }; 487 488 /** 489 * struct nand_ecc_ctrl - Control structure for ECC 490 * @mode: ECC mode 491 * @steps: number of ECC steps per page 492 * @size: data bytes per ECC step 493 * @bytes: ECC bytes per step 494 * @strength: max number of correctible bits per ECC step 495 * @total: total number of ECC bytes per page 496 * @prepad: padding information for syndrome based ECC generators 497 * @postpad: padding information for syndrome based ECC generators 498 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 499 * @layout: ECC layout control struct pointer 500 * @priv: pointer to private ECC control data 501 * @hwctl: function to control hardware ECC generator. Must only 502 * be provided if an hardware ECC is available 503 * @calculate: function for ECC calculation or readback from ECC hardware 504 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 505 * Should return a positive number representing the number of 506 * corrected bitflips, -EBADMSG if the number of bitflips exceed 507 * ECC strength, or any other error code if the error is not 508 * directly related to correction. 509 * If -EBADMSG is returned the input buffers should be left 510 * untouched. 511 * @read_page_raw: function to read a raw page without ECC. This function 512 * should hide the specific layout used by the ECC 513 * controller and always return contiguous in-band and 514 * out-of-band data even if they're not stored 515 * contiguously on the NAND chip (e.g. 516 * NAND_ECC_HW_SYNDROME interleaves in-band and 517 * out-of-band data). 518 * @write_page_raw: function to write a raw page without ECC. This function 519 * should hide the specific layout used by the ECC 520 * controller and consider the passed data as contiguous 521 * in-band and out-of-band data. ECC controller is 522 * responsible for doing the appropriate transformations 523 * to adapt to its specific layout (e.g. 524 * NAND_ECC_HW_SYNDROME interleaves in-band and 525 * out-of-band data). 526 * @read_page: function to read a page according to the ECC generator 527 * requirements; returns maximum number of bitflips corrected in 528 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 529 * @read_subpage: function to read parts of the page covered by ECC; 530 * returns same as read_page() 531 * @write_subpage: function to write parts of the page covered by ECC. 532 * @write_page: function to write a page according to the ECC generator 533 * requirements. 534 * @write_oob_raw: function to write chip OOB data without ECC 535 * @read_oob_raw: function to read chip OOB data without ECC 536 * @read_oob: function to read chip OOB data 537 * @write_oob: function to write chip OOB data 538 */ 539 struct nand_ecc_ctrl { 540 nand_ecc_modes_t mode; 541 int steps; 542 int size; 543 int bytes; 544 int total; 545 int strength; 546 int prepad; 547 int postpad; 548 unsigned int options; 549 struct nand_ecclayout *layout; 550 void *priv; 551 void (*hwctl)(struct mtd_info *mtd, int mode); 552 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 553 uint8_t *ecc_code); 554 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 555 uint8_t *calc_ecc); 556 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 557 uint8_t *buf, int oob_required, int page); 558 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 559 const uint8_t *buf, int oob_required, int page); 560 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 561 uint8_t *buf, int oob_required, int page); 562 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 563 uint32_t offs, uint32_t len, uint8_t *buf, int page); 564 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 565 uint32_t offset, uint32_t data_len, 566 const uint8_t *data_buf, int oob_required, int page); 567 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 568 const uint8_t *buf, int oob_required, int page); 569 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 570 int page); 571 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 572 int page); 573 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 574 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 575 int page); 576 }; 577 578 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 579 { 580 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 581 } 582 583 /** 584 * struct nand_buffers - buffer structure for read/write 585 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 586 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 587 * @databuf: buffer pointer for data, size is (page size + oobsize). 588 * 589 * Do not change the order of buffers. databuf and oobrbuf must be in 590 * consecutive order. 591 */ 592 struct nand_buffers { 593 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 594 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 595 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 596 ARCH_DMA_MINALIGN)]; 597 }; 598 599 /** 600 * struct nand_sdr_timings - SDR NAND chip timings 601 * 602 * This struct defines the timing requirements of a SDR NAND chip. 603 * These information can be found in every NAND datasheets and the timings 604 * meaning are described in the ONFI specifications: 605 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 606 * Parameters) 607 * 608 * All these timings are expressed in picoseconds. 609 * 610 * @tBERS_max: Block erase time 611 * @tCCS_min: Change column setup time 612 * @tPROG_max: Page program time 613 * @tR_max: Page read time 614 * @tALH_min: ALE hold time 615 * @tADL_min: ALE to data loading time 616 * @tALS_min: ALE setup time 617 * @tAR_min: ALE to RE# delay 618 * @tCEA_max: CE# access time 619 * @tCEH_min: CE# high hold time 620 * @tCH_min: CE# hold time 621 * @tCHZ_max: CE# high to output hi-Z 622 * @tCLH_min: CLE hold time 623 * @tCLR_min: CLE to RE# delay 624 * @tCLS_min: CLE setup time 625 * @tCOH_min: CE# high to output hold 626 * @tCS_min: CE# setup time 627 * @tDH_min: Data hold time 628 * @tDS_min: Data setup time 629 * @tFEAT_max: Busy time for Set Features and Get Features 630 * @tIR_min: Output hi-Z to RE# low 631 * @tITC_max: Interface and Timing Mode Change time 632 * @tRC_min: RE# cycle time 633 * @tREA_max: RE# access time 634 * @tREH_min: RE# high hold time 635 * @tRHOH_min: RE# high to output hold 636 * @tRHW_min: RE# high to WE# low 637 * @tRHZ_max: RE# high to output hi-Z 638 * @tRLOH_min: RE# low to output hold 639 * @tRP_min: RE# pulse width 640 * @tRR_min: Ready to RE# low (data only) 641 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 642 * rising edge of R/B#. 643 * @tWB_max: WE# high to SR[6] low 644 * @tWC_min: WE# cycle time 645 * @tWH_min: WE# high hold time 646 * @tWHR_min: WE# high to RE# low 647 * @tWP_min: WE# pulse width 648 * @tWW_min: WP# transition to WE# low 649 */ 650 struct nand_sdr_timings { 651 u64 tBERS_max; 652 u32 tCCS_min; 653 u64 tPROG_max; 654 u64 tR_max; 655 u32 tALH_min; 656 u32 tADL_min; 657 u32 tALS_min; 658 u32 tAR_min; 659 u32 tCEA_max; 660 u32 tCEH_min; 661 u32 tCH_min; 662 u32 tCHZ_max; 663 u32 tCLH_min; 664 u32 tCLR_min; 665 u32 tCLS_min; 666 u32 tCOH_min; 667 u32 tCS_min; 668 u32 tDH_min; 669 u32 tDS_min; 670 u32 tFEAT_max; 671 u32 tIR_min; 672 u32 tITC_max; 673 u32 tRC_min; 674 u32 tREA_max; 675 u32 tREH_min; 676 u32 tRHOH_min; 677 u32 tRHW_min; 678 u32 tRHZ_max; 679 u32 tRLOH_min; 680 u32 tRP_min; 681 u32 tRR_min; 682 u64 tRST_max; 683 u32 tWB_max; 684 u32 tWC_min; 685 u32 tWH_min; 686 u32 tWHR_min; 687 u32 tWP_min; 688 u32 tWW_min; 689 }; 690 691 /** 692 * enum nand_data_interface_type - NAND interface timing type 693 * @NAND_SDR_IFACE: Single Data Rate interface 694 */ 695 enum nand_data_interface_type { 696 NAND_SDR_IFACE, 697 }; 698 699 /** 700 * struct nand_data_interface - NAND interface timing 701 * @type: type of the timing 702 * @timings: The timing, type according to @type 703 */ 704 struct nand_data_interface { 705 enum nand_data_interface_type type; 706 union { 707 struct nand_sdr_timings sdr; 708 } timings; 709 }; 710 711 /** 712 * nand_get_sdr_timings - get SDR timing from data interface 713 * @conf: The data interface 714 */ 715 static inline const struct nand_sdr_timings * 716 nand_get_sdr_timings(const struct nand_data_interface *conf) 717 { 718 if (conf->type != NAND_SDR_IFACE) 719 return ERR_PTR(-EINVAL); 720 721 return &conf->timings.sdr; 722 } 723 724 /** 725 * struct nand_chip - NAND Private Flash Chip Data 726 * @mtd: MTD device registered to the MTD framework 727 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 728 * flash device 729 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 730 * flash device. 731 * @flash_node: [BOARDSPECIFIC] device node describing this instance 732 * @read_byte: [REPLACEABLE] read one byte from the chip 733 * @read_word: [REPLACEABLE] read one word from the chip 734 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 735 * low 8 I/O lines 736 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 737 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 738 * @select_chip: [REPLACEABLE] select chip nr 739 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 740 * @block_markbad: [REPLACEABLE] mark a block bad 741 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 742 * ALE/CLE/nCE. Also used to write command and address 743 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 744 * device ready/busy line. If set to NULL no access to 745 * ready/busy is available and the ready/busy information 746 * is read from the chip status register. 747 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 748 * commands to the chip. 749 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 750 * ready. 751 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 752 * setting the read-retry mode. Mostly needed for MLC NAND. 753 * @ecc: [BOARDSPECIFIC] ECC control structure 754 * @buffers: buffer structure for read/write 755 * @hwcontrol: platform-specific hardware control structure 756 * @erase: [REPLACEABLE] erase function 757 * @scan_bbt: [REPLACEABLE] function to scan bad block table 758 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 759 * data from array to read regs (tR). 760 * @state: [INTERN] the current state of the NAND device 761 * @oob_poi: "poison value buffer," used for laying out OOB data 762 * before writing 763 * @page_shift: [INTERN] number of address bits in a page (column 764 * address bits). 765 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 766 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 767 * @chip_shift: [INTERN] number of address bits in one chip 768 * @options: [BOARDSPECIFIC] various chip options. They can partly 769 * be set to inform nand_scan about special functionality. 770 * See the defines for further explanation. 771 * @bbt_options: [INTERN] bad block specific options. All options used 772 * here must come from bbm.h. By default, these options 773 * will be copied to the appropriate nand_bbt_descr's. 774 * @badblockpos: [INTERN] position of the bad block marker in the oob 775 * area. 776 * @badblockbits: [INTERN] minimum number of set bits in a good block's 777 * bad block marker position; i.e., BBM == 11110111b is 778 * not bad when badblockbits == 7 779 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 780 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 781 * Minimum amount of bit errors per @ecc_step_ds guaranteed 782 * to be correctable. If unknown, set to zero. 783 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 784 * also from the datasheet. It is the recommended ECC step 785 * size, if known; if unknown, set to zero. 786 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 787 * set to the actually used ONFI mode if the chip is 788 * ONFI compliant or deduced from the datasheet if 789 * the NAND chip is not ONFI compliant. 790 * @numchips: [INTERN] number of physical chips 791 * @chipsize: [INTERN] the size of one chip for multichip arrays 792 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 793 * @pagebuf: [INTERN] holds the pagenumber which is currently in 794 * data_buf. 795 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 796 * currently in data_buf. 797 * @subpagesize: [INTERN] holds the subpagesize 798 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 799 * non 0 if ONFI supported. 800 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 801 * non 0 if JEDEC supported. 802 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 803 * supported, 0 otherwise. 804 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 805 * supported, 0 otherwise. 806 * @read_retries: [INTERN] the number of read retry modes supported 807 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 808 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 809 * @setup_data_interface: [OPTIONAL] setup the data interface and timing 810 * @bbt: [INTERN] bad block table pointer 811 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 812 * lookup. 813 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 814 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 815 * bad block scan. 816 * @controller: [REPLACEABLE] a pointer to a hardware controller 817 * structure which is shared among multiple independent 818 * devices. 819 * @priv: [OPTIONAL] pointer to private chip data 820 * @errstat: [OPTIONAL] hardware specific function to perform 821 * additional error status checks (determine if errors are 822 * correctable). 823 * @write_page: [REPLACEABLE] High-level page write function 824 */ 825 826 struct nand_chip { 827 struct mtd_info mtd; 828 void __iomem *IO_ADDR_R; 829 void __iomem *IO_ADDR_W; 830 831 int flash_node; 832 833 uint8_t (*read_byte)(struct mtd_info *mtd); 834 u16 (*read_word)(struct mtd_info *mtd); 835 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 836 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 837 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 838 void (*select_chip)(struct mtd_info *mtd, int chip); 839 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 840 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 841 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 842 int (*dev_ready)(struct mtd_info *mtd); 843 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 844 int page_addr); 845 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 846 int (*erase)(struct mtd_info *mtd, int page); 847 int (*scan_bbt)(struct mtd_info *mtd); 848 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 849 int status, int page); 850 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 851 uint32_t offset, int data_len, const uint8_t *buf, 852 int oob_required, int page, int raw); 853 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 854 int feature_addr, uint8_t *subfeature_para); 855 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 856 int feature_addr, uint8_t *subfeature_para); 857 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 858 int (*setup_data_interface)(struct mtd_info *mtd, 859 const struct nand_data_interface *conf, 860 bool check_only); 861 862 863 int chip_delay; 864 unsigned int options; 865 unsigned int bbt_options; 866 867 int page_shift; 868 int phys_erase_shift; 869 int bbt_erase_shift; 870 int chip_shift; 871 int numchips; 872 uint64_t chipsize; 873 int pagemask; 874 int pagebuf; 875 unsigned int pagebuf_bitflips; 876 int subpagesize; 877 uint8_t bits_per_cell; 878 uint16_t ecc_strength_ds; 879 uint16_t ecc_step_ds; 880 int onfi_timing_mode_default; 881 int badblockpos; 882 int badblockbits; 883 884 int onfi_version; 885 int jedec_version; 886 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 887 struct nand_onfi_params onfi_params; 888 #endif 889 struct nand_jedec_params jedec_params; 890 891 struct nand_data_interface *data_interface; 892 893 int read_retries; 894 895 flstate_t state; 896 897 uint8_t *oob_poi; 898 struct nand_hw_control *controller; 899 struct nand_ecclayout *ecclayout; 900 901 struct nand_ecc_ctrl ecc; 902 struct nand_buffers *buffers; 903 struct nand_hw_control hwcontrol; 904 905 uint8_t *bbt; 906 struct nand_bbt_descr *bbt_td; 907 struct nand_bbt_descr *bbt_md; 908 909 struct nand_bbt_descr *badblock_pattern; 910 911 void *priv; 912 }; 913 914 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 915 { 916 return container_of(mtd, struct nand_chip, mtd); 917 } 918 919 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 920 { 921 return &chip->mtd; 922 } 923 924 static inline void *nand_get_controller_data(struct nand_chip *chip) 925 { 926 return chip->priv; 927 } 928 929 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 930 { 931 chip->priv = priv; 932 } 933 934 /* 935 * NAND Flash Manufacturer ID Codes 936 */ 937 #define NAND_MFR_TOSHIBA 0x98 938 #define NAND_MFR_SAMSUNG 0xec 939 #define NAND_MFR_FUJITSU 0x04 940 #define NAND_MFR_NATIONAL 0x8f 941 #define NAND_MFR_RENESAS 0x07 942 #define NAND_MFR_STMICRO 0x20 943 #define NAND_MFR_HYNIX 0xad 944 #define NAND_MFR_MICRON 0x2c 945 #define NAND_MFR_AMD 0x01 946 #define NAND_MFR_MACRONIX 0xc2 947 #define NAND_MFR_EON 0x92 948 #define NAND_MFR_SANDISK 0x45 949 #define NAND_MFR_INTEL 0x89 950 #define NAND_MFR_ATO 0x9b 951 952 /* The maximum expected count of bytes in the NAND ID sequence */ 953 #define NAND_MAX_ID_LEN 8 954 955 /* 956 * A helper for defining older NAND chips where the second ID byte fully 957 * defined the chip, including the geometry (chip size, eraseblock size, page 958 * size). All these chips have 512 bytes NAND page size. 959 */ 960 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 961 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 962 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 963 964 /* 965 * A helper for defining newer chips which report their page size and 966 * eraseblock size via the extended ID bytes. 967 * 968 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 969 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 970 * device ID now only represented a particular total chip size (and voltage, 971 * buswidth), and the page size, eraseblock size, and OOB size could vary while 972 * using the same device ID. 973 */ 974 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 975 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 976 .options = (opts) } 977 978 #define NAND_ECC_INFO(_strength, _step) \ 979 { .strength_ds = (_strength), .step_ds = (_step) } 980 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 981 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 982 983 /** 984 * struct nand_flash_dev - NAND Flash Device ID Structure 985 * @name: a human-readable name of the NAND chip 986 * @dev_id: the device ID (the second byte of the full chip ID array) 987 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 988 * memory address as @id[0]) 989 * @dev_id: device ID part of the full chip ID array (refers the same memory 990 * address as @id[1]) 991 * @id: full device ID array 992 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 993 * well as the eraseblock size) is determined from the extended NAND 994 * chip ID array) 995 * @chipsize: total chip size in MiB 996 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 997 * @options: stores various chip bit options 998 * @id_len: The valid length of the @id. 999 * @oobsize: OOB size 1000 * @ecc: ECC correctability and step information from the datasheet. 1001 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1002 * @ecc_strength_ds in nand_chip{}. 1003 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1004 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1005 * For example, the "4bit ECC for each 512Byte" can be set with 1006 * NAND_ECC_INFO(4, 512). 1007 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1008 * reset. Should be deduced from timings described 1009 * in the datasheet. 1010 * 1011 */ 1012 struct nand_flash_dev { 1013 char *name; 1014 union { 1015 struct { 1016 uint8_t mfr_id; 1017 uint8_t dev_id; 1018 }; 1019 uint8_t id[NAND_MAX_ID_LEN]; 1020 }; 1021 unsigned int pagesize; 1022 unsigned int chipsize; 1023 unsigned int erasesize; 1024 unsigned int options; 1025 uint16_t id_len; 1026 uint16_t oobsize; 1027 struct { 1028 uint16_t strength_ds; 1029 uint16_t step_ds; 1030 } ecc; 1031 int onfi_timing_mode_default; 1032 }; 1033 1034 /** 1035 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1036 * @name: Manufacturer name 1037 * @id: manufacturer ID code of device. 1038 */ 1039 struct nand_manufacturers { 1040 int id; 1041 char *name; 1042 }; 1043 1044 extern struct nand_flash_dev nand_flash_ids[]; 1045 extern struct nand_manufacturers nand_manuf_ids[]; 1046 1047 extern int nand_default_bbt(struct mtd_info *mtd); 1048 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1049 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1050 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1051 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1052 int allowbbt); 1053 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1054 size_t *retlen, uint8_t *buf); 1055 1056 /* 1057 * Constants for oob configuration 1058 */ 1059 #define NAND_SMALL_BADBLOCK_POS 5 1060 #define NAND_LARGE_BADBLOCK_POS 0 1061 1062 /** 1063 * struct platform_nand_chip - chip level device structure 1064 * @nr_chips: max. number of chips to scan for 1065 * @chip_offset: chip number offset 1066 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1067 * @partitions: mtd partition list 1068 * @chip_delay: R/B delay value in us 1069 * @options: Option flags, e.g. 16bit buswidth 1070 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1071 * @part_probe_types: NULL-terminated array of probe types 1072 */ 1073 struct platform_nand_chip { 1074 int nr_chips; 1075 int chip_offset; 1076 int nr_partitions; 1077 struct mtd_partition *partitions; 1078 int chip_delay; 1079 unsigned int options; 1080 unsigned int bbt_options; 1081 const char **part_probe_types; 1082 }; 1083 1084 /* Keep gcc happy */ 1085 struct platform_device; 1086 1087 /** 1088 * struct platform_nand_ctrl - controller level device structure 1089 * @probe: platform specific function to probe/setup hardware 1090 * @remove: platform specific function to remove/teardown hardware 1091 * @hwcontrol: platform specific hardware control structure 1092 * @dev_ready: platform specific function to read ready/busy pin 1093 * @select_chip: platform specific chip select function 1094 * @cmd_ctrl: platform specific function for controlling 1095 * ALE/CLE/nCE. Also used to write command and address 1096 * @write_buf: platform specific function for write buffer 1097 * @read_buf: platform specific function for read buffer 1098 * @read_byte: platform specific function to read one byte from chip 1099 * @priv: private data to transport driver specific settings 1100 * 1101 * All fields are optional and depend on the hardware driver requirements 1102 */ 1103 struct platform_nand_ctrl { 1104 int (*probe)(struct platform_device *pdev); 1105 void (*remove)(struct platform_device *pdev); 1106 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1107 int (*dev_ready)(struct mtd_info *mtd); 1108 void (*select_chip)(struct mtd_info *mtd, int chip); 1109 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1110 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1111 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1112 unsigned char (*read_byte)(struct mtd_info *mtd); 1113 void *priv; 1114 }; 1115 1116 /** 1117 * struct platform_nand_data - container structure for platform-specific data 1118 * @chip: chip level chip structure 1119 * @ctrl: controller level device structure 1120 */ 1121 struct platform_nand_data { 1122 struct platform_nand_chip chip; 1123 struct platform_nand_ctrl ctrl; 1124 }; 1125 1126 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1127 /* return the supported features. */ 1128 static inline int onfi_feature(struct nand_chip *chip) 1129 { 1130 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1131 } 1132 1133 /* return the supported asynchronous timing mode. */ 1134 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1135 { 1136 if (!chip->onfi_version) 1137 return ONFI_TIMING_MODE_UNKNOWN; 1138 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1139 } 1140 1141 /* return the supported synchronous timing mode. */ 1142 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1143 { 1144 if (!chip->onfi_version) 1145 return ONFI_TIMING_MODE_UNKNOWN; 1146 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1147 } 1148 #endif 1149 1150 int onfi_init_data_interface(struct nand_chip *chip, 1151 struct nand_data_interface *iface, 1152 enum nand_data_interface_type type, 1153 int timing_mode); 1154 1155 /* 1156 * Check if it is a SLC nand. 1157 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1158 * We do not distinguish the MLC and TLC now. 1159 */ 1160 static inline bool nand_is_slc(struct nand_chip *chip) 1161 { 1162 return chip->bits_per_cell == 1; 1163 } 1164 1165 /** 1166 * Check if the opcode's address should be sent only on the lower 8 bits 1167 * @command: opcode to check 1168 */ 1169 static inline int nand_opcode_8bits(unsigned int command) 1170 { 1171 switch (command) { 1172 case NAND_CMD_READID: 1173 case NAND_CMD_PARAM: 1174 case NAND_CMD_GET_FEATURES: 1175 case NAND_CMD_SET_FEATURES: 1176 return 1; 1177 default: 1178 break; 1179 } 1180 return 0; 1181 } 1182 1183 /* return the supported JEDEC features. */ 1184 static inline int jedec_feature(struct nand_chip *chip) 1185 { 1186 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1187 : 0; 1188 } 1189 1190 /* Standard NAND functions from nand_base.c */ 1191 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1192 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1193 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1194 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1195 uint8_t nand_read_byte(struct mtd_info *mtd); 1196 1197 /* get timing characteristics from ONFI timing mode. */ 1198 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1199 /* get data interface from ONFI timing mode 0, used after reset. */ 1200 const struct nand_data_interface *nand_get_default_data_interface(void); 1201 1202 int nand_check_erased_ecc_chunk(void *data, int datalen, 1203 void *ecc, int ecclen, 1204 void *extraoob, int extraooblen, 1205 int threshold); 1206 1207 /* Reset and initialize a NAND device */ 1208 int nand_reset(struct nand_chip *chip, int chipnr); 1209 1210 #endif /* __LINUX_MTD_NAND_H */ 1211