1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #include <config.h> 20 21 #include <linux/compat.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 extern int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 extern int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Free resources held by the NAND device */ 41 extern void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 extern void nand_wait_ready(struct mtd_info *mtd); 45 46 /* 47 * This constant declares the max. oobsize / page, which 48 * is supported now. If you add a chip with bigger oobsize/page 49 * adjust this accordingly. 50 */ 51 #define NAND_MAX_OOBSIZE 1664 52 #define NAND_MAX_PAGESIZE 16384 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 /* Extended commands for AG-AND device */ 100 /* 101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 102 * there is no way to distinguish that from NAND_CMD_READ0 103 * until the remaining sequence of commands has been completed 104 * so add a high order bit and mask it off in the command. 105 */ 106 #define NAND_CMD_DEPLETE1 0x100 107 #define NAND_CMD_DEPLETE2 0x38 108 #define NAND_CMD_STATUS_MULTI 0x71 109 #define NAND_CMD_STATUS_ERROR 0x72 110 /* multi-bank error status (banks 0-3) */ 111 #define NAND_CMD_STATUS_ERROR0 0x73 112 #define NAND_CMD_STATUS_ERROR1 0x74 113 #define NAND_CMD_STATUS_ERROR2 0x75 114 #define NAND_CMD_STATUS_ERROR3 0x76 115 #define NAND_CMD_STATUS_RESET 0x7f 116 #define NAND_CMD_STATUS_CLEAR 0xff 117 118 #define NAND_CMD_NONE -1 119 120 /* Status bits */ 121 #define NAND_STATUS_FAIL 0x01 122 #define NAND_STATUS_FAIL_N1 0x02 123 #define NAND_STATUS_TRUE_READY 0x20 124 #define NAND_STATUS_READY 0x40 125 #define NAND_STATUS_WP 0x80 126 127 /* 128 * Constants for ECC_MODES 129 */ 130 typedef enum { 131 NAND_ECC_NONE, 132 NAND_ECC_SOFT, 133 NAND_ECC_HW, 134 NAND_ECC_HW_SYNDROME, 135 NAND_ECC_HW_OOB_FIRST, 136 NAND_ECC_SOFT_BCH, 137 } nand_ecc_modes_t; 138 139 /* 140 * Constants for Hardware ECC 141 */ 142 /* Reset Hardware ECC for read */ 143 #define NAND_ECC_READ 0 144 /* Reset Hardware ECC for write */ 145 #define NAND_ECC_WRITE 1 146 /* Enable Hardware ECC before syndrome is read back from flash */ 147 #define NAND_ECC_READSYN 2 148 149 /* 150 * Enable generic NAND 'page erased' check. This check is only done when 151 * ecc.correct() returns -EBADMSG. 152 * Set this flag if your implementation does not fix bitflips in erased 153 * pages and you want to rely on the default implementation. 154 */ 155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 156 #define NAND_ECC_MAXIMIZE BIT(1) 157 158 /* Bit mask for flags passed to do_nand_read_ecc */ 159 #define NAND_GET_DEVICE 0x80 160 161 162 /* 163 * Option constants for bizarre disfunctionality and real 164 * features. 165 */ 166 /* Buswidth is 16 bit */ 167 #define NAND_BUSWIDTH_16 0x00000002 168 /* Device supports partial programming without padding */ 169 #define NAND_NO_PADDING 0x00000004 170 /* Chip has cache program function */ 171 #define NAND_CACHEPRG 0x00000008 172 /* Chip has copy back function */ 173 #define NAND_COPYBACK 0x00000010 174 /* 175 * Chip requires ready check on read (for auto-incremented sequential read). 176 * True only for small page devices; large page devices do not support 177 * autoincrement. 178 */ 179 #define NAND_NEED_READRDY 0x00000100 180 181 /* Chip does not allow subpage writes */ 182 #define NAND_NO_SUBPAGE_WRITE 0x00000200 183 184 /* Device is one of 'new' xD cards that expose fake nand command set */ 185 #define NAND_BROKEN_XD 0x00000400 186 187 /* Device behaves just like nand, but is readonly */ 188 #define NAND_ROM 0x00000800 189 190 /* Device supports subpage reads */ 191 #define NAND_SUBPAGE_READ 0x00001000 192 193 /* 194 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 195 * patterns. 196 */ 197 #define NAND_NEED_SCRAMBLING 0x00002000 198 199 /* Options valid for Samsung large page devices */ 200 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 201 202 /* Macros to identify the above */ 203 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 204 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 205 206 /* Non chip related options */ 207 /* This option skips the bbt scan during initialization. */ 208 #define NAND_SKIP_BBTSCAN 0x00010000 209 /* 210 * This option is defined if the board driver allocates its own buffers 211 * (e.g. because it needs them DMA-coherent). 212 */ 213 #define NAND_OWN_BUFFERS 0x00020000 214 /* Chip may not exist, so silence any errors in scan */ 215 #define NAND_SCAN_SILENT_NODEV 0x00040000 216 /* 217 * Autodetect nand buswidth with readid/onfi. 218 * This suppose the driver will configure the hardware in 8 bits mode 219 * when calling nand_scan_ident, and update its configuration 220 * before calling nand_scan_tail. 221 */ 222 #define NAND_BUSWIDTH_AUTO 0x00080000 223 /* 224 * This option could be defined by controller drivers to protect against 225 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 226 */ 227 #define NAND_USE_BOUNCE_BUFFER 0x00100000 228 229 /* Options set by nand scan */ 230 /* bbt has already been read */ 231 #define NAND_BBT_SCANNED 0x40000000 232 /* Nand scan has allocated controller struct */ 233 #define NAND_CONTROLLER_ALLOC 0x80000000 234 235 /* Cell info constants */ 236 #define NAND_CI_CHIPNR_MSK 0x03 237 #define NAND_CI_CELLTYPE_MSK 0x0C 238 #define NAND_CI_CELLTYPE_SHIFT 2 239 240 /* Keep gcc happy */ 241 struct nand_chip; 242 243 /* ONFI features */ 244 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 245 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 246 247 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 248 #define ONFI_TIMING_MODE_0 (1 << 0) 249 #define ONFI_TIMING_MODE_1 (1 << 1) 250 #define ONFI_TIMING_MODE_2 (1 << 2) 251 #define ONFI_TIMING_MODE_3 (1 << 3) 252 #define ONFI_TIMING_MODE_4 (1 << 4) 253 #define ONFI_TIMING_MODE_5 (1 << 5) 254 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 255 256 /* ONFI feature address */ 257 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 258 259 /* Vendor-specific feature address (Micron) */ 260 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 261 262 /* ONFI subfeature parameters length */ 263 #define ONFI_SUBFEATURE_PARAM_LEN 4 264 265 /* ONFI optional commands SET/GET FEATURES supported? */ 266 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 267 268 struct nand_onfi_params { 269 /* rev info and features block */ 270 /* 'O' 'N' 'F' 'I' */ 271 u8 sig[4]; 272 __le16 revision; 273 __le16 features; 274 __le16 opt_cmd; 275 u8 reserved0[2]; 276 __le16 ext_param_page_length; /* since ONFI 2.1 */ 277 u8 num_of_param_pages; /* since ONFI 2.1 */ 278 u8 reserved1[17]; 279 280 /* manufacturer information block */ 281 char manufacturer[12]; 282 char model[20]; 283 u8 jedec_id; 284 __le16 date_code; 285 u8 reserved2[13]; 286 287 /* memory organization block */ 288 __le32 byte_per_page; 289 __le16 spare_bytes_per_page; 290 __le32 data_bytes_per_ppage; 291 __le16 spare_bytes_per_ppage; 292 __le32 pages_per_block; 293 __le32 blocks_per_lun; 294 u8 lun_count; 295 u8 addr_cycles; 296 u8 bits_per_cell; 297 __le16 bb_per_lun; 298 __le16 block_endurance; 299 u8 guaranteed_good_blocks; 300 __le16 guaranteed_block_endurance; 301 u8 programs_per_page; 302 u8 ppage_attr; 303 u8 ecc_bits; 304 u8 interleaved_bits; 305 u8 interleaved_ops; 306 u8 reserved3[13]; 307 308 /* electrical parameter block */ 309 u8 io_pin_capacitance_max; 310 __le16 async_timing_mode; 311 __le16 program_cache_timing_mode; 312 __le16 t_prog; 313 __le16 t_bers; 314 __le16 t_r; 315 __le16 t_ccs; 316 __le16 src_sync_timing_mode; 317 u8 src_ssync_features; 318 __le16 clk_pin_capacitance_typ; 319 __le16 io_pin_capacitance_typ; 320 __le16 input_pin_capacitance_typ; 321 u8 input_pin_capacitance_max; 322 u8 driver_strength_support; 323 __le16 t_int_r; 324 __le16 t_adl; 325 u8 reserved4[8]; 326 327 /* vendor */ 328 __le16 vendor_revision; 329 u8 vendor[88]; 330 331 __le16 crc; 332 } __packed; 333 334 #define ONFI_CRC_BASE 0x4F4E 335 336 /* Extended ECC information Block Definition (since ONFI 2.1) */ 337 struct onfi_ext_ecc_info { 338 u8 ecc_bits; 339 u8 codeword_size; 340 __le16 bb_per_lun; 341 __le16 block_endurance; 342 u8 reserved[2]; 343 } __packed; 344 345 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 346 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 347 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 348 struct onfi_ext_section { 349 u8 type; 350 u8 length; 351 } __packed; 352 353 #define ONFI_EXT_SECTION_MAX 8 354 355 /* Extended Parameter Page Definition (since ONFI 2.1) */ 356 struct onfi_ext_param_page { 357 __le16 crc; 358 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 359 u8 reserved0[10]; 360 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 361 362 /* 363 * The actual size of the Extended Parameter Page is in 364 * @ext_param_page_length of nand_onfi_params{}. 365 * The following are the variable length sections. 366 * So we do not add any fields below. Please see the ONFI spec. 367 */ 368 } __packed; 369 370 struct nand_onfi_vendor_micron { 371 u8 two_plane_read; 372 u8 read_cache; 373 u8 read_unique_id; 374 u8 dq_imped; 375 u8 dq_imped_num_settings; 376 u8 dq_imped_feat_addr; 377 u8 rb_pulldown_strength; 378 u8 rb_pulldown_strength_feat_addr; 379 u8 rb_pulldown_strength_num_settings; 380 u8 otp_mode; 381 u8 otp_page_start; 382 u8 otp_data_prot_addr; 383 u8 otp_num_pages; 384 u8 otp_feat_addr; 385 u8 read_retry_options; 386 u8 reserved[72]; 387 u8 param_revision; 388 } __packed; 389 390 struct jedec_ecc_info { 391 u8 ecc_bits; 392 u8 codeword_size; 393 __le16 bb_per_lun; 394 __le16 block_endurance; 395 u8 reserved[2]; 396 } __packed; 397 398 /* JEDEC features */ 399 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 400 401 struct nand_jedec_params { 402 /* rev info and features block */ 403 /* 'J' 'E' 'S' 'D' */ 404 u8 sig[4]; 405 __le16 revision; 406 __le16 features; 407 u8 opt_cmd[3]; 408 __le16 sec_cmd; 409 u8 num_of_param_pages; 410 u8 reserved0[18]; 411 412 /* manufacturer information block */ 413 char manufacturer[12]; 414 char model[20]; 415 u8 jedec_id[6]; 416 u8 reserved1[10]; 417 418 /* memory organization block */ 419 __le32 byte_per_page; 420 __le16 spare_bytes_per_page; 421 u8 reserved2[6]; 422 __le32 pages_per_block; 423 __le32 blocks_per_lun; 424 u8 lun_count; 425 u8 addr_cycles; 426 u8 bits_per_cell; 427 u8 programs_per_page; 428 u8 multi_plane_addr; 429 u8 multi_plane_op_attr; 430 u8 reserved3[38]; 431 432 /* electrical parameter block */ 433 __le16 async_sdr_speed_grade; 434 __le16 toggle_ddr_speed_grade; 435 __le16 sync_ddr_speed_grade; 436 u8 async_sdr_features; 437 u8 toggle_ddr_features; 438 u8 sync_ddr_features; 439 __le16 t_prog; 440 __le16 t_bers; 441 __le16 t_r; 442 __le16 t_r_multi_plane; 443 __le16 t_ccs; 444 __le16 io_pin_capacitance_typ; 445 __le16 input_pin_capacitance_typ; 446 __le16 clk_pin_capacitance_typ; 447 u8 driver_strength_support; 448 __le16 t_adl; 449 u8 reserved4[36]; 450 451 /* ECC and endurance block */ 452 u8 guaranteed_good_blocks; 453 __le16 guaranteed_block_endurance; 454 struct jedec_ecc_info ecc_info[4]; 455 u8 reserved5[29]; 456 457 /* reserved */ 458 u8 reserved6[148]; 459 460 /* vendor */ 461 __le16 vendor_rev_num; 462 u8 reserved7[88]; 463 464 /* CRC for Parameter Page */ 465 __le16 crc; 466 } __packed; 467 468 /** 469 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 470 * @lock: protection lock 471 * @active: the mtd device which holds the controller currently 472 * @wq: wait queue to sleep on if a NAND operation is in 473 * progress used instead of the per chip wait queue 474 * when a hw controller is available. 475 */ 476 struct nand_hw_control { 477 spinlock_t lock; 478 struct nand_chip *active; 479 }; 480 481 /** 482 * struct nand_ecc_ctrl - Control structure for ECC 483 * @mode: ECC mode 484 * @steps: number of ECC steps per page 485 * @size: data bytes per ECC step 486 * @bytes: ECC bytes per step 487 * @strength: max number of correctible bits per ECC step 488 * @total: total number of ECC bytes per page 489 * @prepad: padding information for syndrome based ECC generators 490 * @postpad: padding information for syndrome based ECC generators 491 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 492 * @layout: ECC layout control struct pointer 493 * @priv: pointer to private ECC control data 494 * @hwctl: function to control hardware ECC generator. Must only 495 * be provided if an hardware ECC is available 496 * @calculate: function for ECC calculation or readback from ECC hardware 497 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 498 * Should return a positive number representing the number of 499 * corrected bitflips, -EBADMSG if the number of bitflips exceed 500 * ECC strength, or any other error code if the error is not 501 * directly related to correction. 502 * If -EBADMSG is returned the input buffers should be left 503 * untouched. 504 * @read_page_raw: function to read a raw page without ECC. This function 505 * should hide the specific layout used by the ECC 506 * controller and always return contiguous in-band and 507 * out-of-band data even if they're not stored 508 * contiguously on the NAND chip (e.g. 509 * NAND_ECC_HW_SYNDROME interleaves in-band and 510 * out-of-band data). 511 * @write_page_raw: function to write a raw page without ECC. This function 512 * should hide the specific layout used by the ECC 513 * controller and consider the passed data as contiguous 514 * in-band and out-of-band data. ECC controller is 515 * responsible for doing the appropriate transformations 516 * to adapt to its specific layout (e.g. 517 * NAND_ECC_HW_SYNDROME interleaves in-band and 518 * out-of-band data). 519 * @read_page: function to read a page according to the ECC generator 520 * requirements; returns maximum number of bitflips corrected in 521 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 522 * @read_subpage: function to read parts of the page covered by ECC; 523 * returns same as read_page() 524 * @write_subpage: function to write parts of the page covered by ECC. 525 * @write_page: function to write a page according to the ECC generator 526 * requirements. 527 * @write_oob_raw: function to write chip OOB data without ECC 528 * @read_oob_raw: function to read chip OOB data without ECC 529 * @read_oob: function to read chip OOB data 530 * @write_oob: function to write chip OOB data 531 */ 532 struct nand_ecc_ctrl { 533 nand_ecc_modes_t mode; 534 int steps; 535 int size; 536 int bytes; 537 int total; 538 int strength; 539 int prepad; 540 int postpad; 541 unsigned int options; 542 struct nand_ecclayout *layout; 543 void *priv; 544 void (*hwctl)(struct mtd_info *mtd, int mode); 545 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 546 uint8_t *ecc_code); 547 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 548 uint8_t *calc_ecc); 549 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 550 uint8_t *buf, int oob_required, int page); 551 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 552 const uint8_t *buf, int oob_required, int page); 553 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 554 uint8_t *buf, int oob_required, int page); 555 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 556 uint32_t offs, uint32_t len, uint8_t *buf, int page); 557 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 558 uint32_t offset, uint32_t data_len, 559 const uint8_t *data_buf, int oob_required, int page); 560 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 561 const uint8_t *buf, int oob_required, int page); 562 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 563 int page); 564 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 565 int page); 566 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 567 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 568 int page); 569 }; 570 571 /** 572 * struct nand_buffers - buffer structure for read/write 573 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 574 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 575 * @databuf: buffer pointer for data, size is (page size + oobsize). 576 * 577 * Do not change the order of buffers. databuf and oobrbuf must be in 578 * consecutive order. 579 */ 580 struct nand_buffers { 581 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 582 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 583 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 584 ARCH_DMA_MINALIGN)]; 585 }; 586 587 /** 588 * struct nand_sdr_timings - SDR NAND chip timings 589 * 590 * This struct defines the timing requirements of a SDR NAND chip. 591 * These information can be found in every NAND datasheets and the timings 592 * meaning are described in the ONFI specifications: 593 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 594 * Parameters) 595 * 596 * All these timings are expressed in picoseconds. 597 * 598 * @tALH_min: ALE hold time 599 * @tADL_min: ALE to data loading time 600 * @tALS_min: ALE setup time 601 * @tAR_min: ALE to RE# delay 602 * @tCEA_max: CE# access time 603 * @tCEH_min: CE# high hold time 604 * @tCH_min: CE# hold time 605 * @tCHZ_max: CE# high to output hi-Z 606 * @tCLH_min: CLE hold time 607 * @tCLR_min: CLE to RE# delay 608 * @tCLS_min: CLE setup time 609 * @tCOH_min: CE# high to output hold 610 * @tCS_min: CE# setup time 611 * @tDH_min: Data hold time 612 * @tDS_min: Data setup time 613 * @tFEAT_max: Busy time for Set Features and Get Features 614 * @tIR_min: Output hi-Z to RE# low 615 * @tITC_max: Interface and Timing Mode Change time 616 * @tRC_min: RE# cycle time 617 * @tREA_max: RE# access time 618 * @tREH_min: RE# high hold time 619 * @tRHOH_min: RE# high to output hold 620 * @tRHW_min: RE# high to WE# low 621 * @tRHZ_max: RE# high to output hi-Z 622 * @tRLOH_min: RE# low to output hold 623 * @tRP_min: RE# pulse width 624 * @tRR_min: Ready to RE# low (data only) 625 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 626 * rising edge of R/B#. 627 * @tWB_max: WE# high to SR[6] low 628 * @tWC_min: WE# cycle time 629 * @tWH_min: WE# high hold time 630 * @tWHR_min: WE# high to RE# low 631 * @tWP_min: WE# pulse width 632 * @tWW_min: WP# transition to WE# low 633 */ 634 struct nand_sdr_timings { 635 u32 tALH_min; 636 u32 tADL_min; 637 u32 tALS_min; 638 u32 tAR_min; 639 u32 tCEA_max; 640 u32 tCEH_min; 641 u32 tCH_min; 642 u32 tCHZ_max; 643 u32 tCLH_min; 644 u32 tCLR_min; 645 u32 tCLS_min; 646 u32 tCOH_min; 647 u32 tCS_min; 648 u32 tDH_min; 649 u32 tDS_min; 650 u32 tFEAT_max; 651 u32 tIR_min; 652 u32 tITC_max; 653 u32 tRC_min; 654 u32 tREA_max; 655 u32 tREH_min; 656 u32 tRHOH_min; 657 u32 tRHW_min; 658 u32 tRHZ_max; 659 u32 tRLOH_min; 660 u32 tRP_min; 661 u32 tRR_min; 662 u64 tRST_max; 663 u32 tWB_max; 664 u32 tWC_min; 665 u32 tWH_min; 666 u32 tWHR_min; 667 u32 tWP_min; 668 u32 tWW_min; 669 }; 670 671 /** 672 * enum nand_data_interface_type - NAND interface timing type 673 * @NAND_SDR_IFACE: Single Data Rate interface 674 */ 675 enum nand_data_interface_type { 676 NAND_SDR_IFACE, 677 }; 678 679 /** 680 * struct nand_data_interface - NAND interface timing 681 * @type: type of the timing 682 * @timings: The timing, type according to @type 683 */ 684 struct nand_data_interface { 685 enum nand_data_interface_type type; 686 union { 687 struct nand_sdr_timings sdr; 688 } timings; 689 }; 690 691 /** 692 * nand_get_sdr_timings - get SDR timing from data interface 693 * @conf: The data interface 694 */ 695 static inline const struct nand_sdr_timings * 696 nand_get_sdr_timings(const struct nand_data_interface *conf) 697 { 698 if (conf->type != NAND_SDR_IFACE) 699 return ERR_PTR(-EINVAL); 700 701 return &conf->timings.sdr; 702 } 703 704 /** 705 * struct nand_chip - NAND Private Flash Chip Data 706 * @mtd: MTD device registered to the MTD framework 707 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 708 * flash device 709 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 710 * flash device. 711 * @flash_node: [BOARDSPECIFIC] device node describing this instance 712 * @read_byte: [REPLACEABLE] read one byte from the chip 713 * @read_word: [REPLACEABLE] read one word from the chip 714 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 715 * low 8 I/O lines 716 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 717 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 718 * @select_chip: [REPLACEABLE] select chip nr 719 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 720 * @block_markbad: [REPLACEABLE] mark a block bad 721 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 722 * ALE/CLE/nCE. Also used to write command and address 723 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 724 * device ready/busy line. If set to NULL no access to 725 * ready/busy is available and the ready/busy information 726 * is read from the chip status register. 727 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 728 * commands to the chip. 729 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 730 * ready. 731 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 732 * setting the read-retry mode. Mostly needed for MLC NAND. 733 * @ecc: [BOARDSPECIFIC] ECC control structure 734 * @buffers: buffer structure for read/write 735 * @hwcontrol: platform-specific hardware control structure 736 * @erase: [REPLACEABLE] erase function 737 * @scan_bbt: [REPLACEABLE] function to scan bad block table 738 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 739 * data from array to read regs (tR). 740 * @state: [INTERN] the current state of the NAND device 741 * @oob_poi: "poison value buffer," used for laying out OOB data 742 * before writing 743 * @page_shift: [INTERN] number of address bits in a page (column 744 * address bits). 745 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 746 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 747 * @chip_shift: [INTERN] number of address bits in one chip 748 * @options: [BOARDSPECIFIC] various chip options. They can partly 749 * be set to inform nand_scan about special functionality. 750 * See the defines for further explanation. 751 * @bbt_options: [INTERN] bad block specific options. All options used 752 * here must come from bbm.h. By default, these options 753 * will be copied to the appropriate nand_bbt_descr's. 754 * @badblockpos: [INTERN] position of the bad block marker in the oob 755 * area. 756 * @badblockbits: [INTERN] minimum number of set bits in a good block's 757 * bad block marker position; i.e., BBM == 11110111b is 758 * not bad when badblockbits == 7 759 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 760 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 761 * Minimum amount of bit errors per @ecc_step_ds guaranteed 762 * to be correctable. If unknown, set to zero. 763 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 764 * also from the datasheet. It is the recommended ECC step 765 * size, if known; if unknown, set to zero. 766 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 767 * either deduced from the datasheet if the NAND 768 * chip is not ONFI compliant or set to 0 if it is 769 * (an ONFI chip is always configured in mode 0 770 * after a NAND reset) 771 * @numchips: [INTERN] number of physical chips 772 * @chipsize: [INTERN] the size of one chip for multichip arrays 773 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 774 * @pagebuf: [INTERN] holds the pagenumber which is currently in 775 * data_buf. 776 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 777 * currently in data_buf. 778 * @subpagesize: [INTERN] holds the subpagesize 779 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 780 * non 0 if ONFI supported. 781 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 782 * non 0 if JEDEC supported. 783 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 784 * supported, 0 otherwise. 785 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 786 * supported, 0 otherwise. 787 * @read_retries: [INTERN] the number of read retry modes supported 788 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 789 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 790 * @bbt: [INTERN] bad block table pointer 791 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 792 * lookup. 793 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 794 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 795 * bad block scan. 796 * @controller: [REPLACEABLE] a pointer to a hardware controller 797 * structure which is shared among multiple independent 798 * devices. 799 * @priv: [OPTIONAL] pointer to private chip data 800 * @errstat: [OPTIONAL] hardware specific function to perform 801 * additional error status checks (determine if errors are 802 * correctable). 803 * @write_page: [REPLACEABLE] High-level page write function 804 */ 805 806 struct nand_chip { 807 struct mtd_info mtd; 808 void __iomem *IO_ADDR_R; 809 void __iomem *IO_ADDR_W; 810 811 int flash_node; 812 813 uint8_t (*read_byte)(struct mtd_info *mtd); 814 u16 (*read_word)(struct mtd_info *mtd); 815 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 816 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 817 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 818 void (*select_chip)(struct mtd_info *mtd, int chip); 819 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 820 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 821 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 822 int (*dev_ready)(struct mtd_info *mtd); 823 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 824 int page_addr); 825 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 826 int (*erase)(struct mtd_info *mtd, int page); 827 int (*scan_bbt)(struct mtd_info *mtd); 828 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, 829 int status, int page); 830 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 831 uint32_t offset, int data_len, const uint8_t *buf, 832 int oob_required, int page, int cached, int raw); 833 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 834 int feature_addr, uint8_t *subfeature_para); 835 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 836 int feature_addr, uint8_t *subfeature_para); 837 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 838 839 int chip_delay; 840 unsigned int options; 841 unsigned int bbt_options; 842 843 int page_shift; 844 int phys_erase_shift; 845 int bbt_erase_shift; 846 int chip_shift; 847 int numchips; 848 uint64_t chipsize; 849 int pagemask; 850 int pagebuf; 851 unsigned int pagebuf_bitflips; 852 int subpagesize; 853 uint8_t bits_per_cell; 854 uint16_t ecc_strength_ds; 855 uint16_t ecc_step_ds; 856 int onfi_timing_mode_default; 857 int badblockpos; 858 int badblockbits; 859 860 int onfi_version; 861 int jedec_version; 862 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 863 struct nand_onfi_params onfi_params; 864 #endif 865 struct nand_jedec_params jedec_params; 866 867 int read_retries; 868 869 flstate_t state; 870 871 uint8_t *oob_poi; 872 struct nand_hw_control *controller; 873 struct nand_ecclayout *ecclayout; 874 875 struct nand_ecc_ctrl ecc; 876 struct nand_buffers *buffers; 877 struct nand_hw_control hwcontrol; 878 879 uint8_t *bbt; 880 struct nand_bbt_descr *bbt_td; 881 struct nand_bbt_descr *bbt_md; 882 883 struct nand_bbt_descr *badblock_pattern; 884 885 void *priv; 886 }; 887 888 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 889 { 890 return container_of(mtd, struct nand_chip, mtd); 891 } 892 893 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 894 { 895 return &chip->mtd; 896 } 897 898 static inline void *nand_get_controller_data(struct nand_chip *chip) 899 { 900 return chip->priv; 901 } 902 903 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 904 { 905 chip->priv = priv; 906 } 907 908 /* 909 * NAND Flash Manufacturer ID Codes 910 */ 911 #define NAND_MFR_TOSHIBA 0x98 912 #define NAND_MFR_SAMSUNG 0xec 913 #define NAND_MFR_FUJITSU 0x04 914 #define NAND_MFR_NATIONAL 0x8f 915 #define NAND_MFR_RENESAS 0x07 916 #define NAND_MFR_STMICRO 0x20 917 #define NAND_MFR_HYNIX 0xad 918 #define NAND_MFR_MICRON 0x2c 919 #define NAND_MFR_AMD 0x01 920 #define NAND_MFR_MACRONIX 0xc2 921 #define NAND_MFR_EON 0x92 922 #define NAND_MFR_SANDISK 0x45 923 #define NAND_MFR_INTEL 0x89 924 #define NAND_MFR_ATO 0x9b 925 926 /* The maximum expected count of bytes in the NAND ID sequence */ 927 #define NAND_MAX_ID_LEN 8 928 929 /* 930 * A helper for defining older NAND chips where the second ID byte fully 931 * defined the chip, including the geometry (chip size, eraseblock size, page 932 * size). All these chips have 512 bytes NAND page size. 933 */ 934 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 935 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 936 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 937 938 /* 939 * A helper for defining newer chips which report their page size and 940 * eraseblock size via the extended ID bytes. 941 * 942 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 943 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 944 * device ID now only represented a particular total chip size (and voltage, 945 * buswidth), and the page size, eraseblock size, and OOB size could vary while 946 * using the same device ID. 947 */ 948 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 949 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 950 .options = (opts) } 951 952 #define NAND_ECC_INFO(_strength, _step) \ 953 { .strength_ds = (_strength), .step_ds = (_step) } 954 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 955 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 956 957 /** 958 * struct nand_flash_dev - NAND Flash Device ID Structure 959 * @name: a human-readable name of the NAND chip 960 * @dev_id: the device ID (the second byte of the full chip ID array) 961 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 962 * memory address as @id[0]) 963 * @dev_id: device ID part of the full chip ID array (refers the same memory 964 * address as @id[1]) 965 * @id: full device ID array 966 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 967 * well as the eraseblock size) is determined from the extended NAND 968 * chip ID array) 969 * @chipsize: total chip size in MiB 970 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 971 * @options: stores various chip bit options 972 * @id_len: The valid length of the @id. 973 * @oobsize: OOB size 974 * @ecc: ECC correctability and step information from the datasheet. 975 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 976 * @ecc_strength_ds in nand_chip{}. 977 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 978 * @ecc_step_ds in nand_chip{}, also from the datasheet. 979 * For example, the "4bit ECC for each 512Byte" can be set with 980 * NAND_ECC_INFO(4, 512). 981 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 982 * reset. Should be deduced from timings described 983 * in the datasheet. 984 * 985 */ 986 struct nand_flash_dev { 987 char *name; 988 union { 989 struct { 990 uint8_t mfr_id; 991 uint8_t dev_id; 992 }; 993 uint8_t id[NAND_MAX_ID_LEN]; 994 }; 995 unsigned int pagesize; 996 unsigned int chipsize; 997 unsigned int erasesize; 998 unsigned int options; 999 uint16_t id_len; 1000 uint16_t oobsize; 1001 struct { 1002 uint16_t strength_ds; 1003 uint16_t step_ds; 1004 } ecc; 1005 int onfi_timing_mode_default; 1006 }; 1007 1008 /** 1009 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1010 * @name: Manufacturer name 1011 * @id: manufacturer ID code of device. 1012 */ 1013 struct nand_manufacturers { 1014 int id; 1015 char *name; 1016 }; 1017 1018 extern struct nand_flash_dev nand_flash_ids[]; 1019 extern struct nand_manufacturers nand_manuf_ids[]; 1020 1021 extern int nand_default_bbt(struct mtd_info *mtd); 1022 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1023 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1024 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1025 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1026 int allowbbt); 1027 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1028 size_t *retlen, uint8_t *buf); 1029 1030 /* 1031 * Constants for oob configuration 1032 */ 1033 #define NAND_SMALL_BADBLOCK_POS 5 1034 #define NAND_LARGE_BADBLOCK_POS 0 1035 1036 /** 1037 * struct platform_nand_chip - chip level device structure 1038 * @nr_chips: max. number of chips to scan for 1039 * @chip_offset: chip number offset 1040 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1041 * @partitions: mtd partition list 1042 * @chip_delay: R/B delay value in us 1043 * @options: Option flags, e.g. 16bit buswidth 1044 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1045 * @part_probe_types: NULL-terminated array of probe types 1046 */ 1047 struct platform_nand_chip { 1048 int nr_chips; 1049 int chip_offset; 1050 int nr_partitions; 1051 struct mtd_partition *partitions; 1052 int chip_delay; 1053 unsigned int options; 1054 unsigned int bbt_options; 1055 const char **part_probe_types; 1056 }; 1057 1058 /* Keep gcc happy */ 1059 struct platform_device; 1060 1061 /** 1062 * struct platform_nand_ctrl - controller level device structure 1063 * @probe: platform specific function to probe/setup hardware 1064 * @remove: platform specific function to remove/teardown hardware 1065 * @hwcontrol: platform specific hardware control structure 1066 * @dev_ready: platform specific function to read ready/busy pin 1067 * @select_chip: platform specific chip select function 1068 * @cmd_ctrl: platform specific function for controlling 1069 * ALE/CLE/nCE. Also used to write command and address 1070 * @write_buf: platform specific function for write buffer 1071 * @read_buf: platform specific function for read buffer 1072 * @read_byte: platform specific function to read one byte from chip 1073 * @priv: private data to transport driver specific settings 1074 * 1075 * All fields are optional and depend on the hardware driver requirements 1076 */ 1077 struct platform_nand_ctrl { 1078 int (*probe)(struct platform_device *pdev); 1079 void (*remove)(struct platform_device *pdev); 1080 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1081 int (*dev_ready)(struct mtd_info *mtd); 1082 void (*select_chip)(struct mtd_info *mtd, int chip); 1083 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1084 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1085 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1086 unsigned char (*read_byte)(struct mtd_info *mtd); 1087 void *priv; 1088 }; 1089 1090 /** 1091 * struct platform_nand_data - container structure for platform-specific data 1092 * @chip: chip level chip structure 1093 * @ctrl: controller level device structure 1094 */ 1095 struct platform_nand_data { 1096 struct platform_nand_chip chip; 1097 struct platform_nand_ctrl ctrl; 1098 }; 1099 1100 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1101 /* return the supported features. */ 1102 static inline int onfi_feature(struct nand_chip *chip) 1103 { 1104 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1105 } 1106 1107 /* return the supported asynchronous timing mode. */ 1108 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1109 { 1110 if (!chip->onfi_version) 1111 return ONFI_TIMING_MODE_UNKNOWN; 1112 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1113 } 1114 1115 /* return the supported synchronous timing mode. */ 1116 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1117 { 1118 if (!chip->onfi_version) 1119 return ONFI_TIMING_MODE_UNKNOWN; 1120 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1121 } 1122 #endif 1123 1124 int onfi_init_data_interface(struct nand_chip *chip, 1125 struct nand_data_interface *iface, 1126 enum nand_data_interface_type type, 1127 int timing_mode); 1128 1129 /* 1130 * Check if it is a SLC nand. 1131 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1132 * We do not distinguish the MLC and TLC now. 1133 */ 1134 static inline bool nand_is_slc(struct nand_chip *chip) 1135 { 1136 return chip->bits_per_cell == 1; 1137 } 1138 1139 /** 1140 * Check if the opcode's address should be sent only on the lower 8 bits 1141 * @command: opcode to check 1142 */ 1143 static inline int nand_opcode_8bits(unsigned int command) 1144 { 1145 switch (command) { 1146 case NAND_CMD_READID: 1147 case NAND_CMD_PARAM: 1148 case NAND_CMD_GET_FEATURES: 1149 case NAND_CMD_SET_FEATURES: 1150 return 1; 1151 default: 1152 break; 1153 } 1154 return 0; 1155 } 1156 1157 /* return the supported JEDEC features. */ 1158 static inline int jedec_feature(struct nand_chip *chip) 1159 { 1160 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1161 : 0; 1162 } 1163 1164 /* Standard NAND functions from nand_base.c */ 1165 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1166 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1167 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1168 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1169 uint8_t nand_read_byte(struct mtd_info *mtd); 1170 1171 /* get timing characteristics from ONFI timing mode. */ 1172 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1173 /* get data interface from ONFI timing mode 0, used after reset. */ 1174 const struct nand_data_interface *nand_get_default_data_interface(void); 1175 1176 int nand_check_erased_ecc_chunk(void *data, int datalen, 1177 void *ecc, int ecclen, 1178 void *extraoob, int extraooblen, 1179 int threshold); 1180 1181 /* Reset and initialize a NAND device */ 1182 int nand_reset(struct nand_chip *chip); 1183 1184 #endif /* __LINUX_MTD_NAND_H */ 1185