1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 #ifndef __DW_HDMI__ 11 #define __DW_HDMI__ 12 13 struct dw_hdmi; 14 struct drm_display_mode; 15 struct ddc_adapter; 16 struct i2c_msg; 17 18 /** 19 * DOC: Supported input formats and encodings 20 * 21 * Depending on the Hardware configuration of the Controller IP, it supports 22 * a subset of the following input formats and encodings on its internal 23 * 48bit bus. 24 * 25 * +----------------------+----------------------------------+------------------------------+ 26 * + Format Name + Format Code + Encodings + 27 * +----------------------+----------------------------------+------------------------------+ 28 * + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 29 * +----------------------+----------------------------------+------------------------------+ 30 * + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 31 * +----------------------+----------------------------------+------------------------------+ 32 * + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 33 * +----------------------+----------------------------------+------------------------------+ 34 * + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 35 * +----------------------+----------------------------------+------------------------------+ 36 * + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` + 37 * + + + or ``V4L2_YCBCR_ENC_709`` + 38 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 39 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 40 * +----------------------+----------------------------------+------------------------------+ 41 * + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` + 42 * + + + or ``V4L2_YCBCR_ENC_709`` + 43 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 44 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 45 * +----------------------+----------------------------------+------------------------------+ 46 * + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` + 47 * + + + or ``V4L2_YCBCR_ENC_709`` + 48 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 49 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 50 * +----------------------+----------------------------------+------------------------------+ 51 * + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` + 52 * + + + or ``V4L2_YCBCR_ENC_709`` + 53 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 54 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 55 * +----------------------+----------------------------------+------------------------------+ 56 * + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` + 57 * + + + or ``V4L2_YCBCR_ENC_709`` + 58 * +----------------------+----------------------------------+------------------------------+ 59 * + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` + 60 * + + + or ``V4L2_YCBCR_ENC_709`` + 61 * +----------------------+----------------------------------+------------------------------+ 62 * + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` + 63 * + + + or ``V4L2_YCBCR_ENC_709`` + 64 * +----------------------+----------------------------------+------------------------------+ 65 * + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` + 66 * + + + or ``V4L2_YCBCR_ENC_709`` + 67 * +----------------------+----------------------------------+------------------------------+ 68 * + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` + 69 * + + + or ``V4L2_YCBCR_ENC_709`` + 70 * +----------------------+----------------------------------+------------------------------+ 71 * + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` + 72 * + + + or ``V4L2_YCBCR_ENC_709`` + 73 * +----------------------+----------------------------------+------------------------------+ 74 * + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` + 75 * + + + or ``V4L2_YCBCR_ENC_709`` + 76 * +----------------------+----------------------------------+------------------------------+ 77 */ 78 79 enum { 80 DW_HDMI_RES_8, 81 DW_HDMI_RES_10, 82 DW_HDMI_RES_12, 83 DW_HDMI_RES_MAX, 84 }; 85 86 enum dw_hdmi_devtype { 87 IMX6Q_HDMI, 88 IMX6DL_HDMI, 89 RK3228_HDMI, 90 RK3288_HDMI, 91 RK3328_HDMI, 92 RK3366_HDMI, 93 RK3368_HDMI, 94 RK3399_HDMI, 95 RK3568_HDMI, 96 }; 97 98 struct dw_hdmi_audio_tmds_n { 99 unsigned long tmds; 100 unsigned int n_32k; 101 unsigned int n_44k1; 102 unsigned int n_48k; 103 }; 104 105 enum dw_hdmi_phy_type { 106 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 107 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 108 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 109 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 110 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 111 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 112 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 113 }; 114 115 struct dw_hdmi_mpll_config { 116 unsigned long mpixelclock; 117 struct { 118 u16 cpce; 119 u16 gmp; 120 } res[DW_HDMI_RES_MAX]; 121 }; 122 123 struct dw_hdmi_curr_ctrl { 124 unsigned long mpixelclock; 125 u16 curr[DW_HDMI_RES_MAX]; 126 }; 127 128 struct dw_hdmi_phy_config { 129 unsigned long mpixelclock; 130 u16 sym_ctr; /*clock symbol and transmitter control*/ 131 u16 term; /*transmission termination value*/ 132 u16 vlev_ctr; /* voltage level control */ 133 }; 134 135 struct rockchip_connector; 136 struct dw_hdmi_phy_ops { 137 int (*init)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data); 138 void (*disable)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data); 139 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, 140 void *data); 141 void (*mode_valid)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data); 142 }; 143 144 struct dw_hdmi_qp_phy_ops { 145 int (*init)(struct rockchip_connector *conn, void *hdmi, void *data); 146 void (*disable)(struct rockchip_connector *conn, void *hdmi, void *data); 147 enum drm_connector_status (*read_hpd)(void *data); 148 void (*mode_valid)(void *hdmi, void *data); 149 void (*set_pll)(struct rockchip_connector *conn, void *hdmi, void *data); 150 }; 151 152 struct dw_hdmi_link_config { 153 bool dsc_mode; 154 bool frl_mode; 155 int frl_lanes; 156 int rate_per_lane; 157 int hcactive; 158 bool allm_en; 159 u8 pps_payload[128]; 160 }; 161 162 struct dw_hdmi_plat_data { 163 enum dw_hdmi_devtype dev_type; 164 unsigned long input_bus_format; 165 unsigned long input_bus_encoding; 166 u32 vop_sel_bit; 167 u32 grf_vop_sel_reg; 168 /* Vendor PHY support */ 169 const struct dw_hdmi_phy_ops *phy_ops; 170 const struct dw_hdmi_qp_phy_ops *qp_phy_ops; 171 const struct dw_hdmi_audio_tmds_n *tmds_n_table; 172 const char *phy_name; 173 void *phy_data; 174 void *hdmi; 175 176 /* Synopsys PHY support */ 177 const struct dw_hdmi_mpll_config *mpll_cfg; 178 const struct dw_hdmi_mpll_config *mpll_cfg_420; 179 const struct dw_hdmi_curr_ctrl *cur_ctr; 180 const struct dw_hdmi_phy_config *phy_config; 181 int (*configure_phy)(struct dw_hdmi *hdmi, 182 const struct dw_hdmi_plat_data *pdata, 183 unsigned long mpixelclock); 184 unsigned long (*get_input_bus_format)(void *data); 185 unsigned long (*get_output_bus_format)(void *data); 186 unsigned long (*get_enc_in_encoding)(void *data); 187 unsigned long (*get_enc_out_encoding)(void *data); 188 unsigned long (*get_quant_range)(void *data); 189 }; 190 191 #endif /* __IMX_HDMI_H__ */ 192