1 /* 2 * Copyright (C) 2011 Freescale Semiconductor, Inc. 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 #ifndef __DW_HDMI__ 11 #define __DW_HDMI__ 12 13 /** 14 * DOC: Supported input formats and encodings 15 * 16 * Depending on the Hardware configuration of the Controller IP, it supports 17 * a subset of the following input formats and encodings on its internal 18 * 48bit bus. 19 * 20 * +----------------------+----------------------------------+------------------------------+ 21 * + Format Name + Format Code + Encodings + 22 * +----------------------+----------------------------------+------------------------------+ 23 * + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 24 * +----------------------+----------------------------------+------------------------------+ 25 * + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 26 * +----------------------+----------------------------------+------------------------------+ 27 * + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 28 * +----------------------+----------------------------------+------------------------------+ 29 * + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` + 30 * +----------------------+----------------------------------+------------------------------+ 31 * + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` + 32 * + + + or ``V4L2_YCBCR_ENC_709`` + 33 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 34 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 35 * +----------------------+----------------------------------+------------------------------+ 36 * + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` + 37 * + + + or ``V4L2_YCBCR_ENC_709`` + 38 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 39 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 40 * +----------------------+----------------------------------+------------------------------+ 41 * + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` + 42 * + + + or ``V4L2_YCBCR_ENC_709`` + 43 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 44 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 45 * +----------------------+----------------------------------+------------------------------+ 46 * + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` + 47 * + + + or ``V4L2_YCBCR_ENC_709`` + 48 * + + + or ``V4L2_YCBCR_ENC_XV601`` + 49 * + + + or ``V4L2_YCBCR_ENC_XV709`` + 50 * +----------------------+----------------------------------+------------------------------+ 51 * + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` + 52 * + + + or ``V4L2_YCBCR_ENC_709`` + 53 * +----------------------+----------------------------------+------------------------------+ 54 * + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` + 55 * + + + or ``V4L2_YCBCR_ENC_709`` + 56 * +----------------------+----------------------------------+------------------------------+ 57 * + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` + 58 * + + + or ``V4L2_YCBCR_ENC_709`` + 59 * +----------------------+----------------------------------+------------------------------+ 60 * + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` + 61 * + + + or ``V4L2_YCBCR_ENC_709`` + 62 * +----------------------+----------------------------------+------------------------------+ 63 * + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` + 64 * + + + or ``V4L2_YCBCR_ENC_709`` + 65 * +----------------------+----------------------------------+------------------------------+ 66 * + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` + 67 * + + + or ``V4L2_YCBCR_ENC_709`` + 68 * +----------------------+----------------------------------+------------------------------+ 69 * + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` + 70 * + + + or ``V4L2_YCBCR_ENC_709`` + 71 * +----------------------+----------------------------------+------------------------------+ 72 */ 73 74 enum { 75 DW_HDMI_RES_8, 76 DW_HDMI_RES_10, 77 DW_HDMI_RES_12, 78 DW_HDMI_RES_MAX, 79 }; 80 81 enum dw_hdmi_devtype { 82 IMX6Q_HDMI, 83 IMX6DL_HDMI, 84 RK3228_HDMI, 85 RK3288_HDMI, 86 RK3328_HDMI, 87 RK3366_HDMI, 88 RK3368_HDMI, 89 RK3399_HDMI, 90 }; 91 92 struct dw_hdmi_audio_tmds_n { 93 unsigned long tmds; 94 unsigned int n_32k; 95 unsigned int n_44k1; 96 unsigned int n_48k; 97 }; 98 99 enum dw_hdmi_phy_type { 100 DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, 101 DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, 102 DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, 103 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, 104 DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, 105 DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, 106 DW_HDMI_PHY_VENDOR_PHY = 0xfe, 107 }; 108 109 struct dw_hdmi_mpll_config { 110 unsigned long mpixelclock; 111 struct { 112 u16 cpce; 113 u16 gmp; 114 } res[DW_HDMI_RES_MAX]; 115 }; 116 117 struct dw_hdmi_curr_ctrl { 118 unsigned long mpixelclock; 119 u16 curr[DW_HDMI_RES_MAX]; 120 }; 121 122 struct dw_hdmi_phy_config { 123 unsigned long mpixelclock; 124 u16 sym_ctr; /*clock symbol and transmitter control*/ 125 u16 term; /*transmission termination value*/ 126 u16 vlev_ctr; /* voltage level control */ 127 }; 128 129 struct dw_hdmi_phy_ops { 130 int (*init)(struct dw_hdmi *hdmi, void *data, 131 struct drm_display_mode *mode); 132 void (*disable)(struct dw_hdmi *hdmi, void *data); 133 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); 134 }; 135 136 struct dw_hdmi_plat_data { 137 enum dw_hdmi_devtype dev_type; 138 unsigned long input_bus_format; 139 unsigned long input_bus_encoding; 140 u32 vop_sel_bit; 141 u32 grf_vop_sel_reg; 142 /* Vendor PHY support */ 143 const struct dw_hdmi_phy_ops *phy_ops; 144 const struct dw_hdmi_audio_tmds_n *tmds_n_table; 145 const char *phy_name; 146 void *phy_data; 147 148 /* Synopsys PHY support */ 149 const struct dw_hdmi_mpll_config *mpll_cfg; 150 const struct dw_hdmi_curr_ctrl *cur_ctr; 151 const struct dw_hdmi_phy_config *phy_config; 152 int (*configure_phy)(struct dw_hdmi *hdmi, 153 const struct dw_hdmi_plat_data *pdata, 154 unsigned long mpixelclock); 155 unsigned long (*get_input_bus_format)(void *data); 156 unsigned long (*get_output_bus_format)(void *data); 157 unsigned long (*get_enc_in_encoding)(void *data); 158 unsigned long (*get_enc_out_encoding)(void *data); 159 }; 160 161 #endif /* __IMX_HDMI_H__ */ 162