1fe8c2806Swdenk /* 28655b6f8Swdenk * MPC823 and PXA LCD Controller 3fe8c2806Swdenk * 4fe8c2806Swdenk * Modeled after video interface by Paolo Scaffardi 5fe8c2806Swdenk * 6fe8c2806Swdenk * 7fe8c2806Swdenk * (C) Copyright 2001 8fe8c2806Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9fe8c2806Swdenk * 10fe8c2806Swdenk * See file CREDITS for list of people who contributed to this 11fe8c2806Swdenk * project. 12fe8c2806Swdenk * 13fe8c2806Swdenk * This program is free software; you can redistribute it and/or 14fe8c2806Swdenk * modify it under the terms of the GNU General Public License as 15fe8c2806Swdenk * published by the Free Software Foundation; either version 2 of 16fe8c2806Swdenk * the License, or (at your option) any later version. 17fe8c2806Swdenk * 18fe8c2806Swdenk * This program is distributed in the hope that it will be useful, 19fe8c2806Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 20fe8c2806Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21fe8c2806Swdenk * GNU General Public License for more details. 22fe8c2806Swdenk * 23fe8c2806Swdenk * You should have received a copy of the GNU General Public License 24fe8c2806Swdenk * along with this program; if not, write to the Free Software 25fe8c2806Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26fe8c2806Swdenk * MA 02111-1307 USA 27fe8c2806Swdenk */ 28fe8c2806Swdenk 29fe8c2806Swdenk #ifndef _LCD_H_ 30fe8c2806Swdenk #define _LCD_H_ 31fe8c2806Swdenk 328655b6f8Swdenk extern char lcd_is_enabled; 338655b6f8Swdenk 348655b6f8Swdenk extern int lcd_line_length; 358655b6f8Swdenk extern int lcd_color_fg; 368655b6f8Swdenk extern int lcd_color_bg; 378655b6f8Swdenk 388655b6f8Swdenk /* 398655b6f8Swdenk * Frame buffer memory information 408655b6f8Swdenk */ 418655b6f8Swdenk extern void *lcd_base; /* Start of framebuffer memory */ 428655b6f8Swdenk extern void *lcd_console_address; /* Start of console buffer */ 438655b6f8Swdenk 448655b6f8Swdenk extern short console_col; 458655b6f8Swdenk extern short console_row; 466111722aSAlessandro Rubini extern struct vidinfo panel_info; 476111722aSAlessandro Rubini 486111722aSAlessandro Rubini extern void lcd_ctrl_init (void *lcdbase); 496111722aSAlessandro Rubini extern void lcd_enable (void); 506111722aSAlessandro Rubini 516111722aSAlessandro Rubini /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ 526111722aSAlessandro Rubini extern void lcd_setcolreg (ushort regno, 536111722aSAlessandro Rubini ushort red, ushort green, ushort blue); 546111722aSAlessandro Rubini extern void lcd_initcolregs (void); 556111722aSAlessandro Rubini 566111722aSAlessandro Rubini /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ 576111722aSAlessandro Rubini extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp); 58de3b49c4SAnatolij Gustschin extern int bmp_display(ulong addr, int x, int y); 598655b6f8Swdenk 60*9a8efc46SSimon Glass /** 61*9a8efc46SSimon Glass * Set whether we need to flush the dcache when changing the LCD image. This 62*9a8efc46SSimon Glass * defaults to off. 63*9a8efc46SSimon Glass * 64*9a8efc46SSimon Glass * @param flush non-zero to flush cache after update, 0 to skip 65*9a8efc46SSimon Glass */ 66*9a8efc46SSimon Glass void lcd_set_flush_dcache(int flush); 67*9a8efc46SSimon Glass 688655b6f8Swdenk #if defined CONFIG_MPC823 698655b6f8Swdenk /* 708655b6f8Swdenk * LCD controller stucture for MPC823 CPU 718655b6f8Swdenk */ 728655b6f8Swdenk typedef struct vidinfo { 738655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 748655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 758655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 768655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 778655b6f8Swdenk 788655b6f8Swdenk /* LCD configuration register */ 798655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 808655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 818655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 828655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 838655b6f8Swdenk u_char vl_dp; /* Data polarity */ 848655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 858655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 868655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 878655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 888655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 898655b6f8Swdenk 908655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 918655b6f8Swdenk ushort vl_wbl; /* Wait between lines */ 928655b6f8Swdenk 938655b6f8Swdenk /* Vertical control register */ 948655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 958655b6f8Swdenk u_char vl_lcdac; /* LCD AC timing */ 968655b6f8Swdenk u_char vl_wbf; /* Wait between frames */ 978655b6f8Swdenk } vidinfo_t; 988655b6f8Swdenk 99abc20abaSMarek Vasut #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ 100abc20abaSMarek Vasut defined CONFIG_CPU_MONAHANS 1018655b6f8Swdenk /* 1028655b6f8Swdenk * PXA LCD DMA descriptor 1038655b6f8Swdenk */ 1048655b6f8Swdenk struct pxafb_dma_descriptor { 1058655b6f8Swdenk u_long fdadr; /* Frame descriptor address register */ 1068655b6f8Swdenk u_long fsadr; /* Frame source address register */ 1078655b6f8Swdenk u_long fidr; /* Frame ID register */ 1088655b6f8Swdenk u_long ldcmd; /* Command register */ 1098655b6f8Swdenk }; 1108655b6f8Swdenk 1118655b6f8Swdenk /* 1128655b6f8Swdenk * PXA LCD info 1138655b6f8Swdenk */ 1148655b6f8Swdenk struct pxafb_info { 1158655b6f8Swdenk 1168655b6f8Swdenk /* Misc registers */ 1178655b6f8Swdenk u_long reg_lccr3; 1188655b6f8Swdenk u_long reg_lccr2; 1198655b6f8Swdenk u_long reg_lccr1; 1208655b6f8Swdenk u_long reg_lccr0; 1218655b6f8Swdenk u_long fdadr0; 1228655b6f8Swdenk u_long fdadr1; 1238655b6f8Swdenk 1248655b6f8Swdenk /* DMA descriptors */ 1258655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fblow; 1268655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fbhigh; 1278655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_palette; 1288655b6f8Swdenk 1298655b6f8Swdenk u_long screen; /* physical address of frame buffer */ 1308655b6f8Swdenk u_long palette; /* physical address of palette memory */ 1318655b6f8Swdenk u_int palette_size; 1328655b6f8Swdenk }; 1338655b6f8Swdenk 1348655b6f8Swdenk /* 1358655b6f8Swdenk * LCD controller stucture for PXA CPU 1368655b6f8Swdenk */ 1378655b6f8Swdenk typedef struct vidinfo { 1388655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 1398655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 1408655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 1418655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 1428655b6f8Swdenk 1438655b6f8Swdenk /* LCD configuration register */ 1448655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 1458655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 1468655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 1478655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 1488655b6f8Swdenk u_char vl_dp; /* Data polarity */ 1498655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 1508655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 1518655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 1528655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 1538655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 1548655b6f8Swdenk 1558655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 1568655b6f8Swdenk ushort vl_hpw; /* Horz sync pulse width */ 1578655b6f8Swdenk u_char vl_blw; /* Wait before of line */ 1588655b6f8Swdenk u_char vl_elw; /* Wait end of line */ 1598655b6f8Swdenk 1608655b6f8Swdenk /* Vertical control register. */ 1618655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 1628655b6f8Swdenk u_char vl_bfw; /* Wait before of frame */ 1638655b6f8Swdenk u_char vl_efw; /* Wait end of frame */ 1648655b6f8Swdenk 1658655b6f8Swdenk /* PXA LCD controller params */ 1668655b6f8Swdenk struct pxafb_info pxa; 1678655b6f8Swdenk } vidinfo_t; 1688655b6f8Swdenk 169f6b690e6SBo Shen #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) 17039cf4804SStelian Pop 17139cf4804SStelian Pop typedef struct vidinfo { 17278459123SMarek Vasut ushort vl_col; /* Number of columns (i.e. 640) */ 17378459123SMarek Vasut ushort vl_row; /* Number of rows (i.e. 480) */ 17439cf4804SStelian Pop u_long vl_clk; /* pixel clock in ps */ 17539cf4804SStelian Pop 17639cf4804SStelian Pop /* LCD configuration register */ 17739cf4804SStelian Pop u_long vl_sync; /* Horizontal / vertical sync */ 17839cf4804SStelian Pop u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 17939cf4804SStelian Pop u_long vl_tft; /* 0 = passive, 1 = TFT */ 180cdfcedbfSAlexander Stein u_long vl_cont_pol_low; /* contrast polarity is low */ 181f6b690e6SBo Shen u_long vl_clk_pol; /* clock polarity */ 18239cf4804SStelian Pop 18339cf4804SStelian Pop /* Horizontal control register. */ 18439cf4804SStelian Pop u_long vl_hsync_len; /* Length of horizontal sync */ 18539cf4804SStelian Pop u_long vl_left_margin; /* Time from sync to picture */ 18639cf4804SStelian Pop u_long vl_right_margin; /* Time from picture to sync */ 18739cf4804SStelian Pop 18839cf4804SStelian Pop /* Vertical control register. */ 18939cf4804SStelian Pop u_long vl_vsync_len; /* Length of vertical sync */ 19039cf4804SStelian Pop u_long vl_upper_margin; /* Time from sync to picture */ 19139cf4804SStelian Pop u_long vl_lower_margin; /* Time from picture to sync */ 19239cf4804SStelian Pop 19339cf4804SStelian Pop u_long mmio; /* Memory mapped registers */ 19439cf4804SStelian Pop } vidinfo_t; 19539cf4804SStelian Pop 196559a05ccSDonghwa Lee #elif defined(CONFIG_EXYNOS_FB) 197559a05ccSDonghwa Lee 198559a05ccSDonghwa Lee enum { 199559a05ccSDonghwa Lee FIMD_RGB_INTERFACE = 1, 200559a05ccSDonghwa Lee FIMD_CPU_INTERFACE = 2, 201559a05ccSDonghwa Lee }; 202559a05ccSDonghwa Lee 20390464971SDonghwa Lee enum exynos_fb_rgb_mode_t { 20490464971SDonghwa Lee MODE_RGB_P = 0, 20590464971SDonghwa Lee MODE_BGR_P = 1, 20690464971SDonghwa Lee MODE_RGB_S = 2, 20790464971SDonghwa Lee MODE_BGR_S = 3, 20890464971SDonghwa Lee }; 20990464971SDonghwa Lee 210559a05ccSDonghwa Lee typedef struct vidinfo { 211559a05ccSDonghwa Lee ushort vl_col; /* Number of columns (i.e. 640) */ 212559a05ccSDonghwa Lee ushort vl_row; /* Number of rows (i.e. 480) */ 213559a05ccSDonghwa Lee ushort vl_width; /* Width of display area in millimeters */ 214559a05ccSDonghwa Lee ushort vl_height; /* Height of display area in millimeters */ 215559a05ccSDonghwa Lee 216559a05ccSDonghwa Lee /* LCD configuration register */ 217559a05ccSDonghwa Lee u_char vl_freq; /* Frequency */ 218559a05ccSDonghwa Lee u_char vl_clkp; /* Clock polarity */ 219559a05ccSDonghwa Lee u_char vl_oep; /* Output Enable polarity */ 220559a05ccSDonghwa Lee u_char vl_hsp; /* Horizontal Sync polarity */ 221559a05ccSDonghwa Lee u_char vl_vsp; /* Vertical Sync polarity */ 222559a05ccSDonghwa Lee u_char vl_dp; /* Data polarity */ 223559a05ccSDonghwa Lee u_char vl_bpix; /* Bits per pixel */ 224559a05ccSDonghwa Lee 225559a05ccSDonghwa Lee /* Horizontal control register. Timing from data sheet */ 226559a05ccSDonghwa Lee u_char vl_hspw; /* Horz sync pulse width */ 227559a05ccSDonghwa Lee u_char vl_hfpd; /* Wait before of line */ 228559a05ccSDonghwa Lee u_char vl_hbpd; /* Wait end of line */ 229559a05ccSDonghwa Lee 230559a05ccSDonghwa Lee /* Vertical control register. */ 231559a05ccSDonghwa Lee u_char vl_vspw; /* Vertical sync pulse width */ 232559a05ccSDonghwa Lee u_char vl_vfpd; /* Wait before of frame */ 233559a05ccSDonghwa Lee u_char vl_vbpd; /* Wait end of frame */ 234559a05ccSDonghwa Lee u_char vl_cmd_allow_len; /* Wait end of frame */ 235559a05ccSDonghwa Lee 236559a05ccSDonghwa Lee void (*cfg_gpio)(void); 237559a05ccSDonghwa Lee void (*backlight_on)(unsigned int onoff); 238559a05ccSDonghwa Lee void (*reset_lcd)(void); 239559a05ccSDonghwa Lee void (*lcd_power_on)(void); 240559a05ccSDonghwa Lee void (*cfg_ldo)(void); 241559a05ccSDonghwa Lee void (*enable_ldo)(unsigned int onoff); 242559a05ccSDonghwa Lee void (*mipi_power)(void); 243559a05ccSDonghwa Lee void (*backlight_reset)(void); 244559a05ccSDonghwa Lee 245559a05ccSDonghwa Lee unsigned int win_id; 246559a05ccSDonghwa Lee unsigned int init_delay; 247559a05ccSDonghwa Lee unsigned int power_on_delay; 248559a05ccSDonghwa Lee unsigned int reset_delay; 249559a05ccSDonghwa Lee unsigned int interface_mode; 250559a05ccSDonghwa Lee unsigned int mipi_enabled; 2515addfcfcSDonghwa Lee unsigned int dp_enabled; 252559a05ccSDonghwa Lee unsigned int cs_setup; 253559a05ccSDonghwa Lee unsigned int wr_setup; 254559a05ccSDonghwa Lee unsigned int wr_act; 255559a05ccSDonghwa Lee unsigned int wr_hold; 25690464971SDonghwa Lee unsigned int logo_on; 25790464971SDonghwa Lee unsigned int logo_width; 25890464971SDonghwa Lee unsigned int logo_height; 25990464971SDonghwa Lee unsigned long logo_addr; 26090464971SDonghwa Lee unsigned int rgb_mode; 26190464971SDonghwa Lee unsigned int resolution; 262559a05ccSDonghwa Lee 263559a05ccSDonghwa Lee /* parent clock name(MPLL, EPLL or VPLL) */ 264559a05ccSDonghwa Lee unsigned int pclk_name; 265559a05ccSDonghwa Lee /* ratio value for source clock from parent clock. */ 266559a05ccSDonghwa Lee unsigned int sclk_div; 267559a05ccSDonghwa Lee 268559a05ccSDonghwa Lee unsigned int dual_lcd_enabled; 269559a05ccSDonghwa Lee 270559a05ccSDonghwa Lee } vidinfo_t; 271559a05ccSDonghwa Lee 272559a05ccSDonghwa Lee void init_panel_info(vidinfo_t *vid); 273559a05ccSDonghwa Lee 274b245e65eSGuennadi Liakhovetski #else 275b245e65eSGuennadi Liakhovetski 276b245e65eSGuennadi Liakhovetski typedef struct vidinfo { 277b245e65eSGuennadi Liakhovetski ushort vl_col; /* Number of columns (i.e. 160) */ 278b245e65eSGuennadi Liakhovetski ushort vl_row; /* Number of rows (i.e. 100) */ 279b245e65eSGuennadi Liakhovetski 280b245e65eSGuennadi Liakhovetski u_char vl_bpix; /* Bits per pixel, 0 = 1 */ 281b245e65eSGuennadi Liakhovetski 282b245e65eSGuennadi Liakhovetski ushort *cmap; /* Pointer to the colormap */ 283b245e65eSGuennadi Liakhovetski 284b245e65eSGuennadi Liakhovetski void *priv; /* Pointer to driver-specific data */ 285b245e65eSGuennadi Liakhovetski } vidinfo_t; 286b245e65eSGuennadi Liakhovetski 287abc20abaSMarek Vasut #endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ 2888655b6f8Swdenk 28960e97419SAlessandro Rubini extern vidinfo_t panel_info; 29060e97419SAlessandro Rubini 2918655b6f8Swdenk /* Video functions */ 2928655b6f8Swdenk 293682011ffSwdenk #if defined(CONFIG_RBC823) 294682011ffSwdenk void lcd_disable (void); 295682011ffSwdenk #endif 296682011ffSwdenk 297fe8c2806Swdenk 298c3f4d17eSwdenk /* int lcd_init (void *lcdbase); */ 299fe8c2806Swdenk void lcd_putc (const char c); 300fe8c2806Swdenk void lcd_puts (const char *s); 301fe8c2806Swdenk void lcd_printf (const char *fmt, ...); 30202110903SChe-Liang Chiou void lcd_clear(void); 30302110903SChe-Liang Chiou int lcd_display_bitmap(ulong bmp_image, int x, int y); 304fe8c2806Swdenk 3056b59e03eSHaavard Skinnemoen /* Allow boards to customize the information displayed */ 3066b59e03eSHaavard Skinnemoen void lcd_show_board_info(void); 3078655b6f8Swdenk 308676d319eSSimon Glass /* Return the size of the LCD frame buffer, and the line length */ 309676d319eSSimon Glass int lcd_get_size(int *line_length); 310676d319eSSimon Glass 3118655b6f8Swdenk /************************************************************************/ 3128655b6f8Swdenk /* ** BITMAP DISPLAY SUPPORT */ 3138655b6f8Swdenk /************************************************************************/ 314639221c7SJon Loeliger #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) 3158655b6f8Swdenk # include <bmp_layout.h> 3168655b6f8Swdenk # include <asm/byteorder.h> 317639221c7SJon Loeliger #endif 3188655b6f8Swdenk 3198655b6f8Swdenk /* 3208655b6f8Swdenk * Information about displays we are using. This is for configuring 3218655b6f8Swdenk * the LCD controller and memory allocation. Someone has to know what 3228655b6f8Swdenk * is connected, as we can't autodetect anything. 3238655b6f8Swdenk */ 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HIGH 0 /* Pins are active high */ 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOW 1 /* Pins are active low */ 3268655b6f8Swdenk 3278655b6f8Swdenk #define LCD_MONOCHROME 0 3288655b6f8Swdenk #define LCD_COLOR2 1 3298655b6f8Swdenk #define LCD_COLOR4 2 3308655b6f8Swdenk #define LCD_COLOR8 3 3318655b6f8Swdenk #define LCD_COLOR16 4 3328655b6f8Swdenk 3338655b6f8Swdenk /*----------------------------------------------------------------------*/ 33488804d19Swdenk #if defined(CONFIG_LCD_INFO_BELOW_LOGO) 3358655b6f8Swdenk # define LCD_INFO_X 0 3368655b6f8Swdenk # define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) 3378655b6f8Swdenk #elif defined(CONFIG_LCD_LOGO) 3388655b6f8Swdenk # define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) 3398655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 3408655b6f8Swdenk #else 3418655b6f8Swdenk # define LCD_INFO_X (VIDEO_FONT_WIDTH) 3428655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 3438655b6f8Swdenk #endif 3448655b6f8Swdenk 3458655b6f8Swdenk /* Default to 8bpp if bit depth not specified */ 3468655b6f8Swdenk #ifndef LCD_BPP 3478655b6f8Swdenk # define LCD_BPP LCD_COLOR8 3488655b6f8Swdenk #endif 3498655b6f8Swdenk #ifndef LCD_DF 3508655b6f8Swdenk # define LCD_DF 1 3518655b6f8Swdenk #endif 3528655b6f8Swdenk 3538655b6f8Swdenk /* Calculate nr. of bits per pixel and nr. of colors */ 3548655b6f8Swdenk #define NBITS(bit_code) (1 << (bit_code)) 3558655b6f8Swdenk #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 3568655b6f8Swdenk 3578655b6f8Swdenk /************************************************************************/ 3588655b6f8Swdenk /* ** CONSOLE CONSTANTS */ 3598655b6f8Swdenk /************************************************************************/ 3608655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 3618655b6f8Swdenk 3628655b6f8Swdenk /* 3638655b6f8Swdenk * Simple black/white definitions 3648655b6f8Swdenk */ 3658655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 3668655b6f8Swdenk # define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ 3678655b6f8Swdenk 3688655b6f8Swdenk #elif LCD_BPP == LCD_COLOR8 3698655b6f8Swdenk 3708655b6f8Swdenk /* 3718655b6f8Swdenk * 8bpp color definitions 3728655b6f8Swdenk */ 3738655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 3748655b6f8Swdenk # define CONSOLE_COLOR_RED 1 3758655b6f8Swdenk # define CONSOLE_COLOR_GREEN 2 3768655b6f8Swdenk # define CONSOLE_COLOR_YELLOW 3 3778655b6f8Swdenk # define CONSOLE_COLOR_BLUE 4 3788655b6f8Swdenk # define CONSOLE_COLOR_MAGENTA 5 3798655b6f8Swdenk # define CONSOLE_COLOR_CYAN 6 3808655b6f8Swdenk # define CONSOLE_COLOR_GREY 14 3818655b6f8Swdenk # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ 3828655b6f8Swdenk 3838655b6f8Swdenk #else 3848655b6f8Swdenk 3858655b6f8Swdenk /* 3868655b6f8Swdenk * 16bpp color definitions 3878655b6f8Swdenk */ 3888655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0x0000 3898655b6f8Swdenk # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ 3908655b6f8Swdenk 3918655b6f8Swdenk #endif /* color definitions */ 3928655b6f8Swdenk 3938655b6f8Swdenk /************************************************************************/ 3948655b6f8Swdenk #ifndef PAGE_SIZE 3958655b6f8Swdenk # define PAGE_SIZE 4096 3968655b6f8Swdenk #endif 3978655b6f8Swdenk 3988655b6f8Swdenk /************************************************************************/ 3998655b6f8Swdenk /* ** CONSOLE DEFINITIONS & FUNCTIONS */ 4008655b6f8Swdenk /************************************************************************/ 40188804d19Swdenk #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) 4028655b6f8Swdenk # define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ 4038655b6f8Swdenk / VIDEO_FONT_HEIGHT) 4048655b6f8Swdenk #else 4058655b6f8Swdenk # define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) 4068655b6f8Swdenk #endif 4078655b6f8Swdenk 4088655b6f8Swdenk #define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) 4098655b6f8Swdenk #define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) 4108655b6f8Swdenk #define CONSOLE_ROW_FIRST (lcd_console_address) 4118655b6f8Swdenk #define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) 4128655b6f8Swdenk #define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ 4138655b6f8Swdenk - CONSOLE_ROW_SIZE) 4148655b6f8Swdenk #define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) 4158655b6f8Swdenk #define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) 4168655b6f8Swdenk 4178655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 4188655b6f8Swdenk # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ 4198655b6f8Swdenk (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) 42069f32e6cSMark Jackson #elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) 4218655b6f8Swdenk # define COLOR_MASK(c) (c) 4228655b6f8Swdenk #else 4238655b6f8Swdenk # error Unsupported LCD BPP. 4248655b6f8Swdenk #endif 4258655b6f8Swdenk 4268655b6f8Swdenk /************************************************************************/ 4278655b6f8Swdenk 4288655b6f8Swdenk #endif /* _LCD_H_ */ 429