1fe8c2806Swdenk /* 28655b6f8Swdenk * MPC823 and PXA LCD Controller 3fe8c2806Swdenk * 4fe8c2806Swdenk * Modeled after video interface by Paolo Scaffardi 5fe8c2806Swdenk * 6fe8c2806Swdenk * 7fe8c2806Swdenk * (C) Copyright 2001 8fe8c2806Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9fe8c2806Swdenk * 10fe8c2806Swdenk * See file CREDITS for list of people who contributed to this 11fe8c2806Swdenk * project. 12fe8c2806Swdenk * 13fe8c2806Swdenk * This program is free software; you can redistribute it and/or 14fe8c2806Swdenk * modify it under the terms of the GNU General Public License as 15fe8c2806Swdenk * published by the Free Software Foundation; either version 2 of 16fe8c2806Swdenk * the License, or (at your option) any later version. 17fe8c2806Swdenk * 18fe8c2806Swdenk * This program is distributed in the hope that it will be useful, 19fe8c2806Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 20fe8c2806Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21fe8c2806Swdenk * GNU General Public License for more details. 22fe8c2806Swdenk * 23fe8c2806Swdenk * You should have received a copy of the GNU General Public License 24fe8c2806Swdenk * along with this program; if not, write to the Free Software 25fe8c2806Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26fe8c2806Swdenk * MA 02111-1307 USA 27fe8c2806Swdenk */ 28fe8c2806Swdenk 29fe8c2806Swdenk #ifndef _LCD_H_ 30fe8c2806Swdenk #define _LCD_H_ 31fe8c2806Swdenk 328655b6f8Swdenk extern char lcd_is_enabled; 338655b6f8Swdenk 348655b6f8Swdenk extern int lcd_line_length; 358655b6f8Swdenk extern int lcd_color_fg; 368655b6f8Swdenk extern int lcd_color_bg; 378655b6f8Swdenk 388655b6f8Swdenk /* 398655b6f8Swdenk * Frame buffer memory information 408655b6f8Swdenk */ 418655b6f8Swdenk extern void *lcd_base; /* Start of framebuffer memory */ 428655b6f8Swdenk extern void *lcd_console_address; /* Start of console buffer */ 438655b6f8Swdenk 448655b6f8Swdenk extern short console_col; 458655b6f8Swdenk extern short console_row; 468655b6f8Swdenk 478655b6f8Swdenk #if defined CONFIG_MPC823 488655b6f8Swdenk /* 498655b6f8Swdenk * LCD controller stucture for MPC823 CPU 508655b6f8Swdenk */ 518655b6f8Swdenk typedef struct vidinfo { 528655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 538655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 548655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 558655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 568655b6f8Swdenk 578655b6f8Swdenk /* LCD configuration register */ 588655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 598655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 608655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 618655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 628655b6f8Swdenk u_char vl_dp; /* Data polarity */ 638655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 648655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 658655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 668655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 678655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 688655b6f8Swdenk 698655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 708655b6f8Swdenk ushort vl_wbl; /* Wait between lines */ 718655b6f8Swdenk 728655b6f8Swdenk /* Vertical control register */ 738655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 748655b6f8Swdenk u_char vl_lcdac; /* LCD AC timing */ 758655b6f8Swdenk u_char vl_wbf; /* Wait between frames */ 768655b6f8Swdenk } vidinfo_t; 778655b6f8Swdenk 788655b6f8Swdenk extern vidinfo_t panel_info; 798655b6f8Swdenk 808655b6f8Swdenk #elif defined CONFIG_PXA250 818655b6f8Swdenk /* 828655b6f8Swdenk * PXA LCD DMA descriptor 838655b6f8Swdenk */ 848655b6f8Swdenk struct pxafb_dma_descriptor { 858655b6f8Swdenk u_long fdadr; /* Frame descriptor address register */ 868655b6f8Swdenk u_long fsadr; /* Frame source address register */ 878655b6f8Swdenk u_long fidr; /* Frame ID register */ 888655b6f8Swdenk u_long ldcmd; /* Command register */ 898655b6f8Swdenk }; 908655b6f8Swdenk 918655b6f8Swdenk /* 928655b6f8Swdenk * PXA LCD info 938655b6f8Swdenk */ 948655b6f8Swdenk struct pxafb_info { 958655b6f8Swdenk 968655b6f8Swdenk /* Misc registers */ 978655b6f8Swdenk u_long reg_lccr3; 988655b6f8Swdenk u_long reg_lccr2; 998655b6f8Swdenk u_long reg_lccr1; 1008655b6f8Swdenk u_long reg_lccr0; 1018655b6f8Swdenk u_long fdadr0; 1028655b6f8Swdenk u_long fdadr1; 1038655b6f8Swdenk 1048655b6f8Swdenk /* DMA descriptors */ 1058655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fblow; 1068655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fbhigh; 1078655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_palette; 1088655b6f8Swdenk 1098655b6f8Swdenk u_long screen; /* physical address of frame buffer */ 1108655b6f8Swdenk u_long palette; /* physical address of palette memory */ 1118655b6f8Swdenk u_int palette_size; 1128655b6f8Swdenk }; 1138655b6f8Swdenk 1148655b6f8Swdenk /* 1158655b6f8Swdenk * LCD controller stucture for PXA CPU 1168655b6f8Swdenk */ 1178655b6f8Swdenk typedef struct vidinfo { 1188655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 1198655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 1208655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 1218655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 1228655b6f8Swdenk 1238655b6f8Swdenk /* LCD configuration register */ 1248655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 1258655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 1268655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 1278655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 1288655b6f8Swdenk u_char vl_dp; /* Data polarity */ 1298655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 1308655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 1318655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 1328655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 1338655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 1348655b6f8Swdenk 1358655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 1368655b6f8Swdenk ushort vl_hpw; /* Horz sync pulse width */ 1378655b6f8Swdenk u_char vl_blw; /* Wait before of line */ 1388655b6f8Swdenk u_char vl_elw; /* Wait end of line */ 1398655b6f8Swdenk 1408655b6f8Swdenk /* Vertical control register. */ 1418655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 1428655b6f8Swdenk u_char vl_bfw; /* Wait before of frame */ 1438655b6f8Swdenk u_char vl_efw; /* Wait end of frame */ 1448655b6f8Swdenk 1458655b6f8Swdenk /* PXA LCD controller params */ 1468655b6f8Swdenk struct pxafb_info pxa; 1478655b6f8Swdenk } vidinfo_t; 1488655b6f8Swdenk 1498655b6f8Swdenk extern vidinfo_t panel_info; 1508655b6f8Swdenk 151e8143e72SWolfgang Denk #elif defined(CONFIG_MCC200) 152e8143e72SWolfgang Denk typedef struct vidinfo { 153e8143e72SWolfgang Denk ushort vl_col; /* Number of columns (i.e. 160) */ 154e8143e72SWolfgang Denk ushort vl_row; /* Number of rows (i.e. 100) */ 155e8143e72SWolfgang Denk 156e8143e72SWolfgang Denk u_char vl_bpix; /* Bits per pixel, 0 = 1 */ 157e8143e72SWolfgang Denk } vidinfo_t; 15839cf4804SStelian Pop 15939cf4804SStelian Pop #elif defined(CONFIG_ATMEL_LCD) 16039cf4804SStelian Pop 16139cf4804SStelian Pop typedef struct vidinfo { 16239cf4804SStelian Pop u_long vl_col; /* Number of columns (i.e. 640) */ 16339cf4804SStelian Pop u_long vl_row; /* Number of rows (i.e. 480) */ 16439cf4804SStelian Pop u_long vl_clk; /* pixel clock in ps */ 16539cf4804SStelian Pop 16639cf4804SStelian Pop /* LCD configuration register */ 16739cf4804SStelian Pop u_long vl_sync; /* Horizontal / vertical sync */ 16839cf4804SStelian Pop u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 16939cf4804SStelian Pop u_long vl_tft; /* 0 = passive, 1 = TFT */ 17039cf4804SStelian Pop 17139cf4804SStelian Pop /* Horizontal control register. */ 17239cf4804SStelian Pop u_long vl_hsync_len; /* Length of horizontal sync */ 17339cf4804SStelian Pop u_long vl_left_margin; /* Time from sync to picture */ 17439cf4804SStelian Pop u_long vl_right_margin; /* Time from picture to sync */ 17539cf4804SStelian Pop 17639cf4804SStelian Pop /* Vertical control register. */ 17739cf4804SStelian Pop u_long vl_vsync_len; /* Length of vertical sync */ 17839cf4804SStelian Pop u_long vl_upper_margin; /* Time from sync to picture */ 17939cf4804SStelian Pop u_long vl_lower_margin; /* Time from picture to sync */ 18039cf4804SStelian Pop 18139cf4804SStelian Pop u_long mmio; /* Memory mapped registers */ 18239cf4804SStelian Pop } vidinfo_t; 18339cf4804SStelian Pop 18439cf4804SStelian Pop extern vidinfo_t panel_info; 18539cf4804SStelian Pop 18639cf4804SStelian Pop #endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */ 1878655b6f8Swdenk 1888655b6f8Swdenk /* Video functions */ 1898655b6f8Swdenk 190682011ffSwdenk #if defined(CONFIG_RBC823) 191682011ffSwdenk void lcd_disable (void); 192682011ffSwdenk #endif 193682011ffSwdenk 194fe8c2806Swdenk 195c3f4d17eSwdenk /* int lcd_init (void *lcdbase); */ 196fe8c2806Swdenk void lcd_putc (const char c); 197fe8c2806Swdenk void lcd_puts (const char *s); 198fe8c2806Swdenk void lcd_printf (const char *fmt, ...); 199fe8c2806Swdenk 200*6b59e03eSHaavard Skinnemoen /* Allow boards to customize the information displayed */ 201*6b59e03eSHaavard Skinnemoen void lcd_show_board_info(void); 2028655b6f8Swdenk 2038655b6f8Swdenk /************************************************************************/ 2048655b6f8Swdenk /* ** BITMAP DISPLAY SUPPORT */ 2058655b6f8Swdenk /************************************************************************/ 206639221c7SJon Loeliger #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) 2078655b6f8Swdenk # include <bmp_layout.h> 2088655b6f8Swdenk # include <asm/byteorder.h> 209639221c7SJon Loeliger #endif 2108655b6f8Swdenk 2118655b6f8Swdenk /* 2128655b6f8Swdenk * Information about displays we are using. This is for configuring 2138655b6f8Swdenk * the LCD controller and memory allocation. Someone has to know what 2148655b6f8Swdenk * is connected, as we can't autodetect anything. 2158655b6f8Swdenk */ 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HIGH 0 /* Pins are active high */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOW 1 /* Pins are active low */ 2188655b6f8Swdenk 2198655b6f8Swdenk #define LCD_MONOCHROME 0 2208655b6f8Swdenk #define LCD_COLOR2 1 2218655b6f8Swdenk #define LCD_COLOR4 2 2228655b6f8Swdenk #define LCD_COLOR8 3 2238655b6f8Swdenk #define LCD_COLOR16 4 2248655b6f8Swdenk 2258655b6f8Swdenk /*----------------------------------------------------------------------*/ 22688804d19Swdenk #if defined(CONFIG_LCD_INFO_BELOW_LOGO) 2278655b6f8Swdenk # define LCD_INFO_X 0 2288655b6f8Swdenk # define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) 2298655b6f8Swdenk #elif defined(CONFIG_LCD_LOGO) 2308655b6f8Swdenk # define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) 2318655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 2328655b6f8Swdenk #else 2338655b6f8Swdenk # define LCD_INFO_X (VIDEO_FONT_WIDTH) 2348655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 2358655b6f8Swdenk #endif 2368655b6f8Swdenk 2378655b6f8Swdenk /* Default to 8bpp if bit depth not specified */ 2388655b6f8Swdenk #ifndef LCD_BPP 2398655b6f8Swdenk # define LCD_BPP LCD_COLOR8 2408655b6f8Swdenk #endif 2418655b6f8Swdenk #ifndef LCD_DF 2428655b6f8Swdenk # define LCD_DF 1 2438655b6f8Swdenk #endif 2448655b6f8Swdenk 2458655b6f8Swdenk /* Calculate nr. of bits per pixel and nr. of colors */ 2468655b6f8Swdenk #define NBITS(bit_code) (1 << (bit_code)) 2478655b6f8Swdenk #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 2488655b6f8Swdenk 2498655b6f8Swdenk /************************************************************************/ 2508655b6f8Swdenk /* ** CONSOLE CONSTANTS */ 2518655b6f8Swdenk /************************************************************************/ 2528655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 2538655b6f8Swdenk 2548655b6f8Swdenk /* 2558655b6f8Swdenk * Simple black/white definitions 2568655b6f8Swdenk */ 2578655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 2588655b6f8Swdenk # define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ 2598655b6f8Swdenk 2608655b6f8Swdenk #elif LCD_BPP == LCD_COLOR8 2618655b6f8Swdenk 2628655b6f8Swdenk /* 2638655b6f8Swdenk * 8bpp color definitions 2648655b6f8Swdenk */ 2658655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 2668655b6f8Swdenk # define CONSOLE_COLOR_RED 1 2678655b6f8Swdenk # define CONSOLE_COLOR_GREEN 2 2688655b6f8Swdenk # define CONSOLE_COLOR_YELLOW 3 2698655b6f8Swdenk # define CONSOLE_COLOR_BLUE 4 2708655b6f8Swdenk # define CONSOLE_COLOR_MAGENTA 5 2718655b6f8Swdenk # define CONSOLE_COLOR_CYAN 6 2728655b6f8Swdenk # define CONSOLE_COLOR_GREY 14 2738655b6f8Swdenk # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ 2748655b6f8Swdenk 2758655b6f8Swdenk #else 2768655b6f8Swdenk 2778655b6f8Swdenk /* 2788655b6f8Swdenk * 16bpp color definitions 2798655b6f8Swdenk */ 2808655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0x0000 2818655b6f8Swdenk # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ 2828655b6f8Swdenk 2838655b6f8Swdenk #endif /* color definitions */ 2848655b6f8Swdenk 2858655b6f8Swdenk /************************************************************************/ 2868655b6f8Swdenk #ifndef PAGE_SIZE 2878655b6f8Swdenk # define PAGE_SIZE 4096 2888655b6f8Swdenk #endif 2898655b6f8Swdenk 2908655b6f8Swdenk /************************************************************************/ 2918655b6f8Swdenk /* ** CONSOLE DEFINITIONS & FUNCTIONS */ 2928655b6f8Swdenk /************************************************************************/ 29388804d19Swdenk #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) 2948655b6f8Swdenk # define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ 2958655b6f8Swdenk / VIDEO_FONT_HEIGHT) 2968655b6f8Swdenk #else 2978655b6f8Swdenk # define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) 2988655b6f8Swdenk #endif 2998655b6f8Swdenk 3008655b6f8Swdenk #define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) 3018655b6f8Swdenk #define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) 3028655b6f8Swdenk #define CONSOLE_ROW_FIRST (lcd_console_address) 3038655b6f8Swdenk #define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) 3048655b6f8Swdenk #define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ 3058655b6f8Swdenk - CONSOLE_ROW_SIZE) 3068655b6f8Swdenk #define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) 3078655b6f8Swdenk #define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) 3088655b6f8Swdenk 3098655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 3108655b6f8Swdenk # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ 3118655b6f8Swdenk (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) 3128655b6f8Swdenk #elif LCD_BPP == LCD_COLOR8 3138655b6f8Swdenk # define COLOR_MASK(c) (c) 3148655b6f8Swdenk #else 3158655b6f8Swdenk # error Unsupported LCD BPP. 3168655b6f8Swdenk #endif 3178655b6f8Swdenk 3188655b6f8Swdenk /************************************************************************/ 3198655b6f8Swdenk 3208655b6f8Swdenk #endif /* _LCD_H_ */ 321