1fe8c2806Swdenk /* 28655b6f8Swdenk * MPC823 and PXA LCD Controller 3fe8c2806Swdenk * 4fe8c2806Swdenk * Modeled after video interface by Paolo Scaffardi 5fe8c2806Swdenk * 6fe8c2806Swdenk * 7fe8c2806Swdenk * (C) Copyright 2001 8fe8c2806Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9fe8c2806Swdenk * 10fe8c2806Swdenk * See file CREDITS for list of people who contributed to this 11fe8c2806Swdenk * project. 12fe8c2806Swdenk * 13fe8c2806Swdenk * This program is free software; you can redistribute it and/or 14fe8c2806Swdenk * modify it under the terms of the GNU General Public License as 15fe8c2806Swdenk * published by the Free Software Foundation; either version 2 of 16fe8c2806Swdenk * the License, or (at your option) any later version. 17fe8c2806Swdenk * 18fe8c2806Swdenk * This program is distributed in the hope that it will be useful, 19fe8c2806Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 20fe8c2806Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21fe8c2806Swdenk * GNU General Public License for more details. 22fe8c2806Swdenk * 23fe8c2806Swdenk * You should have received a copy of the GNU General Public License 24fe8c2806Swdenk * along with this program; if not, write to the Free Software 25fe8c2806Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26fe8c2806Swdenk * MA 02111-1307 USA 27fe8c2806Swdenk */ 28fe8c2806Swdenk 29fe8c2806Swdenk #ifndef _LCD_H_ 30fe8c2806Swdenk #define _LCD_H_ 31fe8c2806Swdenk 328655b6f8Swdenk extern char lcd_is_enabled; 338655b6f8Swdenk 348655b6f8Swdenk extern int lcd_line_length; 358655b6f8Swdenk extern int lcd_color_fg; 368655b6f8Swdenk extern int lcd_color_bg; 378655b6f8Swdenk 388655b6f8Swdenk /* 398655b6f8Swdenk * Frame buffer memory information 408655b6f8Swdenk */ 418655b6f8Swdenk extern void *lcd_base; /* Start of framebuffer memory */ 428655b6f8Swdenk extern void *lcd_console_address; /* Start of console buffer */ 438655b6f8Swdenk 448655b6f8Swdenk extern short console_col; 458655b6f8Swdenk extern short console_row; 466111722aSAlessandro Rubini extern struct vidinfo panel_info; 476111722aSAlessandro Rubini 486111722aSAlessandro Rubini extern void lcd_ctrl_init (void *lcdbase); 496111722aSAlessandro Rubini extern void lcd_enable (void); 506111722aSAlessandro Rubini 516111722aSAlessandro Rubini /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ 526111722aSAlessandro Rubini extern void lcd_setcolreg (ushort regno, 536111722aSAlessandro Rubini ushort red, ushort green, ushort blue); 546111722aSAlessandro Rubini extern void lcd_initcolregs (void); 556111722aSAlessandro Rubini 566111722aSAlessandro Rubini /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ 576111722aSAlessandro Rubini extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp); 588655b6f8Swdenk 598655b6f8Swdenk #if defined CONFIG_MPC823 608655b6f8Swdenk /* 618655b6f8Swdenk * LCD controller stucture for MPC823 CPU 628655b6f8Swdenk */ 638655b6f8Swdenk typedef struct vidinfo { 648655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 658655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 668655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 678655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 688655b6f8Swdenk 698655b6f8Swdenk /* LCD configuration register */ 708655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 718655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 728655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 738655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 748655b6f8Swdenk u_char vl_dp; /* Data polarity */ 758655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 768655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 778655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 788655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 798655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 808655b6f8Swdenk 818655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 828655b6f8Swdenk ushort vl_wbl; /* Wait between lines */ 838655b6f8Swdenk 848655b6f8Swdenk /* Vertical control register */ 858655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 868655b6f8Swdenk u_char vl_lcdac; /* LCD AC timing */ 878655b6f8Swdenk u_char vl_wbf; /* Wait between frames */ 888655b6f8Swdenk } vidinfo_t; 898655b6f8Swdenk 90abc20abaSMarek Vasut #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ 91abc20abaSMarek Vasut defined CONFIG_CPU_MONAHANS 928655b6f8Swdenk /* 938655b6f8Swdenk * PXA LCD DMA descriptor 948655b6f8Swdenk */ 958655b6f8Swdenk struct pxafb_dma_descriptor { 968655b6f8Swdenk u_long fdadr; /* Frame descriptor address register */ 978655b6f8Swdenk u_long fsadr; /* Frame source address register */ 988655b6f8Swdenk u_long fidr; /* Frame ID register */ 998655b6f8Swdenk u_long ldcmd; /* Command register */ 1008655b6f8Swdenk }; 1018655b6f8Swdenk 1028655b6f8Swdenk /* 1038655b6f8Swdenk * PXA LCD info 1048655b6f8Swdenk */ 1058655b6f8Swdenk struct pxafb_info { 1068655b6f8Swdenk 1078655b6f8Swdenk /* Misc registers */ 1088655b6f8Swdenk u_long reg_lccr3; 1098655b6f8Swdenk u_long reg_lccr2; 1108655b6f8Swdenk u_long reg_lccr1; 1118655b6f8Swdenk u_long reg_lccr0; 1128655b6f8Swdenk u_long fdadr0; 1138655b6f8Swdenk u_long fdadr1; 1148655b6f8Swdenk 1158655b6f8Swdenk /* DMA descriptors */ 1168655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fblow; 1178655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_fbhigh; 1188655b6f8Swdenk struct pxafb_dma_descriptor * dmadesc_palette; 1198655b6f8Swdenk 1208655b6f8Swdenk u_long screen; /* physical address of frame buffer */ 1218655b6f8Swdenk u_long palette; /* physical address of palette memory */ 1228655b6f8Swdenk u_int palette_size; 1238655b6f8Swdenk }; 1248655b6f8Swdenk 1258655b6f8Swdenk /* 1268655b6f8Swdenk * LCD controller stucture for PXA CPU 1278655b6f8Swdenk */ 1288655b6f8Swdenk typedef struct vidinfo { 1298655b6f8Swdenk ushort vl_col; /* Number of columns (i.e. 640) */ 1308655b6f8Swdenk ushort vl_row; /* Number of rows (i.e. 480) */ 1318655b6f8Swdenk ushort vl_width; /* Width of display area in millimeters */ 1328655b6f8Swdenk ushort vl_height; /* Height of display area in millimeters */ 1338655b6f8Swdenk 1348655b6f8Swdenk /* LCD configuration register */ 1358655b6f8Swdenk u_char vl_clkp; /* Clock polarity */ 1368655b6f8Swdenk u_char vl_oep; /* Output Enable polarity */ 1378655b6f8Swdenk u_char vl_hsp; /* Horizontal Sync polarity */ 1388655b6f8Swdenk u_char vl_vsp; /* Vertical Sync polarity */ 1398655b6f8Swdenk u_char vl_dp; /* Data polarity */ 1408655b6f8Swdenk u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 1418655b6f8Swdenk u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 1428655b6f8Swdenk u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ 1438655b6f8Swdenk u_char vl_clor; /* Color, 0 = mono, 1 = color */ 1448655b6f8Swdenk u_char vl_tft; /* 0 = passive, 1 = TFT */ 1458655b6f8Swdenk 1468655b6f8Swdenk /* Horizontal control register. Timing from data sheet */ 1478655b6f8Swdenk ushort vl_hpw; /* Horz sync pulse width */ 1488655b6f8Swdenk u_char vl_blw; /* Wait before of line */ 1498655b6f8Swdenk u_char vl_elw; /* Wait end of line */ 1508655b6f8Swdenk 1518655b6f8Swdenk /* Vertical control register. */ 1528655b6f8Swdenk u_char vl_vpw; /* Vertical sync pulse width */ 1538655b6f8Swdenk u_char vl_bfw; /* Wait before of frame */ 1548655b6f8Swdenk u_char vl_efw; /* Wait end of frame */ 1558655b6f8Swdenk 1568655b6f8Swdenk /* PXA LCD controller params */ 1578655b6f8Swdenk struct pxafb_info pxa; 1588655b6f8Swdenk } vidinfo_t; 1598655b6f8Swdenk 16039cf4804SStelian Pop #elif defined(CONFIG_ATMEL_LCD) 16139cf4804SStelian Pop 16239cf4804SStelian Pop typedef struct vidinfo { 16378459123SMarek Vasut ushort vl_col; /* Number of columns (i.e. 640) */ 16478459123SMarek Vasut ushort vl_row; /* Number of rows (i.e. 480) */ 16539cf4804SStelian Pop u_long vl_clk; /* pixel clock in ps */ 16639cf4804SStelian Pop 16739cf4804SStelian Pop /* LCD configuration register */ 16839cf4804SStelian Pop u_long vl_sync; /* Horizontal / vertical sync */ 16939cf4804SStelian Pop u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 17039cf4804SStelian Pop u_long vl_tft; /* 0 = passive, 1 = TFT */ 171cdfcedbfSAlexander Stein u_long vl_cont_pol_low; /* contrast polarity is low */ 17239cf4804SStelian Pop 17339cf4804SStelian Pop /* Horizontal control register. */ 17439cf4804SStelian Pop u_long vl_hsync_len; /* Length of horizontal sync */ 17539cf4804SStelian Pop u_long vl_left_margin; /* Time from sync to picture */ 17639cf4804SStelian Pop u_long vl_right_margin; /* Time from picture to sync */ 17739cf4804SStelian Pop 17839cf4804SStelian Pop /* Vertical control register. */ 17939cf4804SStelian Pop u_long vl_vsync_len; /* Length of vertical sync */ 18039cf4804SStelian Pop u_long vl_upper_margin; /* Time from sync to picture */ 18139cf4804SStelian Pop u_long vl_lower_margin; /* Time from picture to sync */ 18239cf4804SStelian Pop 18339cf4804SStelian Pop u_long mmio; /* Memory mapped registers */ 18439cf4804SStelian Pop } vidinfo_t; 18539cf4804SStelian Pop 186*559a05ccSDonghwa Lee #elif defined(CONFIG_EXYNOS_FB) 187*559a05ccSDonghwa Lee 188*559a05ccSDonghwa Lee enum { 189*559a05ccSDonghwa Lee FIMD_RGB_INTERFACE = 1, 190*559a05ccSDonghwa Lee FIMD_CPU_INTERFACE = 2, 191*559a05ccSDonghwa Lee }; 192*559a05ccSDonghwa Lee 193*559a05ccSDonghwa Lee typedef struct vidinfo { 194*559a05ccSDonghwa Lee ushort vl_col; /* Number of columns (i.e. 640) */ 195*559a05ccSDonghwa Lee ushort vl_row; /* Number of rows (i.e. 480) */ 196*559a05ccSDonghwa Lee ushort vl_width; /* Width of display area in millimeters */ 197*559a05ccSDonghwa Lee ushort vl_height; /* Height of display area in millimeters */ 198*559a05ccSDonghwa Lee 199*559a05ccSDonghwa Lee /* LCD configuration register */ 200*559a05ccSDonghwa Lee u_char vl_freq; /* Frequency */ 201*559a05ccSDonghwa Lee u_char vl_clkp; /* Clock polarity */ 202*559a05ccSDonghwa Lee u_char vl_oep; /* Output Enable polarity */ 203*559a05ccSDonghwa Lee u_char vl_hsp; /* Horizontal Sync polarity */ 204*559a05ccSDonghwa Lee u_char vl_vsp; /* Vertical Sync polarity */ 205*559a05ccSDonghwa Lee u_char vl_dp; /* Data polarity */ 206*559a05ccSDonghwa Lee u_char vl_bpix; /* Bits per pixel */ 207*559a05ccSDonghwa Lee 208*559a05ccSDonghwa Lee /* Horizontal control register. Timing from data sheet */ 209*559a05ccSDonghwa Lee u_char vl_hspw; /* Horz sync pulse width */ 210*559a05ccSDonghwa Lee u_char vl_hfpd; /* Wait before of line */ 211*559a05ccSDonghwa Lee u_char vl_hbpd; /* Wait end of line */ 212*559a05ccSDonghwa Lee 213*559a05ccSDonghwa Lee /* Vertical control register. */ 214*559a05ccSDonghwa Lee u_char vl_vspw; /* Vertical sync pulse width */ 215*559a05ccSDonghwa Lee u_char vl_vfpd; /* Wait before of frame */ 216*559a05ccSDonghwa Lee u_char vl_vbpd; /* Wait end of frame */ 217*559a05ccSDonghwa Lee u_char vl_cmd_allow_len; /* Wait end of frame */ 218*559a05ccSDonghwa Lee 219*559a05ccSDonghwa Lee void (*cfg_gpio)(void); 220*559a05ccSDonghwa Lee void (*backlight_on)(unsigned int onoff); 221*559a05ccSDonghwa Lee void (*reset_lcd)(void); 222*559a05ccSDonghwa Lee void (*lcd_power_on)(void); 223*559a05ccSDonghwa Lee void (*cfg_ldo)(void); 224*559a05ccSDonghwa Lee void (*enable_ldo)(unsigned int onoff); 225*559a05ccSDonghwa Lee void (*mipi_power)(void); 226*559a05ccSDonghwa Lee void (*backlight_reset)(void); 227*559a05ccSDonghwa Lee 228*559a05ccSDonghwa Lee unsigned int win_id; 229*559a05ccSDonghwa Lee unsigned int init_delay; 230*559a05ccSDonghwa Lee unsigned int power_on_delay; 231*559a05ccSDonghwa Lee unsigned int reset_delay; 232*559a05ccSDonghwa Lee unsigned int interface_mode; 233*559a05ccSDonghwa Lee unsigned int mipi_enabled; 234*559a05ccSDonghwa Lee unsigned int cs_setup; 235*559a05ccSDonghwa Lee unsigned int wr_setup; 236*559a05ccSDonghwa Lee unsigned int wr_act; 237*559a05ccSDonghwa Lee unsigned int wr_hold; 238*559a05ccSDonghwa Lee 239*559a05ccSDonghwa Lee /* parent clock name(MPLL, EPLL or VPLL) */ 240*559a05ccSDonghwa Lee unsigned int pclk_name; 241*559a05ccSDonghwa Lee /* ratio value for source clock from parent clock. */ 242*559a05ccSDonghwa Lee unsigned int sclk_div; 243*559a05ccSDonghwa Lee 244*559a05ccSDonghwa Lee unsigned int dual_lcd_enabled; 245*559a05ccSDonghwa Lee 246*559a05ccSDonghwa Lee } vidinfo_t; 247*559a05ccSDonghwa Lee 248*559a05ccSDonghwa Lee void init_panel_info(vidinfo_t *vid); 249*559a05ccSDonghwa Lee 250b245e65eSGuennadi Liakhovetski #else 251b245e65eSGuennadi Liakhovetski 252b245e65eSGuennadi Liakhovetski typedef struct vidinfo { 253b245e65eSGuennadi Liakhovetski ushort vl_col; /* Number of columns (i.e. 160) */ 254b245e65eSGuennadi Liakhovetski ushort vl_row; /* Number of rows (i.e. 100) */ 255b245e65eSGuennadi Liakhovetski 256b245e65eSGuennadi Liakhovetski u_char vl_bpix; /* Bits per pixel, 0 = 1 */ 257b245e65eSGuennadi Liakhovetski 258b245e65eSGuennadi Liakhovetski ushort *cmap; /* Pointer to the colormap */ 259b245e65eSGuennadi Liakhovetski 260b245e65eSGuennadi Liakhovetski void *priv; /* Pointer to driver-specific data */ 261b245e65eSGuennadi Liakhovetski } vidinfo_t; 262b245e65eSGuennadi Liakhovetski 263abc20abaSMarek Vasut #endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ 2648655b6f8Swdenk 26560e97419SAlessandro Rubini extern vidinfo_t panel_info; 26660e97419SAlessandro Rubini 2678655b6f8Swdenk /* Video functions */ 2688655b6f8Swdenk 269682011ffSwdenk #if defined(CONFIG_RBC823) 270682011ffSwdenk void lcd_disable (void); 271682011ffSwdenk #endif 272682011ffSwdenk 273fe8c2806Swdenk 274c3f4d17eSwdenk /* int lcd_init (void *lcdbase); */ 275fe8c2806Swdenk void lcd_putc (const char c); 276fe8c2806Swdenk void lcd_puts (const char *s); 277fe8c2806Swdenk void lcd_printf (const char *fmt, ...); 27802110903SChe-Liang Chiou void lcd_clear(void); 27902110903SChe-Liang Chiou int lcd_display_bitmap(ulong bmp_image, int x, int y); 280fe8c2806Swdenk 2816b59e03eSHaavard Skinnemoen /* Allow boards to customize the information displayed */ 2826b59e03eSHaavard Skinnemoen void lcd_show_board_info(void); 2838655b6f8Swdenk 2848655b6f8Swdenk /************************************************************************/ 2858655b6f8Swdenk /* ** BITMAP DISPLAY SUPPORT */ 2868655b6f8Swdenk /************************************************************************/ 287639221c7SJon Loeliger #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) 2888655b6f8Swdenk # include <bmp_layout.h> 2898655b6f8Swdenk # include <asm/byteorder.h> 290639221c7SJon Loeliger #endif 2918655b6f8Swdenk 2928655b6f8Swdenk /* 2938655b6f8Swdenk * Information about displays we are using. This is for configuring 2948655b6f8Swdenk * the LCD controller and memory allocation. Someone has to know what 2958655b6f8Swdenk * is connected, as we can't autodetect anything. 2968655b6f8Swdenk */ 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HIGH 0 /* Pins are active high */ 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOW 1 /* Pins are active low */ 2998655b6f8Swdenk 3008655b6f8Swdenk #define LCD_MONOCHROME 0 3018655b6f8Swdenk #define LCD_COLOR2 1 3028655b6f8Swdenk #define LCD_COLOR4 2 3038655b6f8Swdenk #define LCD_COLOR8 3 3048655b6f8Swdenk #define LCD_COLOR16 4 3058655b6f8Swdenk 3068655b6f8Swdenk /*----------------------------------------------------------------------*/ 30788804d19Swdenk #if defined(CONFIG_LCD_INFO_BELOW_LOGO) 3088655b6f8Swdenk # define LCD_INFO_X 0 3098655b6f8Swdenk # define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) 3108655b6f8Swdenk #elif defined(CONFIG_LCD_LOGO) 3118655b6f8Swdenk # define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) 3128655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 3138655b6f8Swdenk #else 3148655b6f8Swdenk # define LCD_INFO_X (VIDEO_FONT_WIDTH) 3158655b6f8Swdenk # define LCD_INFO_Y (VIDEO_FONT_HEIGHT) 3168655b6f8Swdenk #endif 3178655b6f8Swdenk 3188655b6f8Swdenk /* Default to 8bpp if bit depth not specified */ 3198655b6f8Swdenk #ifndef LCD_BPP 3208655b6f8Swdenk # define LCD_BPP LCD_COLOR8 3218655b6f8Swdenk #endif 3228655b6f8Swdenk #ifndef LCD_DF 3238655b6f8Swdenk # define LCD_DF 1 3248655b6f8Swdenk #endif 3258655b6f8Swdenk 3268655b6f8Swdenk /* Calculate nr. of bits per pixel and nr. of colors */ 3278655b6f8Swdenk #define NBITS(bit_code) (1 << (bit_code)) 3288655b6f8Swdenk #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 3298655b6f8Swdenk 3308655b6f8Swdenk /************************************************************************/ 3318655b6f8Swdenk /* ** CONSOLE CONSTANTS */ 3328655b6f8Swdenk /************************************************************************/ 3338655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 3348655b6f8Swdenk 3358655b6f8Swdenk /* 3368655b6f8Swdenk * Simple black/white definitions 3378655b6f8Swdenk */ 3388655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 3398655b6f8Swdenk # define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ 3408655b6f8Swdenk 3418655b6f8Swdenk #elif LCD_BPP == LCD_COLOR8 3428655b6f8Swdenk 3438655b6f8Swdenk /* 3448655b6f8Swdenk * 8bpp color definitions 3458655b6f8Swdenk */ 3468655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0 3478655b6f8Swdenk # define CONSOLE_COLOR_RED 1 3488655b6f8Swdenk # define CONSOLE_COLOR_GREEN 2 3498655b6f8Swdenk # define CONSOLE_COLOR_YELLOW 3 3508655b6f8Swdenk # define CONSOLE_COLOR_BLUE 4 3518655b6f8Swdenk # define CONSOLE_COLOR_MAGENTA 5 3528655b6f8Swdenk # define CONSOLE_COLOR_CYAN 6 3538655b6f8Swdenk # define CONSOLE_COLOR_GREY 14 3548655b6f8Swdenk # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ 3558655b6f8Swdenk 3568655b6f8Swdenk #else 3578655b6f8Swdenk 3588655b6f8Swdenk /* 3598655b6f8Swdenk * 16bpp color definitions 3608655b6f8Swdenk */ 3618655b6f8Swdenk # define CONSOLE_COLOR_BLACK 0x0000 3628655b6f8Swdenk # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ 3638655b6f8Swdenk 3648655b6f8Swdenk #endif /* color definitions */ 3658655b6f8Swdenk 3668655b6f8Swdenk /************************************************************************/ 3678655b6f8Swdenk #ifndef PAGE_SIZE 3688655b6f8Swdenk # define PAGE_SIZE 4096 3698655b6f8Swdenk #endif 3708655b6f8Swdenk 3718655b6f8Swdenk /************************************************************************/ 3728655b6f8Swdenk /* ** CONSOLE DEFINITIONS & FUNCTIONS */ 3738655b6f8Swdenk /************************************************************************/ 37488804d19Swdenk #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) 3758655b6f8Swdenk # define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ 3768655b6f8Swdenk / VIDEO_FONT_HEIGHT) 3778655b6f8Swdenk #else 3788655b6f8Swdenk # define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) 3798655b6f8Swdenk #endif 3808655b6f8Swdenk 3818655b6f8Swdenk #define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) 3828655b6f8Swdenk #define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) 3838655b6f8Swdenk #define CONSOLE_ROW_FIRST (lcd_console_address) 3848655b6f8Swdenk #define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) 3858655b6f8Swdenk #define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ 3868655b6f8Swdenk - CONSOLE_ROW_SIZE) 3878655b6f8Swdenk #define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) 3888655b6f8Swdenk #define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) 3898655b6f8Swdenk 3908655b6f8Swdenk #if LCD_BPP == LCD_MONOCHROME 3918655b6f8Swdenk # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ 3928655b6f8Swdenk (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) 39369f32e6cSMark Jackson #elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) 3948655b6f8Swdenk # define COLOR_MASK(c) (c) 3958655b6f8Swdenk #else 3968655b6f8Swdenk # error Unsupported LCD BPP. 3978655b6f8Swdenk #endif 3988655b6f8Swdenk 3998655b6f8Swdenk /************************************************************************/ 4008655b6f8Swdenk 4018655b6f8Swdenk #endif /* _LCD_H_ */ 402