xref: /rk3399_rockchip-uboot/include/irq-platform.h (revision 8a970f94eb6fb3ab165612e36538b0a7fba1aa07)
14e6670feSJoseph Chen /*
24e6670feSJoseph Chen  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
34e6670feSJoseph Chen  *
44e6670feSJoseph Chen  * SPDX-License-Identifier:     GPL-2.0+
54e6670feSJoseph Chen  */
64e6670feSJoseph Chen 
74e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_
84e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_
94e6670feSJoseph Chen 
10778da45fSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK3128)
11778da45fSJoseph Chen #define GPIO0_PHYS			0x2007C000
12778da45fSJoseph Chen #define GPIO1_PHYS			0x20080000
13778da45fSJoseph Chen #define GPIO2_PHYS			0x20084000
14778da45fSJoseph Chen #define GPIO3_PHYS			0x20088000
15778da45fSJoseph Chen 
16778da45fSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
17778da45fSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
18778da45fSJoseph Chen 
19778da45fSJoseph Chen #define GPIO_BANK_NUM			4
20778da45fSJoseph Chen #define GPIO_BANK_PINS			32
21778da45fSJoseph Chen 
22b073251dSJoseph Chen #define IRQ_USB_OTG			42
236d0f6303SJoseph Chen #define IRQ_TIMER1			61
24778da45fSJoseph Chen #define IRQ_GPIO0			68
25778da45fSJoseph Chen #define IRQ_GPIO1			69
26a1b32c24SJoseph Chen #define IRQ_GPIO2			70
27778da45fSJoseph Chen #define IRQ_GPIO3			71
28778da45fSJoseph Chen 
29778da45fSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK322X)
304e6670feSJoseph Chen #define GPIO0_PHYS			0x11110000
314e6670feSJoseph Chen #define GPIO1_PHYS			0x11120000
324e6670feSJoseph Chen #define GPIO2_PHYS			0x11130000
334e6670feSJoseph Chen #define GPIO3_PHYS			0x11140000
344e6670feSJoseph Chen 
354e6670feSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
364e6670feSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
374e6670feSJoseph Chen 
384e6670feSJoseph Chen #define GPIO_BANK_NUM			4
394e6670feSJoseph Chen #define GPIO_BANK_PINS			32
404e6670feSJoseph Chen 
41b073251dSJoseph Chen #define IRQ_USB_OTG			55
426d0f6303SJoseph Chen #define IRQ_TIMER1			76
43b0deaf68SZhangbin Tong #define IRQ_PWM				82
444e6670feSJoseph Chen #define IRQ_GPIO0			83
454e6670feSJoseph Chen #define IRQ_GPIO1			84
464e6670feSJoseph Chen #define IRQ_GPIO2			85
474e6670feSJoseph Chen #define IRQ_GPIO3			86
484e6670feSJoseph Chen 
494e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288)
504e6670feSJoseph Chen #define GPIO0_PHYS			0xFF750000
514e6670feSJoseph Chen #define GPIO1_PHYS			0xFF780000
524e6670feSJoseph Chen #define GPIO2_PHYS			0xFF790000
534e6670feSJoseph Chen #define GPIO3_PHYS			0xFF7A0000
544e6670feSJoseph Chen #define GPIO4_PHYS			0xFF7B0000
554e6670feSJoseph Chen #define GPIO5_PHYS			0xFF7C0000
564e6670feSJoseph Chen #define GPIO6_PHYS			0xFF7D0000
574e6670feSJoseph Chen #define GPIO7_PHYS			0xFF7E0000
584e6670feSJoseph Chen #define GPIO8_PHYS			0xFF7F0000
594e6670feSJoseph Chen 
604e6670feSJoseph Chen #define GIC_IRQS_NR			(5 * 32)
614e6670feSJoseph Chen #define GPIO_IRQS_NR			(9 * 32)
624e6670feSJoseph Chen 
634e6670feSJoseph Chen #define GPIO_BANK_NUM			9
644e6670feSJoseph Chen #define GPIO_BANK_PINS			32
654e6670feSJoseph Chen 
66b073251dSJoseph Chen #define IRQ_USB_OTG			55
676d0f6303SJoseph Chen #define IRQ_TIMER1			99
68b0deaf68SZhangbin Tong #define IRQ_PWM				110
694e6670feSJoseph Chen #define IRQ_GPIO0			113
704e6670feSJoseph Chen #define IRQ_GPIO1			114
714e6670feSJoseph Chen #define IRQ_GPIO2			115
724e6670feSJoseph Chen #define IRQ_GPIO3			116
734e6670feSJoseph Chen #define IRQ_GPIO4			117
744e6670feSJoseph Chen #define IRQ_GPIO5			118
754e6670feSJoseph Chen #define IRQ_GPIO6			119
764e6670feSJoseph Chen #define IRQ_GPIO7			120
774e6670feSJoseph Chen #define IRQ_GPIO8			121
784e6670feSJoseph Chen 
794e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328)
804e6670feSJoseph Chen #define	GPIO0_PHYS			0xFF210000
814e6670feSJoseph Chen #define	GPIO1_PHYS			0xFF220000
824e6670feSJoseph Chen #define	GPIO2_PHYS			0xFF230000
834e6670feSJoseph Chen #define	GPIO3_PHYS			0xFF240000
844e6670feSJoseph Chen 
854e6670feSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
864e6670feSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
874e6670feSJoseph Chen 
884e6670feSJoseph Chen #define GPIO_BANK_NUM			4
894e6670feSJoseph Chen #define GPIO_BANK_PINS			32
904e6670feSJoseph Chen 
916d0f6303SJoseph Chen #define IRQ_TIMER1			76
92b0deaf68SZhangbin Tong #define IRQ_PWM				82
934e6670feSJoseph Chen #define IRQ_GPIO0			83
944e6670feSJoseph Chen #define IRQ_GPIO1			84
954e6670feSJoseph Chen #define IRQ_GPIO2			85
964e6670feSJoseph Chen #define IRQ_GPIO3			86
974e6670feSJoseph Chen 
984e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368)
994e6670feSJoseph Chen #define GPIO0_PHYS			0xFF750000
1004e6670feSJoseph Chen #define GPIO1_PHYS			0xFF780000
1014e6670feSJoseph Chen #define GPIO2_PHYS			0xFF790000
1024e6670feSJoseph Chen #define GPIO3_PHYS			0xFF7A0000
1034e6670feSJoseph Chen 
1044e6670feSJoseph Chen #define GIC_IRQS_NR                     (5 * 32)
1054e6670feSJoseph Chen #define GPIO_IRQS_NR                    (4 * 32)
1064e6670feSJoseph Chen 
1074e6670feSJoseph Chen #define GPIO_BANK_NUM			4
1084e6670feSJoseph Chen #define GPIO_BANK_PINS			32
1094e6670feSJoseph Chen 
1101380460aSXiaoDong Huang #define IRQ_TIMER0			98
1111380460aSXiaoDong Huang #define IRQ_TIMER1			99
112b0deaf68SZhangbin Tong #define IRQ_PWM				110
1134e6670feSJoseph Chen #define IRQ_GPIO0			113
1144e6670feSJoseph Chen #define IRQ_GPIO1			114
1154e6670feSJoseph Chen #define IRQ_GPIO2			115
1164e6670feSJoseph Chen #define IRQ_GPIO3			116
1174e6670feSJoseph Chen 
1184e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399)
1194e6670feSJoseph Chen #define GPIO0_PHYS			0xFF720000
1204e6670feSJoseph Chen #define GPIO1_PHYS			0xFF730000
1214e6670feSJoseph Chen #define GPIO2_PHYS			0xFF780000
1224e6670feSJoseph Chen #define GPIO3_PHYS			0xFF788000
1234e6670feSJoseph Chen #define GPIO4_PHYS			0xFF790000
1244e6670feSJoseph Chen 
1254e6670feSJoseph Chen #define IRQ_GPIO0			46
1264e6670feSJoseph Chen #define IRQ_GPIO1			47
1274e6670feSJoseph Chen #define IRQ_GPIO2			48
1284e6670feSJoseph Chen #define IRQ_GPIO3			49
1294e6670feSJoseph Chen #define IRQ_GPIO4			50
130b0deaf68SZhangbin Tong #define IRQ_PWM				93
1316d0f6303SJoseph Chen #define IRQ_TIMER1			114	/* non-secure */
1324e6670feSJoseph Chen 
1334e6670feSJoseph Chen #define GIC_IRQS_NR			(6 * 32)
1344e6670feSJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
1354e6670feSJoseph Chen 
1364e6670feSJoseph Chen #define GPIO_BANK_NUM			5
1374e6670feSJoseph Chen #define GPIO_BANK_PINS			32
13860848109SJoseph Chen 
13960848109SJoseph Chen #elif defined(CONFIG_ROCKCHIP_PX30)
14060848109SJoseph Chen #define GPIO0_PHYS			0xff040000
14160848109SJoseph Chen #define GPIO1_PHYS			0xff250000
14260848109SJoseph Chen #define GPIO2_PHYS			0xff260000
14360848109SJoseph Chen #define GPIO3_PHYS			0xff270000
14460848109SJoseph Chen 
14560848109SJoseph Chen #define IRQ_GPIO0			35
14660848109SJoseph Chen #define IRQ_GPIO1			36
14760848109SJoseph Chen #define IRQ_GPIO2			37
14860848109SJoseph Chen #define IRQ_GPIO3			38
14960848109SJoseph Chen #define IRQ_PWM0			56
15060848109SJoseph Chen #define IRQ_PWM1			57
15149f812ddSJoseph Chen #define IRQ_TIMER0			62	/* non-secure */
15260848109SJoseph Chen #define IRQ_TIMER1			63	/* non-secure */
15360848109SJoseph Chen 
15460848109SJoseph Chen #define GIC_IRQS_NR			(4 * 32)
15560848109SJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
15660848109SJoseph Chen 
15760848109SJoseph Chen #define GPIO_BANK_NUM			4
15860848109SJoseph Chen #define GPIO_BANK_PINS			32
15960848109SJoseph Chen 
1600b4bf976SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3308)
1610b4bf976SJoseph Chen #define GPIO0_PHYS			0xff220000
1620b4bf976SJoseph Chen #define GPIO1_PHYS			0xff230000
1630b4bf976SJoseph Chen #define GPIO2_PHYS			0xff240000
1640b4bf976SJoseph Chen #define GPIO3_PHYS			0xff250000
1650b4bf976SJoseph Chen #define GPIO4_PHYS			0xff260000
1660b4bf976SJoseph Chen 
1670b4bf976SJoseph Chen #define IRQ_TIMER1			58	/* ch0 ns timer1 */
1680b4bf976SJoseph Chen #define IRQ_GPIO0			72
1690b4bf976SJoseph Chen #define IRQ_GPIO1			73
1700b4bf976SJoseph Chen #define IRQ_GPIO2			74
1710b4bf976SJoseph Chen #define IRQ_GPIO3			75
1720b4bf976SJoseph Chen #define IRQ_GPIO4			76
1730b4bf976SJoseph Chen 
1740b4bf976SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
1750b4bf976SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
1760b4bf976SJoseph Chen 
1770b4bf976SJoseph Chen #define GPIO_BANK_NUM			5
1780b4bf976SJoseph Chen #define GPIO_BANK_PINS			32
17947ad8107SJoseph Chen 
18047ad8107SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK1808)
18147ad8107SJoseph Chen #define GPIO0_PHYS			0xff4c0000
18247ad8107SJoseph Chen #define GPIO1_PHYS			0xff690000
18347ad8107SJoseph Chen #define GPIO2_PHYS			0xff6a0000
18447ad8107SJoseph Chen #define GPIO3_PHYS			0xff6b0000
18547ad8107SJoseph Chen #define GPIO4_PHYS			0xff6c0000
18647ad8107SJoseph Chen 
18747ad8107SJoseph Chen #define IRQ_GPIO0			35
18847ad8107SJoseph Chen #define IRQ_GPIO1			36
18947ad8107SJoseph Chen #define IRQ_GPIO2			37
19047ad8107SJoseph Chen #define IRQ_GPIO3			38
19147ad8107SJoseph Chen #define IRQ_GPIO4			114
19247ad8107SJoseph Chen 
19347ad8107SJoseph Chen #define IRQ_TIMER0			58
19447ad8107SJoseph Chen #define IRQ_TIMER1			59
19547ad8107SJoseph Chen 
19647ad8107SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
19747ad8107SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
19847ad8107SJoseph Chen 
19947ad8107SJoseph Chen #define GPIO_BANK_NUM			5
20047ad8107SJoseph Chen #define GPIO_BANK_PINS			32
20147ad8107SJoseph Chen 
202c928344eSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RV1106)
203c928344eSJoseph Chen #define GPIO0_PHYS			0xff460000
204c928344eSJoseph Chen #define GPIO1_PHYS			0xff620000
205c928344eSJoseph Chen #define GPIO2_PHYS			0xff630000
206c928344eSJoseph Chen #define GPIO3_PHYS			0xff640000
207c928344eSJoseph Chen #define GPIO4_PHYS			0xff650000
208c928344eSJoseph Chen 
209c928344eSJoseph Chen #define GIC_IRQS_NR			(5 * 32)
210c928344eSJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
211c928344eSJoseph Chen 
212c928344eSJoseph Chen #define GPIO_BANK_NUM			5
213c928344eSJoseph Chen #define GPIO_BANK_PINS			32
214c928344eSJoseph Chen 
215c928344eSJoseph Chen #define IRQ_USB_OTG			117
216c928344eSJoseph Chen #define IRQ_TIMER1			57
217c928344eSJoseph Chen #define IRQ_GPIO0			66
218c928344eSJoseph Chen #define IRQ_GPIO1			67
219c928344eSJoseph Chen #define IRQ_GPIO2			68
220c928344eSJoseph Chen #define IRQ_GPIO3			69
221c928344eSJoseph Chen #define IRQ_GPIO4			70
222c928344eSJoseph Chen 
223066e9bcbSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RV1126)
224066e9bcbSJoseph Chen #define GPIO0_PHYS			0xff460000
225066e9bcbSJoseph Chen #define GPIO1_PHYS			0xff620000
226066e9bcbSJoseph Chen #define GPIO2_PHYS			0xff630000
227066e9bcbSJoseph Chen #define GPIO3_PHYS			0xff640000
228066e9bcbSJoseph Chen #define GPIO4_PHYS			0xff650000
229066e9bcbSJoseph Chen 
230066e9bcbSJoseph Chen #define GIC_IRQS_NR			(5 * 32)
231066e9bcbSJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
232066e9bcbSJoseph Chen 
233066e9bcbSJoseph Chen #define GPIO_BANK_NUM			5
234066e9bcbSJoseph Chen #define GPIO_BANK_PINS			32
235066e9bcbSJoseph Chen 
236066e9bcbSJoseph Chen #define IRQ_USB_OTG			117
237066e9bcbSJoseph Chen #define IRQ_TIMER1			57
238066e9bcbSJoseph Chen #define IRQ_GPIO0			66
239066e9bcbSJoseph Chen #define IRQ_GPIO1			67
240066e9bcbSJoseph Chen #define IRQ_GPIO2			68
241066e9bcbSJoseph Chen #define IRQ_GPIO3			69
242066e9bcbSJoseph Chen #define IRQ_GPIO4			70
243066e9bcbSJoseph Chen 
244c6f7c1a3SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3528)
245c6f7c1a3SJoseph Chen #define GPIO0_PHYS			0xff610000
246c6f7c1a3SJoseph Chen #define GPIO1_PHYS			0xffaf0000
247c6f7c1a3SJoseph Chen #define GPIO2_PHYS			0xffb00000
248c6f7c1a3SJoseph Chen #define GPIO3_PHYS			0xffb10000
249c6f7c1a3SJoseph Chen #define GPIO4_PHYS			0xffb20000
250c6f7c1a3SJoseph Chen 
251c6f7c1a3SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
252c6f7c1a3SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
253c6f7c1a3SJoseph Chen 
254c6f7c1a3SJoseph Chen #define GPIO_BANK_NUM			5
255c6f7c1a3SJoseph Chen #define GPIO_BANK_PINS			32
256c6f7c1a3SJoseph Chen 
257c6f7c1a3SJoseph Chen #define IRQ_TIMER0			63
258c6f7c1a3SJoseph Chen #define IRQ_GPIO0			103
259c6f7c1a3SJoseph Chen #define IRQ_GPIO1			105
260c6f7c1a3SJoseph Chen #define IRQ_GPIO2			107
261c6f7c1a3SJoseph Chen #define IRQ_GPIO3			108
262c6f7c1a3SJoseph Chen #define IRQ_GPIO4			110
263c6f7c1a3SJoseph Chen 
26456f7d184SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3562)
26556f7d184SJoseph Chen #define GPIO0_PHYS			0xff260000
26656f7d184SJoseph Chen #define GPIO1_PHYS			0xff620000
26756f7d184SJoseph Chen #define GPIO2_PHYS			0xff630000
26856f7d184SJoseph Chen #define GPIO3_PHYS			0xffac0000
26956f7d184SJoseph Chen #define GPIO4_PHYS			0xffad0000
27056f7d184SJoseph Chen 
27156f7d184SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
27256f7d184SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
27356f7d184SJoseph Chen 
27456f7d184SJoseph Chen #define GPIO_BANK_NUM			5
27556f7d184SJoseph Chen #define GPIO_BANK_PINS			32
27656f7d184SJoseph Chen 
27756f7d184SJoseph Chen #define IRQ_TIMER0			77
27856f7d184SJoseph Chen #define IRQ_GPIO0			32
27956f7d184SJoseph Chen #define IRQ_GPIO1			34
28056f7d184SJoseph Chen #define IRQ_GPIO2			36
28156f7d184SJoseph Chen #define IRQ_GPIO3			38
28256f7d184SJoseph Chen #define IRQ_GPIO4			40
28356f7d184SJoseph Chen 
2845033f049SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3568)
2855033f049SJoseph Chen #define GPIO0_PHYS			0xfdd60000
2865033f049SJoseph Chen #define GPIO1_PHYS			0xfe740000
2875033f049SJoseph Chen #define GPIO2_PHYS			0xfe750000
2885033f049SJoseph Chen #define GPIO3_PHYS			0xfe760000
2895033f049SJoseph Chen #define GPIO4_PHYS			0xfe770000
2905033f049SJoseph Chen 
2915033f049SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
2925033f049SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
2935033f049SJoseph Chen 
2945033f049SJoseph Chen #define GPIO_BANK_NUM			5
2955033f049SJoseph Chen #define GPIO_BANK_PINS			32
2965033f049SJoseph Chen 
2975033f049SJoseph Chen #define IRQ_TIMER0			141
2985033f049SJoseph Chen #define IRQ_GPIO0			65
2995033f049SJoseph Chen #define IRQ_GPIO1			66
3005033f049SJoseph Chen #define IRQ_GPIO2			67
3015033f049SJoseph Chen #define IRQ_GPIO3			68
3025033f049SJoseph Chen #define IRQ_GPIO4			69
3035033f049SJoseph Chen 
304bf72c9c9SXuhui Lin #elif defined(CONFIG_ROCKCHIP_RK3576)
305bf72c9c9SXuhui Lin #define GPIO0_PHYS			0x27320000
306bf72c9c9SXuhui Lin #define GPIO1_PHYS			0x2ae10000
307bf72c9c9SXuhui Lin #define GPIO2_PHYS			0x2ae20000
308bf72c9c9SXuhui Lin #define GPIO3_PHYS			0x2ae30000
309bf72c9c9SXuhui Lin #define GPIO4_PHYS			0x2ae40000
310bf72c9c9SXuhui Lin 
311*8a970f94SXuhui Lin #define GIC_IRQS_NR			(420)
312bf72c9c9SXuhui Lin #define GPIO_IRQS_NR			(5 * 32)
313bf72c9c9SXuhui Lin 
314bf72c9c9SXuhui Lin #define GPIO_BANK_NUM			5
315bf72c9c9SXuhui Lin #define GPIO_BANK_PINS			32
316bf72c9c9SXuhui Lin 
317bf72c9c9SXuhui Lin #define IRQ_TIMER0			77
318bf72c9c9SXuhui Lin 
319bf72c9c9SXuhui Lin #define IRQ_GPIO0			IRQ_GPIO0_0
320bf72c9c9SXuhui Lin #define IRQ_GPIO0_0			185
321bf72c9c9SXuhui Lin #define IRQ_GPIO0_1			186
322bf72c9c9SXuhui Lin #define IRQ_GPIO0_2			187
323bf72c9c9SXuhui Lin #define IRQ_GPIO0_3			188
324bf72c9c9SXuhui Lin 
325bf72c9c9SXuhui Lin #define IRQ_GPIO1			IRQ_GPIO1_0
326bf72c9c9SXuhui Lin #define IRQ_GPIO1_0			189
327bf72c9c9SXuhui Lin #define IRQ_GPIO1_1			190
328bf72c9c9SXuhui Lin #define IRQ_GPIO1_2			191
329bf72c9c9SXuhui Lin #define IRQ_GPIO1_3			192
330bf72c9c9SXuhui Lin 
331bf72c9c9SXuhui Lin #define IRQ_GPIO2			IRQ_GPIO2_0
332bf72c9c9SXuhui Lin #define IRQ_GPIO2_0			193
333bf72c9c9SXuhui Lin #define IRQ_GPIO2_1			194
334bf72c9c9SXuhui Lin #define IRQ_GPIO2_2			195
335bf72c9c9SXuhui Lin #define IRQ_GPIO2_3			196
336bf72c9c9SXuhui Lin 
337bf72c9c9SXuhui Lin #define IRQ_GPIO3			IRQ_GPIO3_0
338bf72c9c9SXuhui Lin #define IRQ_GPIO3_0			197
339bf72c9c9SXuhui Lin #define IRQ_GPIO3_1			198
340bf72c9c9SXuhui Lin #define IRQ_GPIO3_2			199
341bf72c9c9SXuhui Lin #define IRQ_GPIO3_3			200
342bf72c9c9SXuhui Lin 
343bf72c9c9SXuhui Lin #define IRQ_GPIO4			IRQ_GPIO4_0
344bf72c9c9SXuhui Lin #define IRQ_GPIO4_0			201
345bf72c9c9SXuhui Lin #define IRQ_GPIO4_1			202
346bf72c9c9SXuhui Lin #define IRQ_GPIO4_2			203
347bf72c9c9SXuhui Lin #define IRQ_GPIO4_3			204
348bf72c9c9SXuhui Lin 
349c20dcaebSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3588)
350c20dcaebSJoseph Chen #define GPIO0_PHYS			0xfd8a0000
351c20dcaebSJoseph Chen #define GPIO1_PHYS			0xfec20000
352c20dcaebSJoseph Chen #define GPIO2_PHYS			0xfec30000
353c20dcaebSJoseph Chen #define GPIO3_PHYS			0xfec40000
354c20dcaebSJoseph Chen #define GPIO4_PHYS			0xfec50000
355c20dcaebSJoseph Chen 
356c20dcaebSJoseph Chen #define GIC_IRQS_NR			(455)
357c20dcaebSJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
358c20dcaebSJoseph Chen 
359c20dcaebSJoseph Chen #define GPIO_BANK_NUM			5
360c20dcaebSJoseph Chen #define GPIO_BANK_PINS			32
361c20dcaebSJoseph Chen 
362c20dcaebSJoseph Chen #define IRQ_TIMER0			321
363c20dcaebSJoseph Chen #define IRQ_GPIO0			309
364c20dcaebSJoseph Chen #define IRQ_GPIO1			310
365c20dcaebSJoseph Chen #define IRQ_GPIO2			311
366c20dcaebSJoseph Chen #define IRQ_GPIO3			312
367c20dcaebSJoseph Chen #define IRQ_GPIO4			313
3684e6670feSJoseph Chen #else
3694e6670feSJoseph Chen "Missing define RIQ relative things"
3704e6670feSJoseph Chen #endif
3714e6670feSJoseph Chen 
3724e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */
373