14e6670feSJoseph Chen /* 24e6670feSJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 34e6670feSJoseph Chen * 44e6670feSJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 54e6670feSJoseph Chen */ 64e6670feSJoseph Chen 74e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_ 84e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_ 94e6670feSJoseph Chen 10778da45fSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK3128) 11778da45fSJoseph Chen #define GPIO0_PHYS 0x2007C000 12778da45fSJoseph Chen #define GPIO1_PHYS 0x20080000 13778da45fSJoseph Chen #define GPIO2_PHYS 0x20084000 14778da45fSJoseph Chen #define GPIO3_PHYS 0x20088000 15778da45fSJoseph Chen 16778da45fSJoseph Chen #define GIC_IRQS_NR (4 * 32) 17778da45fSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 18778da45fSJoseph Chen 19778da45fSJoseph Chen #define GPIO_BANK_NUM 4 20778da45fSJoseph Chen #define GPIO_BANK_PINS 32 21778da45fSJoseph Chen 22b073251dSJoseph Chen #define IRQ_USB_OTG 42 236d0f6303SJoseph Chen #define IRQ_TIMER1 61 24778da45fSJoseph Chen #define IRQ_GPIO0 68 25778da45fSJoseph Chen #define IRQ_GPIO1 69 26a1b32c24SJoseph Chen #define IRQ_GPIO2 70 27778da45fSJoseph Chen #define IRQ_GPIO3 71 28778da45fSJoseph Chen 29778da45fSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK322X) 304e6670feSJoseph Chen #define GPIO0_PHYS 0x11110000 314e6670feSJoseph Chen #define GPIO1_PHYS 0x11120000 324e6670feSJoseph Chen #define GPIO2_PHYS 0x11130000 334e6670feSJoseph Chen #define GPIO3_PHYS 0x11140000 344e6670feSJoseph Chen 354e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 364e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 374e6670feSJoseph Chen 384e6670feSJoseph Chen #define GPIO_BANK_NUM 4 394e6670feSJoseph Chen #define GPIO_BANK_PINS 32 404e6670feSJoseph Chen 41b073251dSJoseph Chen #define IRQ_USB_OTG 55 426d0f6303SJoseph Chen #define IRQ_TIMER1 76 43b0deaf68SZhangbin Tong #define IRQ_PWM 82 444e6670feSJoseph Chen #define IRQ_GPIO0 83 454e6670feSJoseph Chen #define IRQ_GPIO1 84 464e6670feSJoseph Chen #define IRQ_GPIO2 85 474e6670feSJoseph Chen #define IRQ_GPIO3 86 484e6670feSJoseph Chen 494e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288) 504e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 514e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 524e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 534e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 544e6670feSJoseph Chen #define GPIO4_PHYS 0xFF7B0000 554e6670feSJoseph Chen #define GPIO5_PHYS 0xFF7C0000 564e6670feSJoseph Chen #define GPIO6_PHYS 0xFF7D0000 574e6670feSJoseph Chen #define GPIO7_PHYS 0xFF7E0000 584e6670feSJoseph Chen #define GPIO8_PHYS 0xFF7F0000 594e6670feSJoseph Chen 604e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 614e6670feSJoseph Chen #define GPIO_IRQS_NR (9 * 32) 624e6670feSJoseph Chen 634e6670feSJoseph Chen #define GPIO_BANK_NUM 9 644e6670feSJoseph Chen #define GPIO_BANK_PINS 32 654e6670feSJoseph Chen 66b073251dSJoseph Chen #define IRQ_USB_OTG 55 676d0f6303SJoseph Chen #define IRQ_TIMER1 99 68b0deaf68SZhangbin Tong #define IRQ_PWM 110 694e6670feSJoseph Chen #define IRQ_GPIO0 113 704e6670feSJoseph Chen #define IRQ_GPIO1 114 714e6670feSJoseph Chen #define IRQ_GPIO2 115 724e6670feSJoseph Chen #define IRQ_GPIO3 116 734e6670feSJoseph Chen #define IRQ_GPIO4 117 744e6670feSJoseph Chen #define IRQ_GPIO5 118 754e6670feSJoseph Chen #define IRQ_GPIO6 119 764e6670feSJoseph Chen #define IRQ_GPIO7 120 774e6670feSJoseph Chen #define IRQ_GPIO8 121 784e6670feSJoseph Chen 794e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328) 804e6670feSJoseph Chen #define GPIO0_PHYS 0xFF210000 814e6670feSJoseph Chen #define GPIO1_PHYS 0xFF220000 824e6670feSJoseph Chen #define GPIO2_PHYS 0xFF230000 834e6670feSJoseph Chen #define GPIO3_PHYS 0xFF240000 844e6670feSJoseph Chen 854e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 864e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 874e6670feSJoseph Chen 884e6670feSJoseph Chen #define GPIO_BANK_NUM 4 894e6670feSJoseph Chen #define GPIO_BANK_PINS 32 904e6670feSJoseph Chen 916d0f6303SJoseph Chen #define IRQ_TIMER1 76 92b0deaf68SZhangbin Tong #define IRQ_PWM 82 934e6670feSJoseph Chen #define IRQ_GPIO0 83 944e6670feSJoseph Chen #define IRQ_GPIO1 84 954e6670feSJoseph Chen #define IRQ_GPIO2 85 964e6670feSJoseph Chen #define IRQ_GPIO3 86 974e6670feSJoseph Chen 984e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368) 994e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 1004e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 1014e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 1024e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 1034e6670feSJoseph Chen 1044e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 1054e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 1064e6670feSJoseph Chen 1074e6670feSJoseph Chen #define GPIO_BANK_NUM 4 1084e6670feSJoseph Chen #define GPIO_BANK_PINS 32 1094e6670feSJoseph Chen 1101380460aSXiaoDong Huang #define IRQ_TIMER0 98 1111380460aSXiaoDong Huang #define IRQ_TIMER1 99 112b0deaf68SZhangbin Tong #define IRQ_PWM 110 1134e6670feSJoseph Chen #define IRQ_GPIO0 113 1144e6670feSJoseph Chen #define IRQ_GPIO1 114 1154e6670feSJoseph Chen #define IRQ_GPIO2 115 1164e6670feSJoseph Chen #define IRQ_GPIO3 116 1174e6670feSJoseph Chen 1184e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399) 1194e6670feSJoseph Chen #define GPIO0_PHYS 0xFF720000 1204e6670feSJoseph Chen #define GPIO1_PHYS 0xFF730000 1214e6670feSJoseph Chen #define GPIO2_PHYS 0xFF780000 1224e6670feSJoseph Chen #define GPIO3_PHYS 0xFF788000 1234e6670feSJoseph Chen #define GPIO4_PHYS 0xFF790000 1244e6670feSJoseph Chen 1254e6670feSJoseph Chen #define IRQ_GPIO0 46 1264e6670feSJoseph Chen #define IRQ_GPIO1 47 1274e6670feSJoseph Chen #define IRQ_GPIO2 48 1284e6670feSJoseph Chen #define IRQ_GPIO3 49 1294e6670feSJoseph Chen #define IRQ_GPIO4 50 130b0deaf68SZhangbin Tong #define IRQ_PWM 93 1316d0f6303SJoseph Chen #define IRQ_TIMER1 114 /* non-secure */ 1324e6670feSJoseph Chen 1334e6670feSJoseph Chen #define GIC_IRQS_NR (6 * 32) 1344e6670feSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 1354e6670feSJoseph Chen 1364e6670feSJoseph Chen #define GPIO_BANK_NUM 5 1374e6670feSJoseph Chen #define GPIO_BANK_PINS 32 13860848109SJoseph Chen 13960848109SJoseph Chen #elif defined(CONFIG_ROCKCHIP_PX30) 14060848109SJoseph Chen #define GPIO0_PHYS 0xff040000 14160848109SJoseph Chen #define GPIO1_PHYS 0xff250000 14260848109SJoseph Chen #define GPIO2_PHYS 0xff260000 14360848109SJoseph Chen #define GPIO3_PHYS 0xff270000 14460848109SJoseph Chen 14560848109SJoseph Chen #define IRQ_GPIO0 35 14660848109SJoseph Chen #define IRQ_GPIO1 36 14760848109SJoseph Chen #define IRQ_GPIO2 37 14860848109SJoseph Chen #define IRQ_GPIO3 38 14960848109SJoseph Chen #define IRQ_PWM0 56 15060848109SJoseph Chen #define IRQ_PWM1 57 15149f812ddSJoseph Chen #define IRQ_TIMER0 62 /* non-secure */ 15260848109SJoseph Chen #define IRQ_TIMER1 63 /* non-secure */ 15360848109SJoseph Chen 15460848109SJoseph Chen #define GIC_IRQS_NR (4 * 32) 15560848109SJoseph Chen #define GPIO_IRQS_NR (4 * 32) 15660848109SJoseph Chen 15760848109SJoseph Chen #define GPIO_BANK_NUM 4 15860848109SJoseph Chen #define GPIO_BANK_PINS 32 15960848109SJoseph Chen 1600b4bf976SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3308) 1610b4bf976SJoseph Chen #define GPIO0_PHYS 0xff220000 1620b4bf976SJoseph Chen #define GPIO1_PHYS 0xff230000 1630b4bf976SJoseph Chen #define GPIO2_PHYS 0xff240000 1640b4bf976SJoseph Chen #define GPIO3_PHYS 0xff250000 1650b4bf976SJoseph Chen #define GPIO4_PHYS 0xff260000 1660b4bf976SJoseph Chen 1670b4bf976SJoseph Chen #define IRQ_TIMER1 58 /* ch0 ns timer1 */ 1680b4bf976SJoseph Chen #define IRQ_GPIO0 72 1690b4bf976SJoseph Chen #define IRQ_GPIO1 73 1700b4bf976SJoseph Chen #define IRQ_GPIO2 74 1710b4bf976SJoseph Chen #define IRQ_GPIO3 75 1720b4bf976SJoseph Chen #define IRQ_GPIO4 76 1730b4bf976SJoseph Chen 1740b4bf976SJoseph Chen #define GIC_IRQS_NR (5 * 32) 1750b4bf976SJoseph Chen #define GPIO_IRQS_NR (5 * 32) 1760b4bf976SJoseph Chen 1770b4bf976SJoseph Chen #define GPIO_BANK_NUM 5 1780b4bf976SJoseph Chen #define GPIO_BANK_PINS 32 17947ad8107SJoseph Chen 18047ad8107SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK1808) 18147ad8107SJoseph Chen #define GPIO0_PHYS 0xff4c0000 18247ad8107SJoseph Chen #define GPIO1_PHYS 0xff690000 18347ad8107SJoseph Chen #define GPIO2_PHYS 0xff6a0000 18447ad8107SJoseph Chen #define GPIO3_PHYS 0xff6b0000 18547ad8107SJoseph Chen #define GPIO4_PHYS 0xff6c0000 18647ad8107SJoseph Chen 18747ad8107SJoseph Chen #define IRQ_GPIO0 35 18847ad8107SJoseph Chen #define IRQ_GPIO1 36 18947ad8107SJoseph Chen #define IRQ_GPIO2 37 19047ad8107SJoseph Chen #define IRQ_GPIO3 38 19147ad8107SJoseph Chen #define IRQ_GPIO4 114 19247ad8107SJoseph Chen 19347ad8107SJoseph Chen #define IRQ_TIMER0 58 19447ad8107SJoseph Chen #define IRQ_TIMER1 59 19547ad8107SJoseph Chen 19647ad8107SJoseph Chen #define GIC_IRQS_NR (5 * 32) 19747ad8107SJoseph Chen #define GPIO_IRQS_NR (5 * 32) 19847ad8107SJoseph Chen 19947ad8107SJoseph Chen #define GPIO_BANK_NUM 5 20047ad8107SJoseph Chen #define GPIO_BANK_PINS 32 20147ad8107SJoseph Chen 202b9dcc643SXuhui Lin #elif defined(CONFIG_ROCKCHIP_RV1103B) 203b9dcc643SXuhui Lin #define GPIO0_PHYS 0x20520000 204b9dcc643SXuhui Lin #define GPIO1_PHYS 0x20d80000 205b9dcc643SXuhui Lin #define GPIO2_PHYS 0x20840000 206b9dcc643SXuhui Lin 207b9dcc643SXuhui Lin #define GIC_IRQS_NR 159 208b9dcc643SXuhui Lin #define GPIO_IRQS_NR (3 * 32) 209b9dcc643SXuhui Lin 210b9dcc643SXuhui Lin #define GPIO_BANK_NUM 3 211b9dcc643SXuhui Lin #define GPIO_BANK_PINS 32 212b9dcc643SXuhui Lin 213b9dcc643SXuhui Lin #define IRQ_USB_OTG 47 214b9dcc643SXuhui Lin #define IRQ_TIMER1 65 215b9dcc643SXuhui Lin 216b9dcc643SXuhui Lin #define IRQ_GPIO0 IRQ_GPIO0_0 217b9dcc643SXuhui Lin #define IRQ_GPIO0_0 107 218b9dcc643SXuhui Lin #define IRQ_GPIO0_1 108 219b9dcc643SXuhui Lin #define IRQ_GPIO0_2 109 220b9dcc643SXuhui Lin #define IRQ_GPIO0_3 110 221b9dcc643SXuhui Lin 222b9dcc643SXuhui Lin #define IRQ_GPIO1 IRQ_GPIO1_0 223b9dcc643SXuhui Lin #define IRQ_GPIO1_0 111 224b9dcc643SXuhui Lin #define IRQ_GPIO1_1 112 225b9dcc643SXuhui Lin #define IRQ_GPIO1_2 113 226b9dcc643SXuhui Lin #define IRQ_GPIO1_3 114 227b9dcc643SXuhui Lin 228b9dcc643SXuhui Lin #define IRQ_GPIO2 IRQ_GPIO2_0 229b9dcc643SXuhui Lin #define IRQ_GPIO2_0 115 230b9dcc643SXuhui Lin #define IRQ_GPIO2_1 116 231b9dcc643SXuhui Lin #define IRQ_GPIO2_2 117 232b9dcc643SXuhui Lin #define IRQ_GPIO2_3 118 233b9dcc643SXuhui Lin 234c928344eSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RV1106) 235c928344eSJoseph Chen #define GPIO0_PHYS 0xff460000 236c928344eSJoseph Chen #define GPIO1_PHYS 0xff620000 237c928344eSJoseph Chen #define GPIO2_PHYS 0xff630000 238c928344eSJoseph Chen #define GPIO3_PHYS 0xff640000 239c928344eSJoseph Chen #define GPIO4_PHYS 0xff650000 240c928344eSJoseph Chen 241c928344eSJoseph Chen #define GIC_IRQS_NR (5 * 32) 242c928344eSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 243c928344eSJoseph Chen 244c928344eSJoseph Chen #define GPIO_BANK_NUM 5 245c928344eSJoseph Chen #define GPIO_BANK_PINS 32 246c928344eSJoseph Chen 247c928344eSJoseph Chen #define IRQ_USB_OTG 117 248c928344eSJoseph Chen #define IRQ_TIMER1 57 249c928344eSJoseph Chen #define IRQ_GPIO0 66 250c928344eSJoseph Chen #define IRQ_GPIO1 67 251c928344eSJoseph Chen #define IRQ_GPIO2 68 252c928344eSJoseph Chen #define IRQ_GPIO3 69 253c928344eSJoseph Chen #define IRQ_GPIO4 70 254c928344eSJoseph Chen 255066e9bcbSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RV1126) 256066e9bcbSJoseph Chen #define GPIO0_PHYS 0xff460000 257066e9bcbSJoseph Chen #define GPIO1_PHYS 0xff620000 258066e9bcbSJoseph Chen #define GPIO2_PHYS 0xff630000 259066e9bcbSJoseph Chen #define GPIO3_PHYS 0xff640000 260066e9bcbSJoseph Chen #define GPIO4_PHYS 0xff650000 261066e9bcbSJoseph Chen 262066e9bcbSJoseph Chen #define GIC_IRQS_NR (5 * 32) 263066e9bcbSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 264066e9bcbSJoseph Chen 265066e9bcbSJoseph Chen #define GPIO_BANK_NUM 5 266066e9bcbSJoseph Chen #define GPIO_BANK_PINS 32 267066e9bcbSJoseph Chen 268066e9bcbSJoseph Chen #define IRQ_USB_OTG 117 269066e9bcbSJoseph Chen #define IRQ_TIMER1 57 270066e9bcbSJoseph Chen #define IRQ_GPIO0 66 271066e9bcbSJoseph Chen #define IRQ_GPIO1 67 272066e9bcbSJoseph Chen #define IRQ_GPIO2 68 273066e9bcbSJoseph Chen #define IRQ_GPIO3 69 274066e9bcbSJoseph Chen #define IRQ_GPIO4 70 275066e9bcbSJoseph Chen 276*85e5c210SXuhui Lin #elif defined(CONFIG_ROCKCHIP_RK3506) 277*85e5c210SXuhui Lin #define GPIO0_PHYS 0xff940000 278*85e5c210SXuhui Lin #define GPIO1_PHYS 0xff870000 279*85e5c210SXuhui Lin #define GPIO2_PHYS 0xff1c0000 280*85e5c210SXuhui Lin #define GPIO3_PHYS 0xff1d0000 281*85e5c210SXuhui Lin #define GPIO4_PHYS 0xff1e0000 282*85e5c210SXuhui Lin 283*85e5c210SXuhui Lin #define GIC_IRQS_NR 185 284*85e5c210SXuhui Lin #define GPIO_IRQS_NR (5 * 32) 285*85e5c210SXuhui Lin 286*85e5c210SXuhui Lin #define GPIO_BANK_NUM 5 287*85e5c210SXuhui Lin #define GPIO_BANK_PINS 32 288*85e5c210SXuhui Lin 289*85e5c210SXuhui Lin #define IRQ_TIMER0 IRQ_TIMER0_0 290*85e5c210SXuhui Lin #define IRQ_TIMER0_0 126 291*85e5c210SXuhui Lin #define IRQ_TIMER0_1 127 292*85e5c210SXuhui Lin #define IRQ_TIMER0_2 128 293*85e5c210SXuhui Lin #define IRQ_TIMER0_3 129 294*85e5c210SXuhui Lin #define IRQ_TIMER0_4 130 295*85e5c210SXuhui Lin #define IRQ_TIMER0_5 131 296*85e5c210SXuhui Lin 297*85e5c210SXuhui Lin #define IRQ_GPIO0 IRQ_GPIO0_0 298*85e5c210SXuhui Lin #define IRQ_GPIO0_0 32 299*85e5c210SXuhui Lin #define IRQ_GPIO0_1 33 300*85e5c210SXuhui Lin #define IRQ_GPIO0_2 34 301*85e5c210SXuhui Lin #define IRQ_GPIO0_3 35 302*85e5c210SXuhui Lin 303*85e5c210SXuhui Lin #define IRQ_GPIO1 IRQ_GPIO1_0 304*85e5c210SXuhui Lin #define IRQ_GPIO1_0 36 305*85e5c210SXuhui Lin #define IRQ_GPIO1_1 37 306*85e5c210SXuhui Lin #define IRQ_GPIO1_2 38 307*85e5c210SXuhui Lin #define IRQ_GPIO1_3 39 308*85e5c210SXuhui Lin 309*85e5c210SXuhui Lin #define IRQ_GPIO2 IRQ_GPIO2_0 310*85e5c210SXuhui Lin #define IRQ_GPIO2_0 40 311*85e5c210SXuhui Lin #define IRQ_GPIO2_1 41 312*85e5c210SXuhui Lin #define IRQ_GPIO2_2 42 313*85e5c210SXuhui Lin #define IRQ_GPIO2_3 43 314*85e5c210SXuhui Lin 315*85e5c210SXuhui Lin #define IRQ_GPIO3 IRQ_GPIO3_0 316*85e5c210SXuhui Lin #define IRQ_GPIO3_0 44 317*85e5c210SXuhui Lin #define IRQ_GPIO3_1 45 318*85e5c210SXuhui Lin #define IRQ_GPIO3_2 46 319*85e5c210SXuhui Lin #define IRQ_GPIO3_3 47 320*85e5c210SXuhui Lin 321*85e5c210SXuhui Lin #define IRQ_GPIO4 IRQ_GPIO4_0 322*85e5c210SXuhui Lin #define IRQ_GPIO4_0 48 323*85e5c210SXuhui Lin #define IRQ_GPIO4_1 49 324*85e5c210SXuhui Lin #define IRQ_GPIO4_2 50 325*85e5c210SXuhui Lin #define IRQ_GPIO4_3 51 326*85e5c210SXuhui Lin 327c6f7c1a3SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3528) 328c6f7c1a3SJoseph Chen #define GPIO0_PHYS 0xff610000 329c6f7c1a3SJoseph Chen #define GPIO1_PHYS 0xffaf0000 330c6f7c1a3SJoseph Chen #define GPIO2_PHYS 0xffb00000 331c6f7c1a3SJoseph Chen #define GPIO3_PHYS 0xffb10000 332c6f7c1a3SJoseph Chen #define GPIO4_PHYS 0xffb20000 333c6f7c1a3SJoseph Chen 334c6f7c1a3SJoseph Chen #define GIC_IRQS_NR (5 * 32) 335c6f7c1a3SJoseph Chen #define GPIO_IRQS_NR (5 * 32) 336c6f7c1a3SJoseph Chen 337c6f7c1a3SJoseph Chen #define GPIO_BANK_NUM 5 338c6f7c1a3SJoseph Chen #define GPIO_BANK_PINS 32 339c6f7c1a3SJoseph Chen 340c6f7c1a3SJoseph Chen #define IRQ_TIMER0 63 341c6f7c1a3SJoseph Chen #define IRQ_GPIO0 103 342c6f7c1a3SJoseph Chen #define IRQ_GPIO1 105 343c6f7c1a3SJoseph Chen #define IRQ_GPIO2 107 344c6f7c1a3SJoseph Chen #define IRQ_GPIO3 108 345c6f7c1a3SJoseph Chen #define IRQ_GPIO4 110 346c6f7c1a3SJoseph Chen 34756f7d184SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3562) 34856f7d184SJoseph Chen #define GPIO0_PHYS 0xff260000 34956f7d184SJoseph Chen #define GPIO1_PHYS 0xff620000 35056f7d184SJoseph Chen #define GPIO2_PHYS 0xff630000 35156f7d184SJoseph Chen #define GPIO3_PHYS 0xffac0000 35256f7d184SJoseph Chen #define GPIO4_PHYS 0xffad0000 35356f7d184SJoseph Chen 35456f7d184SJoseph Chen #define GIC_IRQS_NR (5 * 32) 35556f7d184SJoseph Chen #define GPIO_IRQS_NR (5 * 32) 35656f7d184SJoseph Chen 35756f7d184SJoseph Chen #define GPIO_BANK_NUM 5 35856f7d184SJoseph Chen #define GPIO_BANK_PINS 32 35956f7d184SJoseph Chen 36056f7d184SJoseph Chen #define IRQ_TIMER0 77 36156f7d184SJoseph Chen #define IRQ_GPIO0 32 36256f7d184SJoseph Chen #define IRQ_GPIO1 34 36356f7d184SJoseph Chen #define IRQ_GPIO2 36 36456f7d184SJoseph Chen #define IRQ_GPIO3 38 36556f7d184SJoseph Chen #define IRQ_GPIO4 40 36656f7d184SJoseph Chen 3675033f049SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3568) 3685033f049SJoseph Chen #define GPIO0_PHYS 0xfdd60000 3695033f049SJoseph Chen #define GPIO1_PHYS 0xfe740000 3705033f049SJoseph Chen #define GPIO2_PHYS 0xfe750000 3715033f049SJoseph Chen #define GPIO3_PHYS 0xfe760000 3725033f049SJoseph Chen #define GPIO4_PHYS 0xfe770000 3735033f049SJoseph Chen 3745033f049SJoseph Chen #define GIC_IRQS_NR (5 * 32) 3755033f049SJoseph Chen #define GPIO_IRQS_NR (5 * 32) 3765033f049SJoseph Chen 3775033f049SJoseph Chen #define GPIO_BANK_NUM 5 3785033f049SJoseph Chen #define GPIO_BANK_PINS 32 3795033f049SJoseph Chen 3805033f049SJoseph Chen #define IRQ_TIMER0 141 3815033f049SJoseph Chen #define IRQ_GPIO0 65 3825033f049SJoseph Chen #define IRQ_GPIO1 66 3835033f049SJoseph Chen #define IRQ_GPIO2 67 3845033f049SJoseph Chen #define IRQ_GPIO3 68 3855033f049SJoseph Chen #define IRQ_GPIO4 69 3865033f049SJoseph Chen 387bf72c9c9SXuhui Lin #elif defined(CONFIG_ROCKCHIP_RK3576) 388bf72c9c9SXuhui Lin #define GPIO0_PHYS 0x27320000 389bf72c9c9SXuhui Lin #define GPIO1_PHYS 0x2ae10000 390bf72c9c9SXuhui Lin #define GPIO2_PHYS 0x2ae20000 391bf72c9c9SXuhui Lin #define GPIO3_PHYS 0x2ae30000 392bf72c9c9SXuhui Lin #define GPIO4_PHYS 0x2ae40000 393bf72c9c9SXuhui Lin 3948a970f94SXuhui Lin #define GIC_IRQS_NR (420) 395bf72c9c9SXuhui Lin #define GPIO_IRQS_NR (5 * 32) 396bf72c9c9SXuhui Lin 397bf72c9c9SXuhui Lin #define GPIO_BANK_NUM 5 398bf72c9c9SXuhui Lin #define GPIO_BANK_PINS 32 399bf72c9c9SXuhui Lin 400bf72c9c9SXuhui Lin #define IRQ_TIMER0 77 401bf72c9c9SXuhui Lin 402bf72c9c9SXuhui Lin #define IRQ_GPIO0 IRQ_GPIO0_0 403bf72c9c9SXuhui Lin #define IRQ_GPIO0_0 185 404bf72c9c9SXuhui Lin #define IRQ_GPIO0_1 186 405bf72c9c9SXuhui Lin #define IRQ_GPIO0_2 187 406bf72c9c9SXuhui Lin #define IRQ_GPIO0_3 188 407bf72c9c9SXuhui Lin 408bf72c9c9SXuhui Lin #define IRQ_GPIO1 IRQ_GPIO1_0 409bf72c9c9SXuhui Lin #define IRQ_GPIO1_0 189 410bf72c9c9SXuhui Lin #define IRQ_GPIO1_1 190 411bf72c9c9SXuhui Lin #define IRQ_GPIO1_2 191 412bf72c9c9SXuhui Lin #define IRQ_GPIO1_3 192 413bf72c9c9SXuhui Lin 414bf72c9c9SXuhui Lin #define IRQ_GPIO2 IRQ_GPIO2_0 415bf72c9c9SXuhui Lin #define IRQ_GPIO2_0 193 416bf72c9c9SXuhui Lin #define IRQ_GPIO2_1 194 417bf72c9c9SXuhui Lin #define IRQ_GPIO2_2 195 418bf72c9c9SXuhui Lin #define IRQ_GPIO2_3 196 419bf72c9c9SXuhui Lin 420bf72c9c9SXuhui Lin #define IRQ_GPIO3 IRQ_GPIO3_0 421bf72c9c9SXuhui Lin #define IRQ_GPIO3_0 197 422bf72c9c9SXuhui Lin #define IRQ_GPIO3_1 198 423bf72c9c9SXuhui Lin #define IRQ_GPIO3_2 199 424bf72c9c9SXuhui Lin #define IRQ_GPIO3_3 200 425bf72c9c9SXuhui Lin 426bf72c9c9SXuhui Lin #define IRQ_GPIO4 IRQ_GPIO4_0 427bf72c9c9SXuhui Lin #define IRQ_GPIO4_0 201 428bf72c9c9SXuhui Lin #define IRQ_GPIO4_1 202 429bf72c9c9SXuhui Lin #define IRQ_GPIO4_2 203 430bf72c9c9SXuhui Lin #define IRQ_GPIO4_3 204 431bf72c9c9SXuhui Lin 432c20dcaebSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3588) 433c20dcaebSJoseph Chen #define GPIO0_PHYS 0xfd8a0000 434c20dcaebSJoseph Chen #define GPIO1_PHYS 0xfec20000 435c20dcaebSJoseph Chen #define GPIO2_PHYS 0xfec30000 436c20dcaebSJoseph Chen #define GPIO3_PHYS 0xfec40000 437c20dcaebSJoseph Chen #define GPIO4_PHYS 0xfec50000 438c20dcaebSJoseph Chen 439c20dcaebSJoseph Chen #define GIC_IRQS_NR (455) 440c20dcaebSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 441c20dcaebSJoseph Chen 442c20dcaebSJoseph Chen #define GPIO_BANK_NUM 5 443c20dcaebSJoseph Chen #define GPIO_BANK_PINS 32 444c20dcaebSJoseph Chen 445c20dcaebSJoseph Chen #define IRQ_TIMER0 321 446c20dcaebSJoseph Chen #define IRQ_GPIO0 309 447c20dcaebSJoseph Chen #define IRQ_GPIO1 310 448c20dcaebSJoseph Chen #define IRQ_GPIO2 311 449c20dcaebSJoseph Chen #define IRQ_GPIO3 312 450c20dcaebSJoseph Chen #define IRQ_GPIO4 313 4514e6670feSJoseph Chen #else 4524e6670feSJoseph Chen "Missing define RIQ relative things" 4534e6670feSJoseph Chen #endif 4544e6670feSJoseph Chen 4554e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */ 456