14e6670feSJoseph Chen /* 24e6670feSJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 34e6670feSJoseph Chen * 44e6670feSJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 54e6670feSJoseph Chen */ 64e6670feSJoseph Chen 74e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_ 84e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_ 94e6670feSJoseph Chen 10*778da45fSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK3128) 11*778da45fSJoseph Chen #define GPIO0_PHYS 0x2007C000 12*778da45fSJoseph Chen #define GPIO1_PHYS 0x20080000 13*778da45fSJoseph Chen #define GPIO2_PHYS 0x20084000 14*778da45fSJoseph Chen #define GPIO3_PHYS 0x20088000 15*778da45fSJoseph Chen 16*778da45fSJoseph Chen #define GIC_IRQS_NR (4 * 32) 17*778da45fSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 18*778da45fSJoseph Chen 19*778da45fSJoseph Chen #define GPIO_BANK_NUM 4 20*778da45fSJoseph Chen #define GPIO_BANK_PINS 32 21*778da45fSJoseph Chen 22*778da45fSJoseph Chen #define IRQ_GPIO0 68 23*778da45fSJoseph Chen #define IRQ_GPIO1 69 24*778da45fSJoseph Chen #define IRQ_GPIO2 79 25*778da45fSJoseph Chen #define IRQ_GPIO3 71 26*778da45fSJoseph Chen 27*778da45fSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK322X) 284e6670feSJoseph Chen #define GPIO0_PHYS 0x11110000 294e6670feSJoseph Chen #define GPIO1_PHYS 0x11120000 304e6670feSJoseph Chen #define GPIO2_PHYS 0x11130000 314e6670feSJoseph Chen #define GPIO3_PHYS 0x11140000 324e6670feSJoseph Chen 334e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 344e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 354e6670feSJoseph Chen 364e6670feSJoseph Chen #define GPIO_BANK_NUM 4 374e6670feSJoseph Chen #define GPIO_BANK_PINS 32 384e6670feSJoseph Chen 394e6670feSJoseph Chen #define IRQ_GPIO0 83 404e6670feSJoseph Chen #define IRQ_GPIO1 84 414e6670feSJoseph Chen #define IRQ_GPIO2 85 424e6670feSJoseph Chen #define IRQ_GPIO3 86 434e6670feSJoseph Chen 444e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288) 454e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 464e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 474e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 484e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 494e6670feSJoseph Chen #define GPIO4_PHYS 0xFF7B0000 504e6670feSJoseph Chen #define GPIO5_PHYS 0xFF7C0000 514e6670feSJoseph Chen #define GPIO6_PHYS 0xFF7D0000 524e6670feSJoseph Chen #define GPIO7_PHYS 0xFF7E0000 534e6670feSJoseph Chen #define GPIO8_PHYS 0xFF7F0000 544e6670feSJoseph Chen 554e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 564e6670feSJoseph Chen #define GPIO_IRQS_NR (9 * 32) 574e6670feSJoseph Chen 584e6670feSJoseph Chen #define GPIO_BANK_NUM 9 594e6670feSJoseph Chen #define GPIO_BANK_PINS 32 604e6670feSJoseph Chen 614e6670feSJoseph Chen #define IRQ_GPIO0 113 624e6670feSJoseph Chen #define IRQ_GPIO1 114 634e6670feSJoseph Chen #define IRQ_GPIO2 115 644e6670feSJoseph Chen #define IRQ_GPIO3 116 654e6670feSJoseph Chen #define IRQ_GPIO4 117 664e6670feSJoseph Chen #define IRQ_GPIO5 118 674e6670feSJoseph Chen #define IRQ_GPIO6 119 684e6670feSJoseph Chen #define IRQ_GPIO7 120 694e6670feSJoseph Chen #define IRQ_GPIO8 121 704e6670feSJoseph Chen 714e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328) 724e6670feSJoseph Chen #define GPIO0_PHYS 0xFF210000 734e6670feSJoseph Chen #define GPIO1_PHYS 0xFF220000 744e6670feSJoseph Chen #define GPIO2_PHYS 0xFF230000 754e6670feSJoseph Chen #define GPIO3_PHYS 0xFF240000 764e6670feSJoseph Chen 774e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 784e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 794e6670feSJoseph Chen 804e6670feSJoseph Chen #define GPIO_BANK_NUM 4 814e6670feSJoseph Chen #define GPIO_BANK_PINS 32 824e6670feSJoseph Chen 834e6670feSJoseph Chen #define IRQ_GPIO0 83 844e6670feSJoseph Chen #define IRQ_GPIO1 84 854e6670feSJoseph Chen #define IRQ_GPIO2 85 864e6670feSJoseph Chen #define IRQ_GPIO3 86 874e6670feSJoseph Chen 884e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368) 894e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 904e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 914e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 924e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 934e6670feSJoseph Chen 944e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 954e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 964e6670feSJoseph Chen 974e6670feSJoseph Chen #define GPIO_BANK_NUM 4 984e6670feSJoseph Chen #define GPIO_BANK_PINS 32 994e6670feSJoseph Chen 1004e6670feSJoseph Chen #define IRQ_GPIO0 113 1014e6670feSJoseph Chen #define IRQ_GPIO1 114 1024e6670feSJoseph Chen #define IRQ_GPIO2 115 1034e6670feSJoseph Chen #define IRQ_GPIO3 116 1044e6670feSJoseph Chen 1054e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399) 1064e6670feSJoseph Chen #define GPIO0_PHYS 0xFF720000 1074e6670feSJoseph Chen #define GPIO1_PHYS 0xFF730000 1084e6670feSJoseph Chen #define GPIO2_PHYS 0xFF780000 1094e6670feSJoseph Chen #define GPIO3_PHYS 0xFF788000 1104e6670feSJoseph Chen #define GPIO4_PHYS 0xFF790000 1114e6670feSJoseph Chen 1124e6670feSJoseph Chen #define IRQ_GPIO0 46 1134e6670feSJoseph Chen #define IRQ_GPIO1 47 1144e6670feSJoseph Chen #define IRQ_GPIO2 48 1154e6670feSJoseph Chen #define IRQ_GPIO3 49 1164e6670feSJoseph Chen #define IRQ_GPIO4 50 1174e6670feSJoseph Chen 1184e6670feSJoseph Chen #define GIC_IRQS_NR (6 * 32) 1194e6670feSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 1204e6670feSJoseph Chen 1214e6670feSJoseph Chen #define GPIO_BANK_NUM 5 1224e6670feSJoseph Chen #define GPIO_BANK_PINS 32 1234e6670feSJoseph Chen #else 1244e6670feSJoseph Chen "Missing define RIQ relative things" 1254e6670feSJoseph Chen #endif 1264e6670feSJoseph Chen 1274e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */ 128