14e6670feSJoseph Chen /* 24e6670feSJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 34e6670feSJoseph Chen * 44e6670feSJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 54e6670feSJoseph Chen */ 64e6670feSJoseph Chen 74e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_ 84e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_ 94e6670feSJoseph Chen 10778da45fSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK3128) 11778da45fSJoseph Chen #define GPIO0_PHYS 0x2007C000 12778da45fSJoseph Chen #define GPIO1_PHYS 0x20080000 13778da45fSJoseph Chen #define GPIO2_PHYS 0x20084000 14778da45fSJoseph Chen #define GPIO3_PHYS 0x20088000 15778da45fSJoseph Chen 16778da45fSJoseph Chen #define GIC_IRQS_NR (4 * 32) 17778da45fSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 18778da45fSJoseph Chen 19778da45fSJoseph Chen #define GPIO_BANK_NUM 4 20778da45fSJoseph Chen #define GPIO_BANK_PINS 32 21778da45fSJoseph Chen 22*6d0f6303SJoseph Chen #define IRQ_TIMER1 61 23778da45fSJoseph Chen #define IRQ_GPIO0 68 24778da45fSJoseph Chen #define IRQ_GPIO1 69 25778da45fSJoseph Chen #define IRQ_GPIO2 79 26778da45fSJoseph Chen #define IRQ_GPIO3 71 27778da45fSJoseph Chen 28778da45fSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK322X) 294e6670feSJoseph Chen #define GPIO0_PHYS 0x11110000 304e6670feSJoseph Chen #define GPIO1_PHYS 0x11120000 314e6670feSJoseph Chen #define GPIO2_PHYS 0x11130000 324e6670feSJoseph Chen #define GPIO3_PHYS 0x11140000 334e6670feSJoseph Chen 344e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 354e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 364e6670feSJoseph Chen 374e6670feSJoseph Chen #define GPIO_BANK_NUM 4 384e6670feSJoseph Chen #define GPIO_BANK_PINS 32 394e6670feSJoseph Chen 40*6d0f6303SJoseph Chen #define IRQ_TIMER1 76 414e6670feSJoseph Chen #define IRQ_GPIO0 83 424e6670feSJoseph Chen #define IRQ_GPIO1 84 434e6670feSJoseph Chen #define IRQ_GPIO2 85 444e6670feSJoseph Chen #define IRQ_GPIO3 86 454e6670feSJoseph Chen 464e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288) 474e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 484e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 494e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 504e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 514e6670feSJoseph Chen #define GPIO4_PHYS 0xFF7B0000 524e6670feSJoseph Chen #define GPIO5_PHYS 0xFF7C0000 534e6670feSJoseph Chen #define GPIO6_PHYS 0xFF7D0000 544e6670feSJoseph Chen #define GPIO7_PHYS 0xFF7E0000 554e6670feSJoseph Chen #define GPIO8_PHYS 0xFF7F0000 564e6670feSJoseph Chen 574e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 584e6670feSJoseph Chen #define GPIO_IRQS_NR (9 * 32) 594e6670feSJoseph Chen 604e6670feSJoseph Chen #define GPIO_BANK_NUM 9 614e6670feSJoseph Chen #define GPIO_BANK_PINS 32 624e6670feSJoseph Chen 63*6d0f6303SJoseph Chen #define IRQ_TIMER1 99 644e6670feSJoseph Chen #define IRQ_GPIO0 113 654e6670feSJoseph Chen #define IRQ_GPIO1 114 664e6670feSJoseph Chen #define IRQ_GPIO2 115 674e6670feSJoseph Chen #define IRQ_GPIO3 116 684e6670feSJoseph Chen #define IRQ_GPIO4 117 694e6670feSJoseph Chen #define IRQ_GPIO5 118 704e6670feSJoseph Chen #define IRQ_GPIO6 119 714e6670feSJoseph Chen #define IRQ_GPIO7 120 724e6670feSJoseph Chen #define IRQ_GPIO8 121 734e6670feSJoseph Chen 744e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328) 754e6670feSJoseph Chen #define GPIO0_PHYS 0xFF210000 764e6670feSJoseph Chen #define GPIO1_PHYS 0xFF220000 774e6670feSJoseph Chen #define GPIO2_PHYS 0xFF230000 784e6670feSJoseph Chen #define GPIO3_PHYS 0xFF240000 794e6670feSJoseph Chen 804e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 814e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 824e6670feSJoseph Chen 834e6670feSJoseph Chen #define GPIO_BANK_NUM 4 844e6670feSJoseph Chen #define GPIO_BANK_PINS 32 854e6670feSJoseph Chen 86*6d0f6303SJoseph Chen #define IRQ_TIMER1 76 874e6670feSJoseph Chen #define IRQ_GPIO0 83 884e6670feSJoseph Chen #define IRQ_GPIO1 84 894e6670feSJoseph Chen #define IRQ_GPIO2 85 904e6670feSJoseph Chen #define IRQ_GPIO3 86 914e6670feSJoseph Chen 924e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368) 934e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 944e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 954e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 964e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 974e6670feSJoseph Chen 984e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 994e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 1004e6670feSJoseph Chen 1014e6670feSJoseph Chen #define GPIO_BANK_NUM 4 1024e6670feSJoseph Chen #define GPIO_BANK_PINS 32 1034e6670feSJoseph Chen 104*6d0f6303SJoseph Chen #define IRQ_TIMER1 79 1054e6670feSJoseph Chen #define IRQ_GPIO0 113 1064e6670feSJoseph Chen #define IRQ_GPIO1 114 1074e6670feSJoseph Chen #define IRQ_GPIO2 115 1084e6670feSJoseph Chen #define IRQ_GPIO3 116 1094e6670feSJoseph Chen 1104e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399) 1114e6670feSJoseph Chen #define GPIO0_PHYS 0xFF720000 1124e6670feSJoseph Chen #define GPIO1_PHYS 0xFF730000 1134e6670feSJoseph Chen #define GPIO2_PHYS 0xFF780000 1144e6670feSJoseph Chen #define GPIO3_PHYS 0xFF788000 1154e6670feSJoseph Chen #define GPIO4_PHYS 0xFF790000 1164e6670feSJoseph Chen 1174e6670feSJoseph Chen #define IRQ_GPIO0 46 1184e6670feSJoseph Chen #define IRQ_GPIO1 47 1194e6670feSJoseph Chen #define IRQ_GPIO2 48 1204e6670feSJoseph Chen #define IRQ_GPIO3 49 1214e6670feSJoseph Chen #define IRQ_GPIO4 50 122*6d0f6303SJoseph Chen #define IRQ_TIMER1 114 /* non-secure */ 1234e6670feSJoseph Chen 1244e6670feSJoseph Chen #define GIC_IRQS_NR (6 * 32) 1254e6670feSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 1264e6670feSJoseph Chen 1274e6670feSJoseph Chen #define GPIO_BANK_NUM 5 1284e6670feSJoseph Chen #define GPIO_BANK_PINS 32 1294e6670feSJoseph Chen #else 1304e6670feSJoseph Chen "Missing define RIQ relative things" 1314e6670feSJoseph Chen #endif 1324e6670feSJoseph Chen 1334e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */ 134