1*4e6670feSJoseph Chen /* 2*4e6670feSJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4e6670feSJoseph Chen * 4*4e6670feSJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5*4e6670feSJoseph Chen */ 6*4e6670feSJoseph Chen 7*4e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_ 8*4e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_ 9*4e6670feSJoseph Chen 10*4e6670feSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK322X) 11*4e6670feSJoseph Chen #define GPIO0_PHYS 0x11110000 12*4e6670feSJoseph Chen #define GPIO1_PHYS 0x11120000 13*4e6670feSJoseph Chen #define GPIO2_PHYS 0x11130000 14*4e6670feSJoseph Chen #define GPIO3_PHYS 0x11140000 15*4e6670feSJoseph Chen 16*4e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 17*4e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 18*4e6670feSJoseph Chen 19*4e6670feSJoseph Chen #define GPIO_BANK_NUM 4 20*4e6670feSJoseph Chen #define GPIO_BANK_PINS 32 21*4e6670feSJoseph Chen 22*4e6670feSJoseph Chen #define IRQ_GPIO0 83 23*4e6670feSJoseph Chen #define IRQ_GPIO1 84 24*4e6670feSJoseph Chen #define IRQ_GPIO2 85 25*4e6670feSJoseph Chen #define IRQ_GPIO3 86 26*4e6670feSJoseph Chen 27*4e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288) 28*4e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 29*4e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 30*4e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 31*4e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 32*4e6670feSJoseph Chen #define GPIO4_PHYS 0xFF7B0000 33*4e6670feSJoseph Chen #define GPIO5_PHYS 0xFF7C0000 34*4e6670feSJoseph Chen #define GPIO6_PHYS 0xFF7D0000 35*4e6670feSJoseph Chen #define GPIO7_PHYS 0xFF7E0000 36*4e6670feSJoseph Chen #define GPIO8_PHYS 0xFF7F0000 37*4e6670feSJoseph Chen 38*4e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 39*4e6670feSJoseph Chen #define GPIO_IRQS_NR (9 * 32) 40*4e6670feSJoseph Chen 41*4e6670feSJoseph Chen #define GPIO_BANK_NUM 9 42*4e6670feSJoseph Chen #define GPIO_BANK_PINS 32 43*4e6670feSJoseph Chen 44*4e6670feSJoseph Chen #define IRQ_GPIO0 113 45*4e6670feSJoseph Chen #define IRQ_GPIO1 114 46*4e6670feSJoseph Chen #define IRQ_GPIO2 115 47*4e6670feSJoseph Chen #define IRQ_GPIO3 116 48*4e6670feSJoseph Chen #define IRQ_GPIO4 117 49*4e6670feSJoseph Chen #define IRQ_GPIO5 118 50*4e6670feSJoseph Chen #define IRQ_GPIO6 119 51*4e6670feSJoseph Chen #define IRQ_GPIO7 120 52*4e6670feSJoseph Chen #define IRQ_GPIO8 121 53*4e6670feSJoseph Chen 54*4e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328) 55*4e6670feSJoseph Chen #define GPIO0_PHYS 0xFF210000 56*4e6670feSJoseph Chen #define GPIO1_PHYS 0xFF220000 57*4e6670feSJoseph Chen #define GPIO2_PHYS 0xFF230000 58*4e6670feSJoseph Chen #define GPIO3_PHYS 0xFF240000 59*4e6670feSJoseph Chen 60*4e6670feSJoseph Chen #define GIC_IRQS_NR (4 * 32) 61*4e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 62*4e6670feSJoseph Chen 63*4e6670feSJoseph Chen #define GPIO_BANK_NUM 4 64*4e6670feSJoseph Chen #define GPIO_BANK_PINS 32 65*4e6670feSJoseph Chen 66*4e6670feSJoseph Chen #define IRQ_GPIO0 83 67*4e6670feSJoseph Chen #define IRQ_GPIO1 84 68*4e6670feSJoseph Chen #define IRQ_GPIO2 85 69*4e6670feSJoseph Chen #define IRQ_GPIO3 86 70*4e6670feSJoseph Chen 71*4e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368) 72*4e6670feSJoseph Chen #define GPIO0_PHYS 0xFF750000 73*4e6670feSJoseph Chen #define GPIO1_PHYS 0xFF780000 74*4e6670feSJoseph Chen #define GPIO2_PHYS 0xFF790000 75*4e6670feSJoseph Chen #define GPIO3_PHYS 0xFF7A0000 76*4e6670feSJoseph Chen 77*4e6670feSJoseph Chen #define GIC_IRQS_NR (5 * 32) 78*4e6670feSJoseph Chen #define GPIO_IRQS_NR (4 * 32) 79*4e6670feSJoseph Chen 80*4e6670feSJoseph Chen #define GPIO_BANK_NUM 4 81*4e6670feSJoseph Chen #define GPIO_BANK_PINS 32 82*4e6670feSJoseph Chen 83*4e6670feSJoseph Chen #define IRQ_GPIO0 113 84*4e6670feSJoseph Chen #define IRQ_GPIO1 114 85*4e6670feSJoseph Chen #define IRQ_GPIO2 115 86*4e6670feSJoseph Chen #define IRQ_GPIO3 116 87*4e6670feSJoseph Chen 88*4e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399) 89*4e6670feSJoseph Chen #define GPIO0_PHYS 0xFF720000 90*4e6670feSJoseph Chen #define GPIO1_PHYS 0xFF730000 91*4e6670feSJoseph Chen #define GPIO2_PHYS 0xFF780000 92*4e6670feSJoseph Chen #define GPIO3_PHYS 0xFF788000 93*4e6670feSJoseph Chen #define GPIO4_PHYS 0xFF790000 94*4e6670feSJoseph Chen 95*4e6670feSJoseph Chen #define IRQ_GPIO0 46 96*4e6670feSJoseph Chen #define IRQ_GPIO1 47 97*4e6670feSJoseph Chen #define IRQ_GPIO2 48 98*4e6670feSJoseph Chen #define IRQ_GPIO3 49 99*4e6670feSJoseph Chen #define IRQ_GPIO4 50 100*4e6670feSJoseph Chen 101*4e6670feSJoseph Chen #define GIC_IRQS_NR (6 * 32) 102*4e6670feSJoseph Chen #define GPIO_IRQS_NR (5 * 32) 103*4e6670feSJoseph Chen 104*4e6670feSJoseph Chen #define GPIO_BANK_NUM 5 105*4e6670feSJoseph Chen #define GPIO_BANK_PINS 32 106*4e6670feSJoseph Chen #else 107*4e6670feSJoseph Chen "Missing define RIQ relative things" 108*4e6670feSJoseph Chen #endif 109*4e6670feSJoseph Chen 110*4e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */ 111