xref: /rk3399_rockchip-uboot/include/irq-platform.h (revision 0b4bf9764efc2ef2696b06d70c3cb9bbe8331ab8)
14e6670feSJoseph Chen /*
24e6670feSJoseph Chen  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
34e6670feSJoseph Chen  *
44e6670feSJoseph Chen  * SPDX-License-Identifier:     GPL-2.0+
54e6670feSJoseph Chen  */
64e6670feSJoseph Chen 
74e6670feSJoseph Chen #ifndef _ROCKCHIP_PLAT_IRQ_H_
84e6670feSJoseph Chen #define _ROCKCHIP_PLAT_IRQ_H_
94e6670feSJoseph Chen 
10778da45fSJoseph Chen #if defined(CONFIG_ROCKCHIP_RK3128)
11778da45fSJoseph Chen #define GPIO0_PHYS			0x2007C000
12778da45fSJoseph Chen #define GPIO1_PHYS			0x20080000
13778da45fSJoseph Chen #define GPIO2_PHYS			0x20084000
14778da45fSJoseph Chen #define GPIO3_PHYS			0x20088000
15778da45fSJoseph Chen 
16778da45fSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
17778da45fSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
18778da45fSJoseph Chen 
19778da45fSJoseph Chen #define GPIO_BANK_NUM			4
20778da45fSJoseph Chen #define GPIO_BANK_PINS			32
21778da45fSJoseph Chen 
226d0f6303SJoseph Chen #define IRQ_TIMER1			61
23778da45fSJoseph Chen #define IRQ_GPIO0			68
24778da45fSJoseph Chen #define IRQ_GPIO1			69
25a1b32c24SJoseph Chen #define IRQ_GPIO2			70
26778da45fSJoseph Chen #define IRQ_GPIO3			71
27778da45fSJoseph Chen 
28778da45fSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK322X)
294e6670feSJoseph Chen #define GPIO0_PHYS			0x11110000
304e6670feSJoseph Chen #define GPIO1_PHYS			0x11120000
314e6670feSJoseph Chen #define GPIO2_PHYS			0x11130000
324e6670feSJoseph Chen #define GPIO3_PHYS			0x11140000
334e6670feSJoseph Chen 
344e6670feSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
354e6670feSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
364e6670feSJoseph Chen 
374e6670feSJoseph Chen #define GPIO_BANK_NUM			4
384e6670feSJoseph Chen #define GPIO_BANK_PINS			32
394e6670feSJoseph Chen 
406d0f6303SJoseph Chen #define IRQ_TIMER1			76
41b0deaf68SZhangbin Tong #define IRQ_PWM				82
424e6670feSJoseph Chen #define IRQ_GPIO0			83
434e6670feSJoseph Chen #define IRQ_GPIO1			84
444e6670feSJoseph Chen #define IRQ_GPIO2			85
454e6670feSJoseph Chen #define IRQ_GPIO3			86
464e6670feSJoseph Chen 
474e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3288)
484e6670feSJoseph Chen #define GPIO0_PHYS			0xFF750000
494e6670feSJoseph Chen #define GPIO1_PHYS			0xFF780000
504e6670feSJoseph Chen #define GPIO2_PHYS			0xFF790000
514e6670feSJoseph Chen #define GPIO3_PHYS			0xFF7A0000
524e6670feSJoseph Chen #define GPIO4_PHYS			0xFF7B0000
534e6670feSJoseph Chen #define GPIO5_PHYS			0xFF7C0000
544e6670feSJoseph Chen #define GPIO6_PHYS			0xFF7D0000
554e6670feSJoseph Chen #define GPIO7_PHYS			0xFF7E0000
564e6670feSJoseph Chen #define GPIO8_PHYS			0xFF7F0000
574e6670feSJoseph Chen 
584e6670feSJoseph Chen #define GIC_IRQS_NR			(5 * 32)
594e6670feSJoseph Chen #define GPIO_IRQS_NR			(9 * 32)
604e6670feSJoseph Chen 
614e6670feSJoseph Chen #define GPIO_BANK_NUM			9
624e6670feSJoseph Chen #define GPIO_BANK_PINS			32
634e6670feSJoseph Chen 
646d0f6303SJoseph Chen #define IRQ_TIMER1			99
65b0deaf68SZhangbin Tong #define IRQ_PWM				110
664e6670feSJoseph Chen #define IRQ_GPIO0			113
674e6670feSJoseph Chen #define IRQ_GPIO1			114
684e6670feSJoseph Chen #define IRQ_GPIO2			115
694e6670feSJoseph Chen #define IRQ_GPIO3			116
704e6670feSJoseph Chen #define IRQ_GPIO4			117
714e6670feSJoseph Chen #define IRQ_GPIO5			118
724e6670feSJoseph Chen #define IRQ_GPIO6			119
734e6670feSJoseph Chen #define IRQ_GPIO7			120
744e6670feSJoseph Chen #define IRQ_GPIO8			121
754e6670feSJoseph Chen 
764e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3328)
774e6670feSJoseph Chen #define	GPIO0_PHYS			0xFF210000
784e6670feSJoseph Chen #define	GPIO1_PHYS			0xFF220000
794e6670feSJoseph Chen #define	GPIO2_PHYS			0xFF230000
804e6670feSJoseph Chen #define	GPIO3_PHYS			0xFF240000
814e6670feSJoseph Chen 
824e6670feSJoseph Chen #define GIC_IRQS_NR			(4 * 32)
834e6670feSJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
844e6670feSJoseph Chen 
854e6670feSJoseph Chen #define GPIO_BANK_NUM			4
864e6670feSJoseph Chen #define GPIO_BANK_PINS			32
874e6670feSJoseph Chen 
886d0f6303SJoseph Chen #define IRQ_TIMER1			76
89b0deaf68SZhangbin Tong #define IRQ_PWM				82
904e6670feSJoseph Chen #define IRQ_GPIO0			83
914e6670feSJoseph Chen #define IRQ_GPIO1			84
924e6670feSJoseph Chen #define IRQ_GPIO2			85
934e6670feSJoseph Chen #define IRQ_GPIO3			86
944e6670feSJoseph Chen 
954e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3368)
964e6670feSJoseph Chen #define GPIO0_PHYS			0xFF750000
974e6670feSJoseph Chen #define GPIO1_PHYS			0xFF780000
984e6670feSJoseph Chen #define GPIO2_PHYS			0xFF790000
994e6670feSJoseph Chen #define GPIO3_PHYS			0xFF7A0000
1004e6670feSJoseph Chen 
1014e6670feSJoseph Chen #define GIC_IRQS_NR                     (5 * 32)
1024e6670feSJoseph Chen #define GPIO_IRQS_NR                    (4 * 32)
1034e6670feSJoseph Chen 
1044e6670feSJoseph Chen #define GPIO_BANK_NUM			4
1054e6670feSJoseph Chen #define GPIO_BANK_PINS			32
1064e6670feSJoseph Chen 
1076d0f6303SJoseph Chen #define IRQ_TIMER1			79
108b0deaf68SZhangbin Tong #define IRQ_PWM				110
1094e6670feSJoseph Chen #define IRQ_GPIO0			113
1104e6670feSJoseph Chen #define IRQ_GPIO1			114
1114e6670feSJoseph Chen #define IRQ_GPIO2			115
1124e6670feSJoseph Chen #define IRQ_GPIO3			116
1134e6670feSJoseph Chen 
1144e6670feSJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3399)
1154e6670feSJoseph Chen #define GPIO0_PHYS			0xFF720000
1164e6670feSJoseph Chen #define GPIO1_PHYS			0xFF730000
1174e6670feSJoseph Chen #define GPIO2_PHYS			0xFF780000
1184e6670feSJoseph Chen #define GPIO3_PHYS			0xFF788000
1194e6670feSJoseph Chen #define GPIO4_PHYS			0xFF790000
1204e6670feSJoseph Chen 
1214e6670feSJoseph Chen #define IRQ_GPIO0			46
1224e6670feSJoseph Chen #define IRQ_GPIO1			47
1234e6670feSJoseph Chen #define IRQ_GPIO2			48
1244e6670feSJoseph Chen #define IRQ_GPIO3			49
1254e6670feSJoseph Chen #define IRQ_GPIO4			50
126b0deaf68SZhangbin Tong #define IRQ_PWM				93
1276d0f6303SJoseph Chen #define IRQ_TIMER1			114	/* non-secure */
1284e6670feSJoseph Chen 
1294e6670feSJoseph Chen #define GIC_IRQS_NR			(6 * 32)
1304e6670feSJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
1314e6670feSJoseph Chen 
1324e6670feSJoseph Chen #define GPIO_BANK_NUM			5
1334e6670feSJoseph Chen #define GPIO_BANK_PINS			32
13460848109SJoseph Chen 
13560848109SJoseph Chen #elif defined(CONFIG_ROCKCHIP_PX30)
13660848109SJoseph Chen #define GPIO0_PHYS			0xff040000
13760848109SJoseph Chen #define GPIO1_PHYS			0xff250000
13860848109SJoseph Chen #define GPIO2_PHYS			0xff260000
13960848109SJoseph Chen #define GPIO3_PHYS			0xff270000
14060848109SJoseph Chen 
14160848109SJoseph Chen #define IRQ_GPIO0			35
14260848109SJoseph Chen #define IRQ_GPIO1			36
14360848109SJoseph Chen #define IRQ_GPIO2			37
14460848109SJoseph Chen #define IRQ_GPIO3			38
14560848109SJoseph Chen #define IRQ_PWM0			56
14660848109SJoseph Chen #define IRQ_PWM1			57
14749f812ddSJoseph Chen #define IRQ_TIMER0			62	/* non-secure */
14860848109SJoseph Chen #define IRQ_TIMER1			63	/* non-secure */
14960848109SJoseph Chen 
15060848109SJoseph Chen #define GIC_IRQS_NR			(4 * 32)
15160848109SJoseph Chen #define GPIO_IRQS_NR			(4 * 32)
15260848109SJoseph Chen 
15360848109SJoseph Chen #define GPIO_BANK_NUM			4
15460848109SJoseph Chen #define GPIO_BANK_PINS			32
15560848109SJoseph Chen 
156*0b4bf976SJoseph Chen #elif defined(CONFIG_ROCKCHIP_RK3308)
157*0b4bf976SJoseph Chen #define GPIO0_PHYS			0xff220000
158*0b4bf976SJoseph Chen #define GPIO1_PHYS			0xff230000
159*0b4bf976SJoseph Chen #define GPIO2_PHYS			0xff240000
160*0b4bf976SJoseph Chen #define GPIO3_PHYS			0xff250000
161*0b4bf976SJoseph Chen #define GPIO4_PHYS			0xff260000
162*0b4bf976SJoseph Chen 
163*0b4bf976SJoseph Chen #define IRQ_TIMER1			58	/* ch0 ns timer1 */
164*0b4bf976SJoseph Chen #define IRQ_GPIO0			72
165*0b4bf976SJoseph Chen #define IRQ_GPIO1			73
166*0b4bf976SJoseph Chen #define IRQ_GPIO2			74
167*0b4bf976SJoseph Chen #define IRQ_GPIO3			75
168*0b4bf976SJoseph Chen #define IRQ_GPIO4			76
169*0b4bf976SJoseph Chen 
170*0b4bf976SJoseph Chen #define GIC_IRQS_NR			(5 * 32)
171*0b4bf976SJoseph Chen #define GPIO_IRQS_NR			(5 * 32)
172*0b4bf976SJoseph Chen 
173*0b4bf976SJoseph Chen #define GPIO_BANK_NUM			5
174*0b4bf976SJoseph Chen #define GPIO_BANK_PINS			32
1754e6670feSJoseph Chen #else
1764e6670feSJoseph Chen "Missing define RIQ relative things"
1774e6670feSJoseph Chen #endif
1784e6670feSJoseph Chen 
1794e6670feSJoseph Chen #endif /* _ROCKCHIP_PLAT_IRQ_H_ */
180