1*511ed5fdSRajeshwari Shinde /* 2*511ed5fdSRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 3*511ed5fdSRajeshwari Shinde * R. Chandrasekar <rcsekar@samsung.com> 4*511ed5fdSRajeshwari Shinde * 5*511ed5fdSRajeshwari Shinde * See file CREDITS for list of people who contributed to this 6*511ed5fdSRajeshwari Shinde * project. 7*511ed5fdSRajeshwari Shinde * 8*511ed5fdSRajeshwari Shinde * This program is free software; you can redistribute it and/or 9*511ed5fdSRajeshwari Shinde * modify it under the terms of the GNU General Public License as 10*511ed5fdSRajeshwari Shinde * published by the Free Software Foundation; either version 2 of 11*511ed5fdSRajeshwari Shinde * the License, or (at your option) any later version. 12*511ed5fdSRajeshwari Shinde * 13*511ed5fdSRajeshwari Shinde * This program is distributed in the hope that it will be useful, 14*511ed5fdSRajeshwari Shinde * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*511ed5fdSRajeshwari Shinde * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*511ed5fdSRajeshwari Shinde * GNU General Public License for more details. 17*511ed5fdSRajeshwari Shinde * 18*511ed5fdSRajeshwari Shinde * You should have received a copy of the GNU General Public License 19*511ed5fdSRajeshwari Shinde * along with this program; if not, write to the Free Software 20*511ed5fdSRajeshwari Shinde * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*511ed5fdSRajeshwari Shinde * MA 02111-1307 USA 22*511ed5fdSRajeshwari Shinde */ 23*511ed5fdSRajeshwari Shinde 24*511ed5fdSRajeshwari Shinde #ifndef __I2S_H__ 25*511ed5fdSRajeshwari Shinde #define __I2S_H__ 26*511ed5fdSRajeshwari Shinde 27*511ed5fdSRajeshwari Shinde /* 28*511ed5fdSRajeshwari Shinde * DAI hardware audio formats. 29*511ed5fdSRajeshwari Shinde * 30*511ed5fdSRajeshwari Shinde * Describes the physical PCM data formating and clocking. Add new formats 31*511ed5fdSRajeshwari Shinde * to the end. 32*511ed5fdSRajeshwari Shinde */ 33*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_I2S 1 /* I2S mode */ 34*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */ 35*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */ 36*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */ 37*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */ 38*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_AC97 6 /* AC97 */ 39*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */ 40*511ed5fdSRajeshwari Shinde 41*511ed5fdSRajeshwari Shinde /* left and right justified also known as MSB and LSB respectively */ 42*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J 43*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J 44*511ed5fdSRajeshwari Shinde 45*511ed5fdSRajeshwari Shinde /* 46*511ed5fdSRajeshwari Shinde * DAI hardware signal inversions. 47*511ed5fdSRajeshwari Shinde * 48*511ed5fdSRajeshwari Shinde * Specifies whether the DAI can also support inverted clocks for the specified 49*511ed5fdSRajeshwari Shinde * format. 50*511ed5fdSRajeshwari Shinde */ 51*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */ 52*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ 53*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ 54*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ 55*511ed5fdSRajeshwari Shinde 56*511ed5fdSRajeshwari Shinde /* 57*511ed5fdSRajeshwari Shinde * DAI hardware clock masters. 58*511ed5fdSRajeshwari Shinde * 59*511ed5fdSRajeshwari Shinde * This is wrt the codec, the inverse is true for the interface 60*511ed5fdSRajeshwari Shinde * i.e. if the codec is clk and FRM master then the interface is 61*511ed5fdSRajeshwari Shinde * clk and frame slave. 62*511ed5fdSRajeshwari Shinde */ 63*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */ 64*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */ 65*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */ 66*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */ 67*511ed5fdSRajeshwari Shinde 68*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_FORMAT_MASK 0x000f 69*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 70*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_INV_MASK 0x0f00 71*511ed5fdSRajeshwari Shinde #define SND_SOC_DAIFMT_MASTER_MASK 0xf000 72*511ed5fdSRajeshwari Shinde 73*511ed5fdSRajeshwari Shinde /* 74*511ed5fdSRajeshwari Shinde * Master Clock Directions 75*511ed5fdSRajeshwari Shinde */ 76*511ed5fdSRajeshwari Shinde #define SND_SOC_CLOCK_IN 0 77*511ed5fdSRajeshwari Shinde #define SND_SOC_CLOCK_OUT 1 78*511ed5fdSRajeshwari Shinde 79*511ed5fdSRajeshwari Shinde /* I2S Tx Control */ 80*511ed5fdSRajeshwari Shinde #define I2S_TX_ON 1 81*511ed5fdSRajeshwari Shinde #define I2S_TX_OFF 0 82*511ed5fdSRajeshwari Shinde 83*511ed5fdSRajeshwari Shinde #define FIFO_LENGTH 64 84*511ed5fdSRajeshwari Shinde 85*511ed5fdSRajeshwari Shinde /* I2s Registers */ 86*511ed5fdSRajeshwari Shinde struct i2s_reg { 87*511ed5fdSRajeshwari Shinde unsigned int con; /* base + 0 , Control register */ 88*511ed5fdSRajeshwari Shinde unsigned int mod; /* Mode register */ 89*511ed5fdSRajeshwari Shinde unsigned int fic; /* FIFO control register */ 90*511ed5fdSRajeshwari Shinde unsigned int psr; /* Reserved */ 91*511ed5fdSRajeshwari Shinde unsigned int txd; /* Transmit data register */ 92*511ed5fdSRajeshwari Shinde unsigned int rxd; /* Receive Data Register */ 93*511ed5fdSRajeshwari Shinde }; 94*511ed5fdSRajeshwari Shinde 95*511ed5fdSRajeshwari Shinde /* This structure stores the i2s related information */ 96*511ed5fdSRajeshwari Shinde struct i2stx_info { 97*511ed5fdSRajeshwari Shinde unsigned int rfs; /* LR clock frame size */ 98*511ed5fdSRajeshwari Shinde unsigned int bfs; /* Bit slock frame size */ 99*511ed5fdSRajeshwari Shinde unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ 100*511ed5fdSRajeshwari Shinde unsigned int samplingrate; /* sampling rate */ 101*511ed5fdSRajeshwari Shinde unsigned int bitspersample; /* bits per sample */ 102*511ed5fdSRajeshwari Shinde unsigned int channels; /* audio channels */ 103*511ed5fdSRajeshwari Shinde unsigned int base_address; /* I2S Register Base */ 104*511ed5fdSRajeshwari Shinde }; 105*511ed5fdSRajeshwari Shinde 106*511ed5fdSRajeshwari Shinde /* 107*511ed5fdSRajeshwari Shinde * Sends the given data through i2s tx 108*511ed5fdSRajeshwari Shinde * 109*511ed5fdSRajeshwari Shinde * @param pi2s_tx pointer of i2s transmitter parameter structure. 110*511ed5fdSRajeshwari Shinde * @param data address of the data buffer 111*511ed5fdSRajeshwari Shinde * @param data_size array size of the int buffer (total size / size of int) 112*511ed5fdSRajeshwari Shinde * 113*511ed5fdSRajeshwari Shinde * @return int value 0 for success, -1 in case of error 114*511ed5fdSRajeshwari Shinde */ 115*511ed5fdSRajeshwari Shinde int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data, 116*511ed5fdSRajeshwari Shinde unsigned long data_size); 117*511ed5fdSRajeshwari Shinde 118*511ed5fdSRajeshwari Shinde /* 119*511ed5fdSRajeshwari Shinde * Initialise i2s transmiter 120*511ed5fdSRajeshwari Shinde * 121*511ed5fdSRajeshwari Shinde * @param pi2s_tx pointer of i2s transmitter parameter structure. 122*511ed5fdSRajeshwari Shinde * 123*511ed5fdSRajeshwari Shinde * @return int value 0 for success, -1 in case of error 124*511ed5fdSRajeshwari Shinde */ 125*511ed5fdSRajeshwari Shinde int i2s_tx_init(struct i2stx_info *pi2s_tx); 126*511ed5fdSRajeshwari Shinde 127*511ed5fdSRajeshwari Shinde #endif /* __I2S_H__ */ 128