1 /* 2 * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 20 */ 21 #ifndef _ASM_GT64120_H 22 #define _ASM_GT64120_H 23 24 #define MSK(n) ((1 << (n)) - 1) 25 26 /* 27 * Register offset addresses 28 */ 29 /* CPU Configuration. */ 30 #define GT_CPU_OFS 0x000 31 32 #define GT_MULTI_OFS 0x120 33 34 /* CPU Address Decode. */ 35 #define GT_SCS10LD_OFS 0x008 36 #define GT_SCS10HD_OFS 0x010 37 #define GT_SCS32LD_OFS 0x018 38 #define GT_SCS32HD_OFS 0x020 39 #define GT_CS20LD_OFS 0x028 40 #define GT_CS20HD_OFS 0x030 41 #define GT_CS3BOOTLD_OFS 0x038 42 #define GT_CS3BOOTHD_OFS 0x040 43 #define GT_PCI0IOLD_OFS 0x048 44 #define GT_PCI0IOHD_OFS 0x050 45 #define GT_PCI0M0LD_OFS 0x058 46 #define GT_PCI0M0HD_OFS 0x060 47 #define GT_ISD_OFS 0x068 48 49 #define GT_PCI0M1LD_OFS 0x080 50 #define GT_PCI0M1HD_OFS 0x088 51 #define GT_PCI1IOLD_OFS 0x090 52 #define GT_PCI1IOHD_OFS 0x098 53 #define GT_PCI1M0LD_OFS 0x0a0 54 #define GT_PCI1M0HD_OFS 0x0a8 55 #define GT_PCI1M1LD_OFS 0x0b0 56 #define GT_PCI1M1HD_OFS 0x0b8 57 #define GT_PCI1M1LD_OFS 0x0b0 58 #define GT_PCI1M1HD_OFS 0x0b8 59 60 #define GT_SCS10AR_OFS 0x0d0 61 #define GT_SCS32AR_OFS 0x0d8 62 #define GT_CS20R_OFS 0x0e0 63 #define GT_CS3BOOTR_OFS 0x0e8 64 65 #define GT_PCI0IOREMAP_OFS 0x0f0 66 #define GT_PCI0M0REMAP_OFS 0x0f8 67 #define GT_PCI0M1REMAP_OFS 0x100 68 #define GT_PCI1IOREMAP_OFS 0x108 69 #define GT_PCI1M0REMAP_OFS 0x110 70 #define GT_PCI1M1REMAP_OFS 0x118 71 72 /* CPU Error Report. */ 73 #define GT_CPUERR_ADDRLO_OFS 0x070 74 #define GT_CPUERR_ADDRHI_OFS 0x078 75 76 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ 77 #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ 78 #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ 79 80 /* CPU Sync Barrier. */ 81 #define GT_PCI0SYNC_OFS 0x0c0 82 #define GT_PCI1SYNC_OFS 0x0c8 83 84 /* SDRAM and Device Address Decode. */ 85 #define GT_SCS0LD_OFS 0x400 86 #define GT_SCS0HD_OFS 0x404 87 #define GT_SCS1LD_OFS 0x408 88 #define GT_SCS1HD_OFS 0x40c 89 #define GT_SCS2LD_OFS 0x410 90 #define GT_SCS2HD_OFS 0x414 91 #define GT_SCS3LD_OFS 0x418 92 #define GT_SCS3HD_OFS 0x41c 93 #define GT_CS0LD_OFS 0x420 94 #define GT_CS0HD_OFS 0x424 95 #define GT_CS1LD_OFS 0x428 96 #define GT_CS1HD_OFS 0x42c 97 #define GT_CS2LD_OFS 0x430 98 #define GT_CS2HD_OFS 0x434 99 #define GT_CS3LD_OFS 0x438 100 #define GT_CS3HD_OFS 0x43c 101 #define GT_BOOTLD_OFS 0x440 102 #define GT_BOOTHD_OFS 0x444 103 104 #define GT_ADERR_OFS 0x470 105 106 /* SDRAM Configuration. */ 107 #define GT_SDRAM_CFG_OFS 0x448 108 109 #define GT_SDRAM_OPMODE_OFS 0x474 110 #define GT_SDRAM_BM_OFS 0x478 111 #define GT_SDRAM_ADDRDECODE_OFS 0x47c 112 113 /* SDRAM Parameters. */ 114 #define GT_SDRAM_B0_OFS 0x44c 115 #define GT_SDRAM_B1_OFS 0x450 116 #define GT_SDRAM_B2_OFS 0x454 117 #define GT_SDRAM_B3_OFS 0x458 118 119 /* Device Parameters. */ 120 #define GT_DEV_B0_OFS 0x45c 121 #define GT_DEV_B1_OFS 0x460 122 #define GT_DEV_B2_OFS 0x464 123 #define GT_DEV_B3_OFS 0x468 124 #define GT_DEV_BOOT_OFS 0x46c 125 126 /* ECC. */ 127 #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ 128 #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ 129 #define GT_ECC_MEM 0x488 /* GT-64120A only */ 130 #define GT_ECC_CALC 0x48c /* GT-64120A only */ 131 #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ 132 133 /* DMA Record. */ 134 #define GT_DMA0_CNT_OFS 0x800 135 #define GT_DMA1_CNT_OFS 0x804 136 #define GT_DMA2_CNT_OFS 0x808 137 #define GT_DMA3_CNT_OFS 0x80c 138 #define GT_DMA0_SA_OFS 0x810 139 #define GT_DMA1_SA_OFS 0x814 140 #define GT_DMA2_SA_OFS 0x818 141 #define GT_DMA3_SA_OFS 0x81c 142 #define GT_DMA0_DA_OFS 0x820 143 #define GT_DMA1_DA_OFS 0x824 144 #define GT_DMA2_DA_OFS 0x828 145 #define GT_DMA3_DA_OFS 0x82c 146 #define GT_DMA0_NEXT_OFS 0x830 147 #define GT_DMA1_NEXT_OFS 0x834 148 #define GT_DMA2_NEXT_OFS 0x838 149 #define GT_DMA3_NEXT_OFS 0x83c 150 151 #define GT_DMA0_CUR_OFS 0x870 152 #define GT_DMA1_CUR_OFS 0x874 153 #define GT_DMA2_CUR_OFS 0x878 154 #define GT_DMA3_CUR_OFS 0x87c 155 156 /* DMA Channel Control. */ 157 #define GT_DMA0_CTRL_OFS 0x840 158 #define GT_DMA1_CTRL_OFS 0x844 159 #define GT_DMA2_CTRL_OFS 0x848 160 #define GT_DMA3_CTRL_OFS 0x84c 161 162 /* DMA Arbiter. */ 163 #define GT_DMA_ARB_OFS 0x860 164 165 /* Timer/Counter. */ 166 #define GT_TC0_OFS 0x850 167 #define GT_TC1_OFS 0x854 168 #define GT_TC2_OFS 0x858 169 #define GT_TC3_OFS 0x85c 170 171 #define GT_TC_CONTROL_OFS 0x864 172 173 /* PCI Internal. */ 174 #define GT_PCI0_CMD_OFS 0xc00 175 #define GT_PCI0_TOR_OFS 0xc04 176 #define GT_PCI0_BS_SCS10_OFS 0xc08 177 #define GT_PCI0_BS_SCS32_OFS 0xc0c 178 #define GT_PCI0_BS_CS20_OFS 0xc10 179 #define GT_PCI0_BS_CS3BT_OFS 0xc14 180 181 #define GT_PCI1_IACK_OFS 0xc30 182 #define GT_PCI0_IACK_OFS 0xc34 183 184 #define GT_PCI0_BARE_OFS 0xc3c 185 #define GT_PCI0_PREFMBR_OFS 0xc40 186 187 #define GT_PCI0_SCS10_BAR_OFS 0xc48 188 #define GT_PCI0_SCS32_BAR_OFS 0xc4c 189 #define GT_PCI0_CS20_BAR_OFS 0xc50 190 #define GT_PCI0_CS3BT_BAR_OFS 0xc54 191 #define GT_PCI0_SSCS10_BAR_OFS 0xc58 192 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c 193 194 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 195 196 #define GT_PCI1_CMD_OFS 0xc80 197 #define GT_PCI1_TOR_OFS 0xc84 198 #define GT_PCI1_BS_SCS10_OFS 0xc88 199 #define GT_PCI1_BS_SCS32_OFS 0xc8c 200 #define GT_PCI1_BS_CS20_OFS 0xc90 201 #define GT_PCI1_BS_CS3BT_OFS 0xc94 202 203 #define GT_PCI1_BARE_OFS 0xcbc 204 #define GT_PCI1_PREFMBR_OFS 0xcc0 205 206 #define GT_PCI1_SCS10_BAR_OFS 0xcc8 207 #define GT_PCI1_SCS32_BAR_OFS 0xccc 208 #define GT_PCI1_CS20_BAR_OFS 0xcd0 209 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 210 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 211 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc 212 213 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 214 215 #define GT_PCI1_CFGADDR_OFS 0xcf0 216 #define GT_PCI1_CFGDATA_OFS 0xcf4 217 #define GT_PCI0_CFGADDR_OFS 0xcf8 218 #define GT_PCI0_CFGDATA_OFS 0xcfc 219 220 /* Interrupts. */ 221 #define GT_INTRCAUSE_OFS 0xc18 222 #define GT_INTRMASK_OFS 0xc1c 223 224 #define GT_PCI0_ICMASK_OFS 0xc24 225 #define GT_PCI0_SERR0MASK_OFS 0xc28 226 227 #define GT_CPU_INTSEL_OFS 0xc70 228 #define GT_PCI0_INTSEL_OFS 0xc74 229 230 #define GT_HINTRCAUSE_OFS 0xc98 231 #define GT_HINTRMASK_OFS 0xc9c 232 233 #define GT_PCI0_HICMASK_OFS 0xca4 234 #define GT_PCI1_SERR1MASK_OFS 0xca8 235 236 237 /* 238 * I2O Support Registers 239 */ 240 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 241 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 242 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 243 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c 244 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 245 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 246 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 247 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c 248 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 249 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 250 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 251 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 252 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 253 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 254 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 255 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 256 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 257 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c 258 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 259 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 260 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 261 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c 262 263 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 264 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 265 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 266 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c 267 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 268 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 269 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 270 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c 271 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 272 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 273 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 274 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 275 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 276 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 277 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 278 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 279 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 280 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c 281 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 282 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 283 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 284 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c 285 286 /* 287 * Register encodings 288 */ 289 #define GT_CPU_ENDIAN_SHF 12 290 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) 291 #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK 292 #define GT_CPU_WR_SHF 16 293 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) 294 #define GT_CPU_WR_BIT GT_CPU_WR_MSK 295 #define GT_CPU_WR_DXDXDXDX 0 296 #define GT_CPU_WR_DDDD 1 297 298 299 #define GT_PCI_DCRM_SHF 21 300 #define GT_PCI_LD_SHF 0 301 #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) 302 #define GT_PCI_HD_SHF 0 303 #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) 304 #define GT_PCI_REMAP_SHF 0 305 #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) 306 307 308 #define GT_CFGADDR_CFGEN_SHF 31 309 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) 310 #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK 311 312 #define GT_CFGADDR_BUSNUM_SHF 16 313 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) 314 315 #define GT_CFGADDR_DEVNUM_SHF 11 316 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) 317 318 #define GT_CFGADDR_FUNCNUM_SHF 8 319 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) 320 321 #define GT_CFGADDR_REGNUM_SHF 2 322 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) 323 324 325 #define GT_SDRAM_BM_ORDER_SHF 2 326 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) 327 #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK 328 #define GT_SDRAM_BM_ORDER_SUB 1 329 #define GT_SDRAM_BM_ORDER_LIN 0 330 331 #define GT_SDRAM_BM_RSVD_ALL1 0xffb 332 333 334 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 335 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) 336 #define GT_SDRAM_ADDRDECODE_ADDR_0 0 337 #define GT_SDRAM_ADDRDECODE_ADDR_1 1 338 #define GT_SDRAM_ADDRDECODE_ADDR_2 2 339 #define GT_SDRAM_ADDRDECODE_ADDR_3 3 340 #define GT_SDRAM_ADDRDECODE_ADDR_4 4 341 #define GT_SDRAM_ADDRDECODE_ADDR_5 5 342 #define GT_SDRAM_ADDRDECODE_ADDR_6 6 343 #define GT_SDRAM_ADDRDECODE_ADDR_7 7 344 345 346 #define GT_SDRAM_B0_CASLAT_SHF 0 347 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) 348 #define GT_SDRAM_B0_CASLAT_2 1 349 #define GT_SDRAM_B0_CASLAT_3 2 350 351 #define GT_SDRAM_B0_FTDIS_SHF 2 352 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) 353 #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK 354 355 #define GT_SDRAM_B0_SRASPRCHG_SHF 3 356 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) 357 #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK 358 #define GT_SDRAM_B0_SRASPRCHG_2 0 359 #define GT_SDRAM_B0_SRASPRCHG_3 1 360 361 #define GT_SDRAM_B0_B0COMPAB_SHF 4 362 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) 363 #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK 364 365 #define GT_SDRAM_B0_64BITINT_SHF 5 366 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) 367 #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK 368 #define GT_SDRAM_B0_64BITINT_2 0 369 #define GT_SDRAM_B0_64BITINT_4 1 370 371 #define GT_SDRAM_B0_BW_SHF 6 372 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) 373 #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK 374 #define GT_SDRAM_B0_BW_32 0 375 #define GT_SDRAM_B0_BW_64 1 376 377 #define GT_SDRAM_B0_BLODD_SHF 7 378 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) 379 #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK 380 381 #define GT_SDRAM_B0_PAR_SHF 8 382 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) 383 #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK 384 385 #define GT_SDRAM_B0_BYPASS_SHF 9 386 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) 387 #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK 388 389 #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 390 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) 391 #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK 392 #define GT_SDRAM_B0_SRAS2SCAS_2 0 393 #define GT_SDRAM_B0_SRAS2SCAS_3 1 394 395 #define GT_SDRAM_B0_SIZE_SHF 11 396 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) 397 #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK 398 #define GT_SDRAM_B0_SIZE_16M 0 399 #define GT_SDRAM_B0_SIZE_64M 1 400 401 #define GT_SDRAM_B0_EXTPAR_SHF 12 402 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) 403 #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK 404 405 #define GT_SDRAM_B0_BLEN_SHF 13 406 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) 407 #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK 408 #define GT_SDRAM_B0_BLEN_8 0 409 #define GT_SDRAM_B0_BLEN_4 1 410 411 412 #define GT_SDRAM_CFG_REFINT_SHF 0 413 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) 414 415 #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 416 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) 417 #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK 418 419 #define GT_SDRAM_CFG_RMW_SHF 15 420 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) 421 #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK 422 423 #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 424 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) 425 #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK 426 427 #define GT_SDRAM_CFG_DUPCNTL_SHF 19 428 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) 429 #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK 430 431 #define GT_SDRAM_CFG_DUPBA_SHF 20 432 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) 433 #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK 434 435 #define GT_SDRAM_CFG_DUPEOT0_SHF 21 436 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) 437 #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK 438 439 #define GT_SDRAM_CFG_DUPEOT1_SHF 22 440 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) 441 #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK 442 443 #define GT_SDRAM_OPMODE_OP_SHF 0 444 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) 445 #define GT_SDRAM_OPMODE_OP_NORMAL 0 446 #define GT_SDRAM_OPMODE_OP_NOP 1 447 #define GT_SDRAM_OPMODE_OP_PRCHG 2 448 #define GT_SDRAM_OPMODE_OP_MODE 3 449 #define GT_SDRAM_OPMODE_OP_CBR 4 450 451 #define GT_TC_CONTROL_ENTC0_SHF 0 452 #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) 453 #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK 454 #define GT_TC_CONTROL_SELTC0_SHF 1 455 #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) 456 #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK 457 458 459 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 460 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \ 461 (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 462 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK 463 464 #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 465 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) 466 #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK 467 468 #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 469 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) 470 #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK 471 472 #define GT_PCI0_BARE_INTIODIS_SHF 3 473 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) 474 #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK 475 476 #define GT_PCI0_BARE_INTMEMDIS_SHF 4 477 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) 478 #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK 479 480 #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 481 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) 482 #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK 483 484 #define GT_PCI0_BARE_CS20DIS_SHF 6 485 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) 486 #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK 487 488 #define GT_PCI0_BARE_SCS32DIS_SHF 7 489 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) 490 #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK 491 492 #define GT_PCI0_BARE_SCS10DIS_SHF 8 493 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) 494 #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK 495 496 497 #define GT_INTRCAUSE_MASABORT0_SHF 18 498 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) 499 #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK 500 501 #define GT_INTRCAUSE_TARABORT0_SHF 19 502 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) 503 #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK 504 505 506 #define GT_PCI0_CFGADDR_REGNUM_SHF 2 507 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) 508 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 509 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) 510 #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 511 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) 512 #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 513 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) 514 #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 515 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) 516 #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK 517 518 #define GT_PCI0_CMD_MBYTESWAP_SHF 0 519 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) 520 #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK 521 #define GT_PCI0_CMD_MWORDSWAP_SHF 10 522 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) 523 #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK 524 #define GT_PCI0_CMD_SBYTESWAP_SHF 16 525 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) 526 #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK 527 #define GT_PCI0_CMD_SWORDSWAP_SHF 11 528 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 529 #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 530 531 #define GT_INTR_T0EXP_SHF 8 532 #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) 533 #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK 534 #define GT_INTR_RETRYCTR0_SHF 20 535 #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) 536 #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK 537 538 /* 539 * Misc 540 */ 541 #define GT_DEF_PCI0_IO_BASE 0x10000000 542 #define GT_DEF_PCI0_IO_SIZE 0x02000000 543 #define GT_DEF_PCI0_MEM0_BASE 0x12000000 544 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000 545 #define GT_DEF_BASE 0x14000000 546 547 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ 548 #define GT_LATTIM_MIN 6 /* Minimum lat */ 549 550 #endif /* _ASM_GT64120_H */ 551