xref: /rk3399_rockchip-uboot/include/fsl_sfp.h (revision a2e225e65df3d0fe0ddefec77a3db05b881d1e68)
1*a2e225e6Sgaurav rana /*
2*a2e225e6Sgaurav rana  * Copyright 2015 Freescale Semiconductor, Inc.
3*a2e225e6Sgaurav rana  *
4*a2e225e6Sgaurav rana  * SPDX-License-Identifier:	GPL-2.0+
5*a2e225e6Sgaurav rana  */
6*a2e225e6Sgaurav rana 
7*a2e225e6Sgaurav rana #ifndef _FSL_SFP_SNVS_
8*a2e225e6Sgaurav rana #define _FSL_SFP_SNVS_
9*a2e225e6Sgaurav rana 
10*a2e225e6Sgaurav rana #include <common.h>
11*a2e225e6Sgaurav rana #include <config.h>
12*a2e225e6Sgaurav rana #include <asm/io.h>
13*a2e225e6Sgaurav rana 
14*a2e225e6Sgaurav rana #ifdef CONFIG_SYS_FSL_SRK_LE
15*a2e225e6Sgaurav rana #define srk_in32(a)       in_le32(a)
16*a2e225e6Sgaurav rana #else
17*a2e225e6Sgaurav rana #define srk_in32(a)       in_be32(a)
18*a2e225e6Sgaurav rana #endif
19*a2e225e6Sgaurav rana 
20*a2e225e6Sgaurav rana #ifdef CONFIG_SYS_FSL_SFP_LE
21*a2e225e6Sgaurav rana #define sfp_in32(a)       in_le32(a)
22*a2e225e6Sgaurav rana #define sfp_out32(a, v)   out_le32(a, v)
23*a2e225e6Sgaurav rana #define sfp_in16(a)       in_le16(a)
24*a2e225e6Sgaurav rana #elif defined(CONFIG_SYS_FSL_SFP_BE)
25*a2e225e6Sgaurav rana #define sfp_in32(a)       in_be32(a)
26*a2e225e6Sgaurav rana #define sfp_out32(a, v)   out_be32(a, v)
27*a2e225e6Sgaurav rana #define sfp_in16(a)       in_be16(a)
28*a2e225e6Sgaurav rana #else
29*a2e225e6Sgaurav rana #error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
30*a2e225e6Sgaurav rana #endif
31*a2e225e6Sgaurav rana 
32*a2e225e6Sgaurav rana /* Number of SRKH registers */
33*a2e225e6Sgaurav rana #define NUM_SRKH_REGS	8
34*a2e225e6Sgaurav rana 
35*a2e225e6Sgaurav rana #ifdef CONFIG_SYS_FSL_SFP_VER_3_2
36*a2e225e6Sgaurav rana struct ccsr_sfp_regs {
37*a2e225e6Sgaurav rana 	u32 ospr;		/* 0x200 */
38*a2e225e6Sgaurav rana 	u32 ospr1;		/* 0x204 */
39*a2e225e6Sgaurav rana 	u32 reserved1[4];
40*a2e225e6Sgaurav rana 	u32 fswpr;		/* 0x218 FSL Section Write Protect */
41*a2e225e6Sgaurav rana 	u32 fsl_uid;		/* 0x21c FSL UID 0 */
42*a2e225e6Sgaurav rana 	u32 fsl_uid_1;		/* 0x220 FSL UID 0 */
43*a2e225e6Sgaurav rana 	u32 reserved2[12];
44*a2e225e6Sgaurav rana 	u32 srk_hash[8];	/* 0x254 Super Root Key Hash */
45*a2e225e6Sgaurav rana 	u32 oem_uid;		/* 0x274 OEM UID 0*/
46*a2e225e6Sgaurav rana 	u32 oem_uid_1;		/* 0x278 OEM UID 1*/
47*a2e225e6Sgaurav rana 	u32 oem_uid_2;		/* 0x27c OEM UID 2*/
48*a2e225e6Sgaurav rana 	u32 oem_uid_3;		/* 0x280 OEM UID 3*/
49*a2e225e6Sgaurav rana 	u32 oem_uid_4;		/* 0x284 OEM UID 4*/
50*a2e225e6Sgaurav rana 	u32 reserved3[8];
51*a2e225e6Sgaurav rana };
52*a2e225e6Sgaurav rana #elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
53*a2e225e6Sgaurav rana struct ccsr_sfp_regs {
54*a2e225e6Sgaurav rana 	u32 ospr;		/* 0x200 */
55*a2e225e6Sgaurav rana 	u32 reserved0[14];
56*a2e225e6Sgaurav rana 	u32 srk_hash[NUM_SRKH_REGS];	/* 0x23c Super Root Key Hash */
57*a2e225e6Sgaurav rana 	u32 oem_uid;		/* 0x9c OEM Unique ID */
58*a2e225e6Sgaurav rana 	u8 reserved2[0x04];
59*a2e225e6Sgaurav rana 	u32 ovpr;			/* 0xA4  Intent To Secure */
60*a2e225e6Sgaurav rana 	u8 reserved4[0x08];
61*a2e225e6Sgaurav rana 	u32 fsl_uid;		/* 0xB0  FSL Unique ID */
62*a2e225e6Sgaurav rana 	u8 reserved5[0x04];
63*a2e225e6Sgaurav rana 	u32 fsl_spfr0;		/* Scratch Pad Fuse Register 0 */
64*a2e225e6Sgaurav rana 	u32 fsl_spfr1;		/* Scratch Pad Fuse Register 1 */
65*a2e225e6Sgaurav rana 
66*a2e225e6Sgaurav rana };
67*a2e225e6Sgaurav rana #else
68*a2e225e6Sgaurav rana struct ccsr_sfp_regs {
69*a2e225e6Sgaurav rana 	u8 reserved0[0x40];
70*a2e225e6Sgaurav rana 	u32 ospr;	/* 0x40  OEM Security Policy Register */
71*a2e225e6Sgaurav rana 	u8 reserved2[0x38];
72*a2e225e6Sgaurav rana 	u32 srk_hash[8];	/* 0x7c  Super Root Key Hash */
73*a2e225e6Sgaurav rana 	u32 oem_uid;	/* 0x9c  OEM Unique ID */
74*a2e225e6Sgaurav rana 	u8 reserved4[0x4];
75*a2e225e6Sgaurav rana 	u32 ovpr;	/* 0xA4  OEM Validation Policy Register */
76*a2e225e6Sgaurav rana 	u8 reserved8[0x8];
77*a2e225e6Sgaurav rana 	u32 fsl_uid;	/* 0xB0  FSL Unique ID */
78*a2e225e6Sgaurav rana };
79*a2e225e6Sgaurav rana #endif
80*a2e225e6Sgaurav rana #define ITS_MASK	0x00000004
81*a2e225e6Sgaurav rana #define ITS_BIT		2
82*a2e225e6Sgaurav rana #define OSPR_KEY_REVOC_SHIFT	13
83*a2e225e6Sgaurav rana #define OSPR_KEY_REVOC_MASK	0x0000e000
84*a2e225e6Sgaurav rana 
85*a2e225e6Sgaurav rana #endif
86