1a2e225e6Sgaurav rana /* 2a2e225e6Sgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 3a2e225e6Sgaurav rana * 4a2e225e6Sgaurav rana * SPDX-License-Identifier: GPL-2.0+ 5a2e225e6Sgaurav rana */ 6a2e225e6Sgaurav rana 7a2e225e6Sgaurav rana #ifndef _FSL_SFP_SNVS_ 8a2e225e6Sgaurav rana #define _FSL_SFP_SNVS_ 9a2e225e6Sgaurav rana 10a2e225e6Sgaurav rana #include <common.h> 11a2e225e6Sgaurav rana #include <config.h> 12a2e225e6Sgaurav rana #include <asm/io.h> 13a2e225e6Sgaurav rana 14a2e225e6Sgaurav rana #ifdef CONFIG_SYS_FSL_SRK_LE 15a2e225e6Sgaurav rana #define srk_in32(a) in_le32(a) 16a2e225e6Sgaurav rana #else 17a2e225e6Sgaurav rana #define srk_in32(a) in_be32(a) 18a2e225e6Sgaurav rana #endif 19a2e225e6Sgaurav rana 20a2e225e6Sgaurav rana #ifdef CONFIG_SYS_FSL_SFP_LE 21a2e225e6Sgaurav rana #define sfp_in32(a) in_le32(a) 22a2e225e6Sgaurav rana #define sfp_out32(a, v) out_le32(a, v) 23a2e225e6Sgaurav rana #define sfp_in16(a) in_le16(a) 24a2e225e6Sgaurav rana #elif defined(CONFIG_SYS_FSL_SFP_BE) 25a2e225e6Sgaurav rana #define sfp_in32(a) in_be32(a) 26a2e225e6Sgaurav rana #define sfp_out32(a, v) out_be32(a, v) 27a2e225e6Sgaurav rana #define sfp_in16(a) in_be16(a) 28a2e225e6Sgaurav rana #else 29a2e225e6Sgaurav rana #error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined 30a2e225e6Sgaurav rana #endif 31a2e225e6Sgaurav rana 32a2e225e6Sgaurav rana /* Number of SRKH registers */ 33a2e225e6Sgaurav rana #define NUM_SRKH_REGS 8 34a2e225e6Sgaurav rana 353808190aSSaksham Jain #if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \ 363808190aSSaksham Jain defined(CONFIG_SYS_FSL_SFP_VER_3_4) 37a2e225e6Sgaurav rana struct ccsr_sfp_regs { 38a2e225e6Sgaurav rana u32 ospr; /* 0x200 */ 39a2e225e6Sgaurav rana u32 ospr1; /* 0x204 */ 40a2e225e6Sgaurav rana u32 reserved1[4]; 41a2e225e6Sgaurav rana u32 fswpr; /* 0x218 FSL Section Write Protect */ 42a2e225e6Sgaurav rana u32 fsl_uid; /* 0x21c FSL UID 0 */ 43a2e225e6Sgaurav rana u32 fsl_uid_1; /* 0x220 FSL UID 0 */ 44a2e225e6Sgaurav rana u32 reserved2[12]; 45a2e225e6Sgaurav rana u32 srk_hash[8]; /* 0x254 Super Root Key Hash */ 46a2e225e6Sgaurav rana u32 oem_uid; /* 0x274 OEM UID 0*/ 47a2e225e6Sgaurav rana u32 oem_uid_1; /* 0x278 OEM UID 1*/ 48a2e225e6Sgaurav rana u32 oem_uid_2; /* 0x27c OEM UID 2*/ 49a2e225e6Sgaurav rana u32 oem_uid_3; /* 0x280 OEM UID 3*/ 50a2e225e6Sgaurav rana u32 oem_uid_4; /* 0x284 OEM UID 4*/ 51a2e225e6Sgaurav rana u32 reserved3[8]; 52a2e225e6Sgaurav rana }; 53a2e225e6Sgaurav rana #elif defined(CONFIG_SYS_FSL_SFP_VER_3_0) 54a2e225e6Sgaurav rana struct ccsr_sfp_regs { 55a2e225e6Sgaurav rana u32 ospr; /* 0x200 */ 56a2e225e6Sgaurav rana u32 reserved0[14]; 57a2e225e6Sgaurav rana u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */ 58a2e225e6Sgaurav rana u32 oem_uid; /* 0x9c OEM Unique ID */ 59a2e225e6Sgaurav rana u8 reserved2[0x04]; 60a2e225e6Sgaurav rana u32 ovpr; /* 0xA4 Intent To Secure */ 61a2e225e6Sgaurav rana u8 reserved4[0x08]; 62a2e225e6Sgaurav rana u32 fsl_uid; /* 0xB0 FSL Unique ID */ 63a2e225e6Sgaurav rana u8 reserved5[0x04]; 64a2e225e6Sgaurav rana u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */ 65a2e225e6Sgaurav rana u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */ 66a2e225e6Sgaurav rana 67a2e225e6Sgaurav rana }; 68a2e225e6Sgaurav rana #else 69a2e225e6Sgaurav rana struct ccsr_sfp_regs { 70a2e225e6Sgaurav rana u8 reserved0[0x40]; 71a2e225e6Sgaurav rana u32 ospr; /* 0x40 OEM Security Policy Register */ 72a2e225e6Sgaurav rana u8 reserved2[0x38]; 73a2e225e6Sgaurav rana u32 srk_hash[8]; /* 0x7c Super Root Key Hash */ 74a2e225e6Sgaurav rana u32 oem_uid; /* 0x9c OEM Unique ID */ 75a2e225e6Sgaurav rana u8 reserved4[0x4]; 76a2e225e6Sgaurav rana u32 ovpr; /* 0xA4 OEM Validation Policy Register */ 77a2e225e6Sgaurav rana u8 reserved8[0x8]; 78a2e225e6Sgaurav rana u32 fsl_uid; /* 0xB0 FSL Unique ID */ 79a2e225e6Sgaurav rana }; 80a2e225e6Sgaurav rana #endif 81*abd9c1bbSSumit Garg 82a2e225e6Sgaurav rana #define ITS_MASK 0x00000004 83a2e225e6Sgaurav rana #define ITS_BIT 2 84*abd9c1bbSSumit Garg 85*abd9c1bbSSumit Garg #if defined(CONFIG_SYS_FSL_SFP_VER_3_4) 86*abd9c1bbSSumit Garg #define OSPR_KEY_REVOC_SHIFT 9 87*abd9c1bbSSumit Garg #define OSPR_KEY_REVOC_MASK 0x0000fe00 88*abd9c1bbSSumit Garg #else 89a2e225e6Sgaurav rana #define OSPR_KEY_REVOC_SHIFT 13 90a2e225e6Sgaurav rana #define OSPR_KEY_REVOC_MASK 0x0000e000 91*abd9c1bbSSumit Garg #endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */ 92a2e225e6Sgaurav rana 93a2e225e6Sgaurav rana #endif 94