1*fe78378dSgaurav rana /* 2*fe78378dSgaurav rana * Common internal memory map for some Freescale SoCs 3*fe78378dSgaurav rana * 4*fe78378dSgaurav rana * Copyright 2015 Freescale Semiconductor, Inc. 5*fe78378dSgaurav rana * SPDX-License-Identifier: GPL-2.0+ 6*fe78378dSgaurav rana */ 7*fe78378dSgaurav rana 8*fe78378dSgaurav rana #ifndef __FSL_SEC_MON_H 9*fe78378dSgaurav rana #define __FSL_SEC_MON_H 10*fe78378dSgaurav rana 11*fe78378dSgaurav rana #include <common.h> 12*fe78378dSgaurav rana #include <asm/io.h> 13*fe78378dSgaurav rana 14*fe78378dSgaurav rana #ifdef CONFIG_SYS_FSL_SEC_MON_LE 15*fe78378dSgaurav rana #define sec_mon_in32(a) in_le32(a) 16*fe78378dSgaurav rana #define sec_mon_out32(a, v) out_le32(a, v) 17*fe78378dSgaurav rana #define sec_mon_in16(a) in_le16(a) 18*fe78378dSgaurav rana #define sec_mon_clrbits32 clrbits_le32 19*fe78378dSgaurav rana #define sec_mon_setbits32 setbits_le32 20*fe78378dSgaurav rana #elif defined(CONFIG_SYS_FSL_SEC_MON_BE) 21*fe78378dSgaurav rana #define sec_mon_in32(a) in_be32(a) 22*fe78378dSgaurav rana #define sec_mon_out32(a, v) out_be32(a, v) 23*fe78378dSgaurav rana #define sec_mon_in16(a) in_be16(a) 24*fe78378dSgaurav rana #define sec_mon_clrbits32 clrbits_be32 25*fe78378dSgaurav rana #define sec_mon_setbits32 setbits_be32 26*fe78378dSgaurav rana #else 27*fe78378dSgaurav rana #error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined 28*fe78378dSgaurav rana #endif 29*fe78378dSgaurav rana 30*fe78378dSgaurav rana struct ccsr_sec_mon_regs { 31*fe78378dSgaurav rana u8 reserved0[0x04]; 32*fe78378dSgaurav rana u32 hp_com; /* 0x04 SEC_MON_HP Command Register */ 33*fe78378dSgaurav rana u8 reserved2[0x0c]; 34*fe78378dSgaurav rana u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ 35*fe78378dSgaurav rana }; 36*fe78378dSgaurav rana 37*fe78378dSgaurav rana #define HPCOMR_SW_SV 0x100 /* Security Violation bit */ 38*fe78378dSgaurav rana #define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ 39*fe78378dSgaurav rana #define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ 40*fe78378dSgaurav rana #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ 41*fe78378dSgaurav rana #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ 42*fe78378dSgaurav rana #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ 43*fe78378dSgaurav rana #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ 44*fe78378dSgaurav rana #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ 45*fe78378dSgaurav rana 46*fe78378dSgaurav rana /* 47*fe78378dSgaurav rana * SEC_MON read. This specifies the possible reads 48*fe78378dSgaurav rana * from the SEC_MON 49*fe78378dSgaurav rana */ 50*fe78378dSgaurav rana enum { 51*fe78378dSgaurav rana SEC_MON_SSM_ST, 52*fe78378dSgaurav rana SEC_MON_SW_FSV, 53*fe78378dSgaurav rana SEC_MON_SW_SV, 54*fe78378dSgaurav rana }; 55*fe78378dSgaurav rana 56*fe78378dSgaurav rana int change_sec_mon_state(uint32_t initial_state, uint32_t final_state); 57*fe78378dSgaurav rana 58*fe78378dSgaurav rana #endif /* __FSL_SEC_MON_H */ 59