1 /* 2 * Common internal memory map for some Freescale SoCs 3 * 4 * Copyright 2014 Freescale Semiconductor, Inc. 5 * 6 */ 7 8 #ifndef __FSL_SEC_H 9 #define __FSL_SEC_H 10 11 #include <common.h> 12 #include <asm/io.h> 13 14 #ifdef CONFIG_SYS_FSL_SEC_LE 15 #define sec_in32(a) in_le32(a) 16 #define sec_out32(a, v) out_le32(a, v) 17 #define sec_in16(a) in_le16(a) 18 #define sec_clrbits32 clrbits_le32 19 #define sec_setbits32 setbits_le32 20 #elif defined(CONFIG_SYS_FSL_SEC_BE) 21 #define sec_in32(a) in_be32(a) 22 #define sec_out32(a, v) out_be32(a, v) 23 #define sec_in16(a) in_be16(a) 24 #define sec_clrbits32 clrbits_be32 25 #define sec_setbits32 setbits_be32 26 #else 27 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined 28 #endif 29 30 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 31 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 32 typedef struct ccsr_sec { 33 u32 res0; 34 u32 mcfgr; /* Master CFG Register */ 35 u8 res1[0x4]; 36 u32 scfgr; 37 struct { 38 u32 ms; /* Job Ring LIODN Register, MS */ 39 u32 ls; /* Job Ring LIODN Register, LS */ 40 } jrliodnr[4]; 41 u8 res2[0x2c]; 42 u32 jrstartr; /* Job Ring Start Register */ 43 struct { 44 u32 ms; /* RTIC LIODN Register, MS */ 45 u32 ls; /* RTIC LIODN Register, LS */ 46 } rticliodnr[4]; 47 u8 res3[0x1c]; 48 u32 decorr; /* DECO Request Register */ 49 struct { 50 u32 ms; /* DECO LIODN Register, MS */ 51 u32 ls; /* DECO LIODN Register, LS */ 52 } decoliodnr[8]; 53 u8 res4[0x40]; 54 u32 dar; /* DECO Avail Register */ 55 u32 drr; /* DECO Reset Register */ 56 u8 res5[0xe78]; 57 u32 crnr_ms; /* CHA Revision Number Register, MS */ 58 u32 crnr_ls; /* CHA Revision Number Register, LS */ 59 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 60 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 61 u8 res6[0x10]; 62 u32 far_ms; /* Fault Address Register, MS */ 63 u32 far_ls; /* Fault Address Register, LS */ 64 u32 falr; /* Fault Address LIODN Register */ 65 u32 fadr; /* Fault Address Detail Register */ 66 u8 res7[0x4]; 67 u32 csta; /* CAAM Status Register */ 68 u8 res8[0x8]; 69 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 70 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 71 u32 chavid_ms; /* CHA Version ID Register, MS */ 72 u32 chavid_ls; /* CHA Version ID Register, LS */ 73 u32 chanum_ms; /* CHA Number Register, MS */ 74 u32 chanum_ls; /* CHA Number Register, LS */ 75 u32 secvid_ms; /* SEC Version ID Register, MS */ 76 u32 secvid_ls; /* SEC Version ID Register, LS */ 77 u8 res9[0x6020]; 78 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 79 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 80 u8 res10[0x8fd8]; 81 } ccsr_sec_t; 82 83 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 84 #define SEC_CTPR_MS_QI 0x02000000 85 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 86 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 87 #define SEC_RVID_MA 0x0f000000 88 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 89 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 90 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 91 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 92 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 93 #define SEC_SECVID_MS_IPID_SHIFT 16 94 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 95 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 96 #define SEC_CCBVID_ERA_MASK 0xff000000 97 #define SEC_CCBVID_ERA_SHIFT 24 98 #define SEC_SCFGR_RDBENABLE 0x00000400 99 #define SEC_SCFGR_VIRT_EN 0x00008000 100 #define SEC_CHAVID_LS_RNG_SHIFT 16 101 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 102 103 #define CONFIG_JRSTARTR_JR0 0x00000001 104 105 struct jr_regs { 106 #ifdef CONFIG_SYS_FSL_SEC_LE 107 u32 irba_l; 108 u32 irba_h; 109 #else 110 u32 irba_h; 111 u32 irba_l; 112 #endif 113 u32 rsvd1; 114 u32 irs; 115 u32 rsvd2; 116 u32 irsa; 117 u32 rsvd3; 118 u32 irja; 119 #ifdef CONFIG_SYS_FSL_SEC_LE 120 u32 orba_l; 121 u32 orba_h; 122 #else 123 u32 orba_h; 124 u32 orba_l; 125 #endif 126 u32 rsvd4; 127 u32 ors; 128 u32 rsvd5; 129 u32 orjr; 130 u32 rsvd6; 131 u32 orsf; 132 u32 rsvd7; 133 u32 jrsta; 134 u32 rsvd8; 135 u32 jrint; 136 u32 jrcfg0; 137 u32 jrcfg1; 138 u32 rsvd9; 139 u32 irri; 140 u32 rsvd10; 141 u32 orwi; 142 u32 rsvd11; 143 u32 jrcr; 144 }; 145 146 int sec_init(void); 147 #endif 148 149 #endif /* __FSL_SEC_H */ 150