1063c1263SAndy Fleming /* 2111fd19eSRoy Zang * Copyright 2009-2012 Freescale Semiconductor, Inc. 3063c1263SAndy Fleming * Jun-jie Zhang <b18070@freescale.com> 4063c1263SAndy Fleming * Mingkai Hu <Mingkai.hu@freescale.com> 5063c1263SAndy Fleming * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7063c1263SAndy Fleming */ 8063c1263SAndy Fleming #ifndef __FSL_PHY_H__ 9063c1263SAndy Fleming #define __FSL_PHY_H__ 10063c1263SAndy Fleming 11063c1263SAndy Fleming #include <net.h> 12063c1263SAndy Fleming #include <miiphy.h> 13063c1263SAndy Fleming #include <asm/fsl_enet.h> 14063c1263SAndy Fleming 15063c1263SAndy Fleming /* PHY register offsets */ 16063c1263SAndy Fleming #define PHY_EXT_PAGE_ACCESS 0x1f 17063c1263SAndy Fleming 18063c1263SAndy Fleming /* MII Management Configuration Register */ 19063c1263SAndy Fleming #define MIIMCFG_RESET_MGMT 0x80000000 20063c1263SAndy Fleming #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 21063c1263SAndy Fleming #define MIIMCFG_INIT_VALUE 0x00000003 22063c1263SAndy Fleming 23063c1263SAndy Fleming /* MII Management Command Register */ 24063c1263SAndy Fleming #define MIIMCOM_READ_CYCLE 0x00000001 25063c1263SAndy Fleming #define MIIMCOM_SCAN_CYCLE 0x00000002 26063c1263SAndy Fleming 27063c1263SAndy Fleming /* MII Management Address Register */ 28063c1263SAndy Fleming #define MIIMADD_PHY_ADDR_SHIFT 8 29063c1263SAndy Fleming 30063c1263SAndy Fleming /* MII Management Indicator Register */ 31063c1263SAndy Fleming #define MIIMIND_BUSY 0x00000001 32063c1263SAndy Fleming #define MIIMIND_NOTVALID 0x00000004 33063c1263SAndy Fleming 34063c1263SAndy Fleming void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, 35063c1263SAndy Fleming int dev_addr, int reg, int value); 36063c1263SAndy Fleming int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, 37063c1263SAndy Fleming int dev_addr, int regnum); 38063c1263SAndy Fleming int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); 39063c1263SAndy Fleming int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, 40063c1263SAndy Fleming u16 value); 41111fd19eSRoy Zang int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 42111fd19eSRoy Zang int regnum, u16 value); 43111fd19eSRoy Zang int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 44111fd19eSRoy Zang int regnum); 45063c1263SAndy Fleming 46063c1263SAndy Fleming struct fsl_pq_mdio_info { 47063c1263SAndy Fleming struct tsec_mii_mng *regs; 48063c1263SAndy Fleming char *name; 49063c1263SAndy Fleming }; 50063c1263SAndy Fleming int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); 51063c1263SAndy Fleming 52063c1263SAndy Fleming #endif /* __FSL_PHY_H__ */ 53