1063c1263SAndy Fleming /* 2*111fd19eSRoy Zang * Copyright 2009-2012 Freescale Semiconductor, Inc. 3063c1263SAndy Fleming * Jun-jie Zhang <b18070@freescale.com> 4063c1263SAndy Fleming * Mingkai Hu <Mingkai.hu@freescale.com> 5063c1263SAndy Fleming * 6063c1263SAndy Fleming * This program is free software; you can redistribute it and/or 7063c1263SAndy Fleming * modify it under the terms of the GNU General Public License as 8063c1263SAndy Fleming * published by the Free Software Foundation; either version 2 of 9063c1263SAndy Fleming * the License, or (at your option) any later version. 10063c1263SAndy Fleming * 11063c1263SAndy Fleming * This program is distributed in the hope that it will be useful, 12063c1263SAndy Fleming * but WITHOUT ANY WARRANTY; without even the implied warranty of 13063c1263SAndy Fleming * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14063c1263SAndy Fleming * GNU General Public License for more details. 15063c1263SAndy Fleming * 16063c1263SAndy Fleming * You should have received a copy of the GNU General Public License 17063c1263SAndy Fleming * along with this program; if not, write to the Free Software 18063c1263SAndy Fleming * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19063c1263SAndy Fleming * MA 02111-1307 USA 20063c1263SAndy Fleming */ 21063c1263SAndy Fleming #ifndef __FSL_PHY_H__ 22063c1263SAndy Fleming #define __FSL_PHY_H__ 23063c1263SAndy Fleming 24063c1263SAndy Fleming #include <net.h> 25063c1263SAndy Fleming #include <miiphy.h> 26063c1263SAndy Fleming #include <asm/fsl_enet.h> 27063c1263SAndy Fleming 28063c1263SAndy Fleming /* PHY register offsets */ 29063c1263SAndy Fleming #define PHY_EXT_PAGE_ACCESS 0x1f 30063c1263SAndy Fleming 31063c1263SAndy Fleming /* MII Management Configuration Register */ 32063c1263SAndy Fleming #define MIIMCFG_RESET_MGMT 0x80000000 33063c1263SAndy Fleming #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 34063c1263SAndy Fleming #define MIIMCFG_INIT_VALUE 0x00000003 35063c1263SAndy Fleming 36063c1263SAndy Fleming /* MII Management Command Register */ 37063c1263SAndy Fleming #define MIIMCOM_READ_CYCLE 0x00000001 38063c1263SAndy Fleming #define MIIMCOM_SCAN_CYCLE 0x00000002 39063c1263SAndy Fleming 40063c1263SAndy Fleming /* MII Management Address Register */ 41063c1263SAndy Fleming #define MIIMADD_PHY_ADDR_SHIFT 8 42063c1263SAndy Fleming 43063c1263SAndy Fleming /* MII Management Indicator Register */ 44063c1263SAndy Fleming #define MIIMIND_BUSY 0x00000001 45063c1263SAndy Fleming #define MIIMIND_NOTVALID 0x00000004 46063c1263SAndy Fleming 47063c1263SAndy Fleming void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, 48063c1263SAndy Fleming int dev_addr, int reg, int value); 49063c1263SAndy Fleming int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, 50063c1263SAndy Fleming int dev_addr, int regnum); 51063c1263SAndy Fleming int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); 52063c1263SAndy Fleming int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, 53063c1263SAndy Fleming u16 value); 54*111fd19eSRoy Zang int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, 55*111fd19eSRoy Zang int regnum, u16 value); 56*111fd19eSRoy Zang int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, 57*111fd19eSRoy Zang int regnum); 58063c1263SAndy Fleming 59063c1263SAndy Fleming struct fsl_pq_mdio_info { 60063c1263SAndy Fleming struct tsec_mii_mng *regs; 61063c1263SAndy Fleming char *name; 62063c1263SAndy Fleming }; 63063c1263SAndy Fleming int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); 64063c1263SAndy Fleming 65063c1263SAndy Fleming #endif /* __FSL_PHY_H__ */ 66