1*063c1263SAndy Fleming /* 2*063c1263SAndy Fleming * Copyright 2009-2010 Freescale Semiconductor, Inc. 3*063c1263SAndy Fleming * Jun-jie Zhang <b18070@freescale.com> 4*063c1263SAndy Fleming * Mingkai Hu <Mingkai.hu@freescale.com> 5*063c1263SAndy Fleming * 6*063c1263SAndy Fleming * This program is free software; you can redistribute it and/or 7*063c1263SAndy Fleming * modify it under the terms of the GNU General Public License as 8*063c1263SAndy Fleming * published by the Free Software Foundation; either version 2 of 9*063c1263SAndy Fleming * the License, or (at your option) any later version. 10*063c1263SAndy Fleming * 11*063c1263SAndy Fleming * This program is distributed in the hope that it will be useful, 12*063c1263SAndy Fleming * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*063c1263SAndy Fleming * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*063c1263SAndy Fleming * GNU General Public License for more details. 15*063c1263SAndy Fleming * 16*063c1263SAndy Fleming * You should have received a copy of the GNU General Public License 17*063c1263SAndy Fleming * along with this program; if not, write to the Free Software 18*063c1263SAndy Fleming * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*063c1263SAndy Fleming * MA 02111-1307 USA 20*063c1263SAndy Fleming */ 21*063c1263SAndy Fleming #ifndef __FSL_PHY_H__ 22*063c1263SAndy Fleming #define __FSL_PHY_H__ 23*063c1263SAndy Fleming 24*063c1263SAndy Fleming #include <net.h> 25*063c1263SAndy Fleming #include <miiphy.h> 26*063c1263SAndy Fleming #include <asm/fsl_enet.h> 27*063c1263SAndy Fleming 28*063c1263SAndy Fleming /* PHY register offsets */ 29*063c1263SAndy Fleming #define PHY_EXT_PAGE_ACCESS 0x1f 30*063c1263SAndy Fleming 31*063c1263SAndy Fleming /* MII Management Configuration Register */ 32*063c1263SAndy Fleming #define MIIMCFG_RESET_MGMT 0x80000000 33*063c1263SAndy Fleming #define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 34*063c1263SAndy Fleming #define MIIMCFG_INIT_VALUE 0x00000003 35*063c1263SAndy Fleming 36*063c1263SAndy Fleming /* MII Management Command Register */ 37*063c1263SAndy Fleming #define MIIMCOM_READ_CYCLE 0x00000001 38*063c1263SAndy Fleming #define MIIMCOM_SCAN_CYCLE 0x00000002 39*063c1263SAndy Fleming 40*063c1263SAndy Fleming /* MII Management Address Register */ 41*063c1263SAndy Fleming #define MIIMADD_PHY_ADDR_SHIFT 8 42*063c1263SAndy Fleming 43*063c1263SAndy Fleming /* MII Management Indicator Register */ 44*063c1263SAndy Fleming #define MIIMIND_BUSY 0x00000001 45*063c1263SAndy Fleming #define MIIMIND_NOTVALID 0x00000004 46*063c1263SAndy Fleming 47*063c1263SAndy Fleming void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, 48*063c1263SAndy Fleming int dev_addr, int reg, int value); 49*063c1263SAndy Fleming int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, 50*063c1263SAndy Fleming int dev_addr, int regnum); 51*063c1263SAndy Fleming int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); 52*063c1263SAndy Fleming int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, 53*063c1263SAndy Fleming u16 value); 54*063c1263SAndy Fleming 55*063c1263SAndy Fleming struct fsl_pq_mdio_info { 56*063c1263SAndy Fleming struct tsec_mii_mng *regs; 57*063c1263SAndy Fleming char *name; 58*063c1263SAndy Fleming }; 59*063c1263SAndy Fleming int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); 60*063c1263SAndy Fleming 61*063c1263SAndy Fleming #endif /* __FSL_PHY_H__ */ 62*063c1263SAndy Fleming 63