1*5614e71bSYork Sun /* 2*5614e71bSYork Sun * Copyright 2008 Freescale Semiconductor, Inc. 3*5614e71bSYork Sun * 4*5614e71bSYork Sun * This program is free software; you can redistribute it and/or 5*5614e71bSYork Sun * modify it under the terms of the GNU General Public License 6*5614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 7*5614e71bSYork Sun */ 8*5614e71bSYork Sun 9*5614e71bSYork Sun #ifndef DDR2_DIMM_PARAMS_H 10*5614e71bSYork Sun #define DDR2_DIMM_PARAMS_H 11*5614e71bSYork Sun 12*5614e71bSYork Sun #define EDC_DATA_PARITY 1 13*5614e71bSYork Sun #define EDC_ECC 2 14*5614e71bSYork Sun #define EDC_AC_PARITY 4 15*5614e71bSYork Sun 16*5614e71bSYork Sun /* Parameters for a DDR2 dimm computed from the SPD */ 17*5614e71bSYork Sun typedef struct dimm_params_s { 18*5614e71bSYork Sun 19*5614e71bSYork Sun /* DIMM organization parameters */ 20*5614e71bSYork Sun char mpart[19]; /* guaranteed null terminated */ 21*5614e71bSYork Sun 22*5614e71bSYork Sun unsigned int n_ranks; 23*5614e71bSYork Sun unsigned long long rank_density; 24*5614e71bSYork Sun unsigned long long capacity; 25*5614e71bSYork Sun unsigned int data_width; 26*5614e71bSYork Sun unsigned int primary_sdram_width; 27*5614e71bSYork Sun unsigned int ec_sdram_width; 28*5614e71bSYork Sun unsigned int registered_dimm; 29*5614e71bSYork Sun unsigned int device_width; /* x4, x8, x16 components */ 30*5614e71bSYork Sun 31*5614e71bSYork Sun /* SDRAM device parameters */ 32*5614e71bSYork Sun unsigned int n_row_addr; 33*5614e71bSYork Sun unsigned int n_col_addr; 34*5614e71bSYork Sun unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ 35*5614e71bSYork Sun unsigned int n_banks_per_sdram_device; 36*5614e71bSYork Sun unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ 37*5614e71bSYork Sun unsigned int row_density; 38*5614e71bSYork Sun 39*5614e71bSYork Sun /* used in computing base address of DIMMs */ 40*5614e71bSYork Sun unsigned long long base_address; 41*5614e71bSYork Sun /* mirrored DIMMs */ 42*5614e71bSYork Sun unsigned int mirrored_dimm; /* only for ddr3 */ 43*5614e71bSYork Sun 44*5614e71bSYork Sun /* DIMM timing parameters */ 45*5614e71bSYork Sun 46*5614e71bSYork Sun unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ 47*5614e71bSYork Sun unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ 48*5614e71bSYork Sun unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ 49*5614e71bSYork Sun unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ 50*5614e71bSYork Sun 51*5614e71bSYork Sun /* 52*5614e71bSYork Sun * SDRAM clock periods 53*5614e71bSYork Sun * The range for these are 1000-10000 so a short should be sufficient 54*5614e71bSYork Sun */ 55*5614e71bSYork Sun unsigned int tckmin_x_ps; 56*5614e71bSYork Sun unsigned int tckmin_x_minus_1_ps; 57*5614e71bSYork Sun unsigned int tckmin_x_minus_2_ps; 58*5614e71bSYork Sun unsigned int tckmax_ps; 59*5614e71bSYork Sun 60*5614e71bSYork Sun /* SPD-defined CAS latencies */ 61*5614e71bSYork Sun unsigned int caslat_x; 62*5614e71bSYork Sun unsigned int caslat_x_minus_1; 63*5614e71bSYork Sun unsigned int caslat_x_minus_2; 64*5614e71bSYork Sun 65*5614e71bSYork Sun unsigned int caslat_lowest_derated; /* Derated CAS latency */ 66*5614e71bSYork Sun 67*5614e71bSYork Sun /* basic timing parameters */ 68*5614e71bSYork Sun unsigned int trcd_ps; 69*5614e71bSYork Sun unsigned int trp_ps; 70*5614e71bSYork Sun unsigned int tras_ps; 71*5614e71bSYork Sun 72*5614e71bSYork Sun unsigned int twr_ps; /* maximum = 63750 ps */ 73*5614e71bSYork Sun unsigned int twtr_ps; /* maximum = 63750 ps */ 74*5614e71bSYork Sun unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns 75*5614e71bSYork Sun = 511750 ps */ 76*5614e71bSYork Sun 77*5614e71bSYork Sun unsigned int trrd_ps; /* maximum = 63750 ps */ 78*5614e71bSYork Sun unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 79*5614e71bSYork Sun 80*5614e71bSYork Sun unsigned int refresh_rate_ps; 81*5614e71bSYork Sun unsigned int extended_op_srt; 82*5614e71bSYork Sun 83*5614e71bSYork Sun /* DDR3 doesn't need these as below */ 84*5614e71bSYork Sun unsigned int tis_ps; /* byte 32, spd->ca_setup */ 85*5614e71bSYork Sun unsigned int tih_ps; /* byte 33, spd->ca_hold */ 86*5614e71bSYork Sun unsigned int tds_ps; /* byte 34, spd->data_setup */ 87*5614e71bSYork Sun unsigned int tdh_ps; /* byte 35, spd->data_hold */ 88*5614e71bSYork Sun unsigned int trtp_ps; /* byte 38, spd->trtp */ 89*5614e71bSYork Sun unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ 90*5614e71bSYork Sun unsigned int tqhs_ps; /* byte 45, spd->tqhs */ 91*5614e71bSYork Sun 92*5614e71bSYork Sun /* DDR3 RDIMM */ 93*5614e71bSYork Sun unsigned char rcw[16]; /* Register Control Word 0-15 */ 94*5614e71bSYork Sun } dimm_params_t; 95*5614e71bSYork Sun 96*5614e71bSYork Sun extern unsigned int ddr_compute_dimm_parameters( 97*5614e71bSYork Sun const generic_spd_eeprom_t *spd, 98*5614e71bSYork Sun dimm_params_t *pdimm, 99*5614e71bSYork Sun unsigned int dimm_number); 100*5614e71bSYork Sun 101*5614e71bSYork Sun #endif 102