19cc2c471SPrabhakar Kushwaha /* 29cc2c471SPrabhakar Kushwaha * Copyright (C) 2015 Freescale Semiconductor 39cc2c471SPrabhakar Kushwaha * 49cc2c471SPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 59cc2c471SPrabhakar Kushwaha */ 69cc2c471SPrabhakar Kushwaha 79cc2c471SPrabhakar Kushwaha #ifndef __LDPAA_WRIOP_H 89cc2c471SPrabhakar Kushwaha #define __LDPAA_WRIOP_H 99cc2c471SPrabhakar Kushwaha 109cc2c471SPrabhakar Kushwaha #include <phy.h> 119cc2c471SPrabhakar Kushwaha 129cc2c471SPrabhakar Kushwaha enum wriop_port { 139cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC1 = 1, 149cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC2, 159cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC3, 169cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC4, 179cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC5, 189cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC6, 199cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC7, 209cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC8, 219cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC9, 229cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC10, 239cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC11, 249cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC12, 259cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC13, 269cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC14, 279cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC15, 289cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC16, 299cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC17, 309cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC18, 319cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC19, 329cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC20, 339cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC21, 349cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC22, 359cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC23, 369cc2c471SPrabhakar Kushwaha WRIOP1_DPMAC24, 379cc2c471SPrabhakar Kushwaha NUM_WRIOP_PORTS, 389cc2c471SPrabhakar Kushwaha }; 399cc2c471SPrabhakar Kushwaha 409cc2c471SPrabhakar Kushwaha struct wriop_dpmac_info { 419cc2c471SPrabhakar Kushwaha u8 enabled; 429cc2c471SPrabhakar Kushwaha u8 id; 439cc2c471SPrabhakar Kushwaha u8 board_mux; 44f9127a04SPrabhakar Kushwaha int phy_addr; 459cc2c471SPrabhakar Kushwaha void *phy_regs; 469cc2c471SPrabhakar Kushwaha phy_interface_t enet_if; 479cc2c471SPrabhakar Kushwaha struct phy_device *phydev; 489cc2c471SPrabhakar Kushwaha struct mii_dev *bus; 499cc2c471SPrabhakar Kushwaha }; 509cc2c471SPrabhakar Kushwaha 519cc2c471SPrabhakar Kushwaha extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; 529cc2c471SPrabhakar Kushwaha 539cc2c471SPrabhakar Kushwaha #define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0" 549cc2c471SPrabhakar Kushwaha #define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1" 559cc2c471SPrabhakar Kushwaha 569cc2c471SPrabhakar Kushwaha void wriop_init_dpmac(int, int, int); 579cc2c471SPrabhakar Kushwaha void wriop_disable_dpmac(int); 589cc2c471SPrabhakar Kushwaha void wriop_enable_dpmac(int); 59f9127a04SPrabhakar Kushwaha u8 wriop_is_enabled_dpmac(int dpmac_id); 609cc2c471SPrabhakar Kushwaha void wriop_set_mdio(int, struct mii_dev *); 619cc2c471SPrabhakar Kushwaha struct mii_dev *wriop_get_mdio(int); 629cc2c471SPrabhakar Kushwaha void wriop_set_phy_address(int, int); 639cc2c471SPrabhakar Kushwaha int wriop_get_phy_address(int); 649cc2c471SPrabhakar Kushwaha void wriop_set_phy_dev(int, struct phy_device *); 659cc2c471SPrabhakar Kushwaha struct phy_device *wriop_get_phy_dev(int); 669cc2c471SPrabhakar Kushwaha phy_interface_t wriop_get_enet_if(int); 679cc2c471SPrabhakar Kushwaha 689cc2c471SPrabhakar Kushwaha void wriop_dpmac_disable(int); 699cc2c471SPrabhakar Kushwaha void wriop_dpmac_enable(int); 709cc2c471SPrabhakar Kushwaha phy_interface_t wriop_dpmac_enet_if(int, int); 71*1b7dba99SPrabhakar Kushwaha void wriop_init_dpmac_qsgmii(int, int); 729cc2c471SPrabhakar Kushwaha #endif /* __LDPAA_WRIOP_H */ 73