1024a26bcSwdenk /* 2024a26bcSwdenk * (C) Copyright 2002 3024a26bcSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4024a26bcSwdenk * 5024a26bcSwdenk * See file CREDITS for list of people who contributed to this 6024a26bcSwdenk * project. 7024a26bcSwdenk * 8024a26bcSwdenk * This program is free software; you can redistribute it and/or 9024a26bcSwdenk * modify it under the terms of the GNU General Public License as 10024a26bcSwdenk * published by the Free Software Foundation; either version 2 of 11024a26bcSwdenk * the License, or (at your option) any later version. 12024a26bcSwdenk * 13024a26bcSwdenk * This program is distributed in the hope that it will be useful, 14024a26bcSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15024a26bcSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16024a26bcSwdenk * GNU General Public License for more details. 17024a26bcSwdenk * 18024a26bcSwdenk * You should have received a copy of the GNU General Public License 19024a26bcSwdenk * along with this program; if not, write to the Free Software 20024a26bcSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21024a26bcSwdenk * MA 02111-1307 USA 22024a26bcSwdenk * 23024a26bcSwdenk */ 24024a26bcSwdenk 25024a26bcSwdenk #include <linux/types.h> /* for ulong typedef */ 26024a26bcSwdenk 27024a26bcSwdenk #ifndef _FPGA_H_ 28024a26bcSwdenk #define _FPGA_H_ 29024a26bcSwdenk 30024a26bcSwdenk #ifndef CONFIG_MAX_FPGA_DEVICES 31024a26bcSwdenk #define CONFIG_MAX_FPGA_DEVICES 5 32024a26bcSwdenk #endif 33024a26bcSwdenk 34024a26bcSwdenk /* these probably belong somewhere else */ 35024a26bcSwdenk #ifndef FALSE 36024a26bcSwdenk #define FALSE (0) 37024a26bcSwdenk #endif 38024a26bcSwdenk #ifndef TRUE 39024a26bcSwdenk #define TRUE (!FALSE) 40024a26bcSwdenk #endif 41024a26bcSwdenk 42024a26bcSwdenk /* CONFIG_FPGA bit assignments */ 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FPGA_MAN(x) (x) 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 ) 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FPGA_IF(x) ((x) << 16 ) 46024a26bcSwdenk 47024a26bcSwdenk /* FPGA Manufacturer bits in CONFIG_FPGA */ 486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 ) 496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 ) 50024a26bcSwdenk 51024a26bcSwdenk 52024a26bcSwdenk /* fpga_xxxx function return value definitions */ 53024a26bcSwdenk #define FPGA_SUCCESS 0 54024a26bcSwdenk #define FPGA_FAIL -1 55024a26bcSwdenk 56024a26bcSwdenk /* device numbers must be non-negative */ 57024a26bcSwdenk #define FPGA_INVALID_DEVICE -1 58024a26bcSwdenk 59024a26bcSwdenk /* root data type defintions */ 60024a26bcSwdenk typedef enum { /* typedef fpga_type */ 61024a26bcSwdenk fpga_min_type, /* range check value */ 62024a26bcSwdenk fpga_xilinx, /* Xilinx Family) */ 63024a26bcSwdenk fpga_altera, /* unimplemented */ 643b8ac464SStefano Babic fpga_lattice, /* Lattice family */ 65024a26bcSwdenk fpga_undefined /* invalid range check value */ 66024a26bcSwdenk } fpga_type; /* end, typedef fpga_type */ 67024a26bcSwdenk 68024a26bcSwdenk typedef struct { /* typedef fpga_desc */ 69024a26bcSwdenk fpga_type devtype; /* switch value to select sub-functions */ 70024a26bcSwdenk void *devdesc; /* real device descriptor */ 71024a26bcSwdenk } fpga_desc; /* end, typedef fpga_desc */ 72024a26bcSwdenk 73024a26bcSwdenk 74024a26bcSwdenk /* root function definitions */ 756385b281SPeter Tyser extern void fpga_init(void); 76024a26bcSwdenk extern int fpga_add(fpga_type devtype, void *desc); 7777ddac94SWolfgang Denk extern int fpga_count(void); 78*e6a857daSWolfgang Denk extern int fpga_load(int devnum, const void *buf, size_t bsize); 79*e6a857daSWolfgang Denk extern int fpga_dump(int devnum, const void *buf, size_t bsize); 80024a26bcSwdenk extern int fpga_info(int devnum); 81024a26bcSwdenk 82024a26bcSwdenk #endif /* _FPGA_H_ */ 83