1c916d7c9SKumar Gala /* 2*111fd19eSRoy Zang * Copyright 2009-2012 Freescale Semiconductor, Inc. 3c916d7c9SKumar Gala * 4c916d7c9SKumar Gala * This program is free software; you can redistribute it and/or 5c916d7c9SKumar Gala * modify it under the terms of the GNU General Public License as 6c916d7c9SKumar Gala * published by the Free Software Foundation; either version 2 of 7c916d7c9SKumar Gala * the License, or (at your option) any later version. 8c916d7c9SKumar Gala * 9c916d7c9SKumar Gala * This program is distributed in the hope that it will be useful, 10c916d7c9SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 11c916d7c9SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12c916d7c9SKumar Gala * GNU General Public License for more details. 13c916d7c9SKumar Gala * 14c916d7c9SKumar Gala * You should have received a copy of the GNU General Public License 15c916d7c9SKumar Gala * along with this program; if not, write to the Free Software 16c916d7c9SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17c916d7c9SKumar Gala * MA 02111-1307 USA 18c916d7c9SKumar Gala */ 19c916d7c9SKumar Gala 20c916d7c9SKumar Gala #ifndef __FM_ETH_H__ 21c916d7c9SKumar Gala #define __FM_ETH_H__ 22c916d7c9SKumar Gala 23c916d7c9SKumar Gala #include <common.h> 24c916d7c9SKumar Gala #include <asm/types.h> 25c916d7c9SKumar Gala #include <asm/fsl_enet.h> 26c916d7c9SKumar Gala 27c916d7c9SKumar Gala enum fm_port { 28c916d7c9SKumar Gala FM1_DTSEC1, 29c916d7c9SKumar Gala FM1_DTSEC2, 30c916d7c9SKumar Gala FM1_DTSEC3, 31c916d7c9SKumar Gala FM1_DTSEC4, 32c916d7c9SKumar Gala FM1_DTSEC5, 339e758758SYork Sun FM1_DTSEC6, 349e758758SYork Sun FM1_DTSEC9, 359e758758SYork Sun FM1_DTSEC10, 36c916d7c9SKumar Gala FM1_10GEC1, 379e758758SYork Sun FM1_10GEC2, 38c916d7c9SKumar Gala FM2_DTSEC1, 39c916d7c9SKumar Gala FM2_DTSEC2, 40c916d7c9SKumar Gala FM2_DTSEC3, 41c916d7c9SKumar Gala FM2_DTSEC4, 4299abf7deSTimur Tabi FM2_DTSEC5, 439e758758SYork Sun FM2_DTSEC6, 449e758758SYork Sun FM2_DTSEC9, 459e758758SYork Sun FM2_DTSEC10, 46c916d7c9SKumar Gala FM2_10GEC1, 479e758758SYork Sun FM2_10GEC2, 48c916d7c9SKumar Gala NUM_FM_PORTS, 49c916d7c9SKumar Gala }; 50c916d7c9SKumar Gala 51c916d7c9SKumar Gala enum fm_eth_type { 52c916d7c9SKumar Gala FM_ETH_1G_E, 53c916d7c9SKumar Gala FM_ETH_10G_E, 54c916d7c9SKumar Gala }; 55c916d7c9SKumar Gala 56*111fd19eSRoy Zang #ifdef CONFIG_SYS_FMAN_V3 57*111fd19eSRoy Zang #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) 58*111fd19eSRoy Zang #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) 59*111fd19eSRoy Zang #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) 60*111fd19eSRoy Zang #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) 61*111fd19eSRoy Zang #else 62c916d7c9SKumar Gala #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) 63c916d7c9SKumar Gala #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) 64*111fd19eSRoy Zang #endif 65c916d7c9SKumar Gala 66c916d7c9SKumar Gala #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" 67c916d7c9SKumar Gala #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" 68c916d7c9SKumar Gala 69c916d7c9SKumar Gala /* Fman ethernet info struct */ 70c916d7c9SKumar Gala #define FM_ETH_INFO_INITIALIZER(idx, pregs) \ 71c916d7c9SKumar Gala .fm = idx, \ 72c916d7c9SKumar Gala .phy_regs = (void *)pregs, \ 73c916d7c9SKumar Gala .enet_if = PHY_INTERFACE_MODE_NONE, \ 74c916d7c9SKumar Gala 75*111fd19eSRoy Zang #ifdef CONFIG_SYS_FMAN_V3 76*111fd19eSRoy Zang #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ 77*111fd19eSRoy Zang { \ 78*111fd19eSRoy Zang FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ 79*111fd19eSRoy Zang .index = idx, \ 80*111fd19eSRoy Zang .num = n - 1, \ 81*111fd19eSRoy Zang .type = FM_ETH_1G_E, \ 82*111fd19eSRoy Zang .port = FM##idx##_DTSEC##n, \ 83*111fd19eSRoy Zang .rx_port_id = RX_PORT_1G_BASE + n - 1, \ 84*111fd19eSRoy Zang .tx_port_id = TX_PORT_1G_BASE + n - 1, \ 85*111fd19eSRoy Zang .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 86*111fd19eSRoy Zang offsetof(struct ccsr_fman, memac[n-1]),\ 87*111fd19eSRoy Zang } 88*111fd19eSRoy Zang 89*111fd19eSRoy Zang #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 90*111fd19eSRoy Zang { \ 91*111fd19eSRoy Zang FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 92*111fd19eSRoy Zang .index = idx, \ 93*111fd19eSRoy Zang .num = n - 1, \ 94*111fd19eSRoy Zang .type = FM_ETH_10G_E, \ 95*111fd19eSRoy Zang .port = FM##idx##_10GEC##n, \ 96*111fd19eSRoy Zang .rx_port_id = RX_PORT_10G_BASE + n - 1, \ 97*111fd19eSRoy Zang .tx_port_id = TX_PORT_10G_BASE + n - 1, \ 98*111fd19eSRoy Zang .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 99*111fd19eSRoy Zang offsetof(struct ccsr_fman, memac[n-1]),\ 100*111fd19eSRoy Zang } 101*111fd19eSRoy Zang #else 102c916d7c9SKumar Gala #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ 103c916d7c9SKumar Gala { \ 104c916d7c9SKumar Gala FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ 105c916d7c9SKumar Gala .index = idx, \ 106c916d7c9SKumar Gala .num = n - 1, \ 107c916d7c9SKumar Gala .type = FM_ETH_1G_E, \ 108c916d7c9SKumar Gala .port = FM##idx##_DTSEC##n, \ 109c916d7c9SKumar Gala .rx_port_id = RX_PORT_1G_BASE + n - 1, \ 110c916d7c9SKumar Gala .tx_port_id = TX_PORT_1G_BASE + n - 1, \ 111c916d7c9SKumar Gala .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 112c916d7c9SKumar Gala offsetof(struct ccsr_fman, mac_1g[n-1]),\ 113c916d7c9SKumar Gala } 114c916d7c9SKumar Gala 115c916d7c9SKumar Gala #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 116c916d7c9SKumar Gala { \ 117c916d7c9SKumar Gala FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 118c916d7c9SKumar Gala .index = idx, \ 119c916d7c9SKumar Gala .num = n - 1, \ 120c916d7c9SKumar Gala .type = FM_ETH_10G_E, \ 121c916d7c9SKumar Gala .port = FM##idx##_10GEC##n, \ 122c916d7c9SKumar Gala .rx_port_id = RX_PORT_10G_BASE + n - 1, \ 123c916d7c9SKumar Gala .tx_port_id = TX_PORT_10G_BASE + n - 1, \ 124c916d7c9SKumar Gala .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 125c916d7c9SKumar Gala offsetof(struct ccsr_fman, mac_10g[n-1]),\ 126c916d7c9SKumar Gala } 127*111fd19eSRoy Zang #endif 128c916d7c9SKumar Gala struct fm_eth_info { 129c916d7c9SKumar Gala u8 enabled; 130c916d7c9SKumar Gala u8 fm; 131c916d7c9SKumar Gala u8 num; 132c916d7c9SKumar Gala u8 phy_addr; 133c916d7c9SKumar Gala int index; 134c916d7c9SKumar Gala u16 rx_port_id; 135c916d7c9SKumar Gala u16 tx_port_id; 136c916d7c9SKumar Gala enum fm_port port; 137c916d7c9SKumar Gala enum fm_eth_type type; 138c916d7c9SKumar Gala void *phy_regs; 139c916d7c9SKumar Gala phy_interface_t enet_if; 140c916d7c9SKumar Gala u32 compat_offset; 141c916d7c9SKumar Gala struct mii_dev *bus; 142c916d7c9SKumar Gala }; 143c916d7c9SKumar Gala 144c916d7c9SKumar Gala struct tgec_mdio_info { 145c916d7c9SKumar Gala struct tgec_mdio_controller *regs; 146c916d7c9SKumar Gala char *name; 147c916d7c9SKumar Gala }; 148c916d7c9SKumar Gala 149*111fd19eSRoy Zang struct memac_mdio_info { 150*111fd19eSRoy Zang struct memac_mdio_controller *regs; 151*111fd19eSRoy Zang char *name; 152*111fd19eSRoy Zang }; 153*111fd19eSRoy Zang 154c916d7c9SKumar Gala int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); 155*111fd19eSRoy Zang int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info); 156*111fd19eSRoy Zang 157c916d7c9SKumar Gala int fm_standard_init(bd_t *bis); 158c916d7c9SKumar Gala void fman_enet_init(void); 159c916d7c9SKumar Gala void fdt_fixup_fman_ethernet(void *fdt); 160c916d7c9SKumar Gala phy_interface_t fm_info_get_enet_if(enum fm_port port); 161c916d7c9SKumar Gala void fm_info_set_phy_address(enum fm_port port, int address); 162ae2291fbSTimur Tabi int fm_info_get_phy_address(enum fm_port port); 163c916d7c9SKumar Gala void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); 16469a85242SKumar Gala void fm_disable_port(enum fm_port port); 165c916d7c9SKumar Gala 166c916d7c9SKumar Gala #endif 167