104c2dd82SMacpaul Lin /* 204c2dd82SMacpaul Lin * Watchdog driver for the FTWDT010 Watch Dog Driver 304c2dd82SMacpaul Lin * 404c2dd82SMacpaul Lin * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) 504c2dd82SMacpaul Lin * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu> 604c2dd82SMacpaul Lin * Based on SoftDog driver by Alan Cox <alan@redhat.com> 704c2dd82SMacpaul Lin * 804c2dd82SMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 904c2dd82SMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 1004c2dd82SMacpaul Lin * 11*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1204c2dd82SMacpaul Lin * 1304c2dd82SMacpaul Lin * 27/11/2004 Initial release, Faraday. 1404c2dd82SMacpaul Lin * 12/01/2011 Port to u-boot, Macpaul Lin. 1504c2dd82SMacpaul Lin */ 1604c2dd82SMacpaul Lin 1704c2dd82SMacpaul Lin #ifndef __FTWDT010_H 1804c2dd82SMacpaul Lin #define __FTWDT010_H 1904c2dd82SMacpaul Lin 2004c2dd82SMacpaul Lin struct ftwdt010_wdt { 2104c2dd82SMacpaul Lin unsigned int wdcounter; /* Counter Reg - 0x00 */ 2204c2dd82SMacpaul Lin unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ 2304c2dd82SMacpaul Lin unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ 2404c2dd82SMacpaul Lin unsigned int wdcr; /* Control Reg - 0x0c */ 2504c2dd82SMacpaul Lin unsigned int wdstatus; /* Status Reg - 0x10 */ 2604c2dd82SMacpaul Lin unsigned int wdclear; /* Timer Clear - 0x14 */ 2704c2dd82SMacpaul Lin unsigned int wdintrlen; /* Interrupt Length - 0x18 */ 2804c2dd82SMacpaul Lin }; 2904c2dd82SMacpaul Lin 3004c2dd82SMacpaul Lin /* 3104c2dd82SMacpaul Lin * WDLOAD - Counter Auto Reload Register 3204c2dd82SMacpaul Lin * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. 3304c2dd82SMacpaul Lin * Which means in a 66MHz system, the period of Watch Dog timer reset is 3404c2dd82SMacpaul Lin * one second. 3504c2dd82SMacpaul Lin */ 3604c2dd82SMacpaul Lin #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) 3704c2dd82SMacpaul Lin 3804c2dd82SMacpaul Lin /* 3904c2dd82SMacpaul Lin * WDRESTART - Watch Dog Timer Counter Restart Register 4004c2dd82SMacpaul Lin * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will 4104c2dd82SMacpaul Lin * automatically reload WDLOAD to WDCOUNTER and restart counting. 4204c2dd82SMacpaul Lin */ 4304c2dd82SMacpaul Lin #define FTWDT010_WDRESTART_MAGIC 0x5AB9 4404c2dd82SMacpaul Lin 4504c2dd82SMacpaul Lin /* WDCR - Watch Dog Timer Control Register */ 4604c2dd82SMacpaul Lin #define FTWDT010_WDCR_ENABLE (1 << 0) 4704c2dd82SMacpaul Lin #define FTWDT010_WDCR_RST (1 << 1) 4804c2dd82SMacpaul Lin #define FTWDT010_WDCR_INTR (1 << 2) 4904c2dd82SMacpaul Lin /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ 5004c2dd82SMacpaul Lin #define FTWDT010_WDCR_EXT (1 << 3) 5104c2dd82SMacpaul Lin /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. 5204c2dd82SMacpaul Lin * The clock source PCLK cannot be gated when system sleeps, even if 5304c2dd82SMacpaul Lin * WDCLOCK bit is turned on. 5404c2dd82SMacpaul Lin * 5504c2dd82SMacpaul Lin * Faraday's Watch Dog timer can be driven by an external clock. The 5604c2dd82SMacpaul Lin * programmer just needs to write one to WdCR[WdClock] bit. 5704c2dd82SMacpaul Lin * 5804c2dd82SMacpaul Lin * Note: There is a limitation between EXTCLK and PCLK: 5904c2dd82SMacpaul Lin * EXTCLK cycle time / PCLK cycle time > 2. 6004c2dd82SMacpaul Lin * If the system does not need an external clock, 6104c2dd82SMacpaul Lin * just keep WdCR[WdClock] bit in its default value. 6204c2dd82SMacpaul Lin */ 6304c2dd82SMacpaul Lin #define FTWDT010_WDCR_CLOCK (1 << 4) 6404c2dd82SMacpaul Lin 6504c2dd82SMacpaul Lin /* 6604c2dd82SMacpaul Lin * WDSTATUS - Watch Dog Timer Status Register 6704c2dd82SMacpaul Lin * This bit is set when the counter reaches Zero 6804c2dd82SMacpaul Lin */ 6904c2dd82SMacpaul Lin #define FTWDT010_WDSTATUS(x) ((x) & 0x1) 7004c2dd82SMacpaul Lin 7104c2dd82SMacpaul Lin /* 7204c2dd82SMacpaul Lin * WDCLEAR - Watch Dog Timer Clear Register 7304c2dd82SMacpaul Lin * Writing one to this register will clear WDSTATUS. 7404c2dd82SMacpaul Lin */ 7504c2dd82SMacpaul Lin #define FTWDT010_WDCLEAR (1 << 0) 7604c2dd82SMacpaul Lin 7704c2dd82SMacpaul Lin /* 7804c2dd82SMacpaul Lin * WDINTRLEN - Watch Dog Timer Interrupt Length 7904c2dd82SMacpaul Lin * This register controls the duration length of wd_rst, wd_intr and wd_ext. 8004c2dd82SMacpaul Lin * The default value is 0xFF. 8104c2dd82SMacpaul Lin */ 8204c2dd82SMacpaul Lin #define FTWDT010_WDINTRLEN(x) ((x) & 0xff) 8304c2dd82SMacpaul Lin 8404c2dd82SMacpaul Lin /* 8504c2dd82SMacpaul Lin * Variable timeout should be set in ms. 8604c2dd82SMacpaul Lin * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. 8704c2dd82SMacpaul Lin * WDLOAD = timeout * TIMEOUT_FACTOR. 8804c2dd82SMacpaul Lin */ 8904c2dd82SMacpaul Lin #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ 9004c2dd82SMacpaul Lin 9104c2dd82SMacpaul Lin void ftwdt010_wdt_reset(void); 9204c2dd82SMacpaul Lin void ftwdt010_wdt_disable(void); 9304c2dd82SMacpaul Lin 9404c2dd82SMacpaul Lin #endif /* __FTWDT010_H */ 95