1*5656b40bSMacpaul Lin /* 2*5656b40bSMacpaul Lin * (C) Copyright 2009 Faraday Technology 3*5656b40bSMacpaul Lin * Po-Yu Chuang <ratbert@faraday-tech.com> 4*5656b40bSMacpaul Lin * 5*5656b40bSMacpaul Lin * This program is free software; you can redistribute it and/or modify 6*5656b40bSMacpaul Lin * it under the terms of the GNU General Public License as published by 7*5656b40bSMacpaul Lin * the Free Software Foundation; either version 2 of the License, or 8*5656b40bSMacpaul Lin * (at your option) any later version. 9*5656b40bSMacpaul Lin * 10*5656b40bSMacpaul Lin * This program is distributed in the hope that it will be useful, 11*5656b40bSMacpaul Lin * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*5656b40bSMacpaul Lin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*5656b40bSMacpaul Lin * GNU General Public License for more details. 14*5656b40bSMacpaul Lin * 15*5656b40bSMacpaul Lin * You should have received a copy of the GNU General Public License 16*5656b40bSMacpaul Lin * along with this program; if not, write to the Free Software 17*5656b40bSMacpaul Lin * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18*5656b40bSMacpaul Lin */ 19*5656b40bSMacpaul Lin 20*5656b40bSMacpaul Lin /* 21*5656b40bSMacpaul Lin * SDRAM Controller 22*5656b40bSMacpaul Lin */ 23*5656b40bSMacpaul Lin #ifndef __FTSDMC020_H 24*5656b40bSMacpaul Lin #define __FTSDMC020_H 25*5656b40bSMacpaul Lin 26*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_TP0 0x00 27*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_TP1 0x04 28*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_CR 0x08 29*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK0_BSR 0x0C 30*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK1_BSR 0x10 31*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK2_BSR 0x14 32*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK3_BSR 0x18 33*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK4_BSR 0x1C 34*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK5_BSR 0x20 35*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK6_BSR 0x24 36*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK7_BSR 0x28 37*5656b40bSMacpaul Lin #define FTSDMC020_OFFSET_ACR 0x34 38*5656b40bSMacpaul Lin 39*5656b40bSMacpaul Lin /* 40*5656b40bSMacpaul Lin * Timing Parametet 0 Register 41*5656b40bSMacpaul Lin */ 42*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TCL(x) ((x) & 0x3) 43*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) 44*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) 45*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) 46*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) 47*5656b40bSMacpaul Lin #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) 48*5656b40bSMacpaul Lin 49*5656b40bSMacpaul Lin /* 50*5656b40bSMacpaul Lin * Timing Parametet 1 Register 51*5656b40bSMacpaul Lin */ 52*5656b40bSMacpaul Lin #define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) 53*5656b40bSMacpaul Lin #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) 54*5656b40bSMacpaul Lin #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) 55*5656b40bSMacpaul Lin 56*5656b40bSMacpaul Lin /* 57*5656b40bSMacpaul Lin * Configuration Register 58*5656b40bSMacpaul Lin */ 59*5656b40bSMacpaul Lin #define FTSDMC020_CR_SREF (1 << 0) 60*5656b40bSMacpaul Lin #define FTSDMC020_CR_PWDN (1 << 1) 61*5656b40bSMacpaul Lin #define FTSDMC020_CR_ISMR (1 << 2) 62*5656b40bSMacpaul Lin #define FTSDMC020_CR_IREF (1 << 3) 63*5656b40bSMacpaul Lin #define FTSDMC020_CR_IPREC (1 << 4) 64*5656b40bSMacpaul Lin #define FTSDMC020_CR_REFTYPE (1 << 5) 65*5656b40bSMacpaul Lin 66*5656b40bSMacpaul Lin /* 67*5656b40bSMacpaul Lin * SDRAM External Bank Base/Size Register 68*5656b40bSMacpaul Lin */ 69*5656b40bSMacpaul Lin #define FTSDMC020_BANK_ENABLE (1 << 28) 70*5656b40bSMacpaul Lin 71*5656b40bSMacpaul Lin #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) 72*5656b40bSMacpaul Lin 73*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X4 (0 << 12) 74*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X8 (1 << 12) 75*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X16 (2 << 12) 76*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X32 (3 << 12) 77*5656b40bSMacpaul Lin 78*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_16M (0 << 8) 79*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_64M (1 << 8) 80*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_128M (2 << 8) 81*5656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_256M (3 << 8) 82*5656b40bSMacpaul Lin 83*5656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_8 (0 << 4) 84*5656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_16 (1 << 4) 85*5656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_32 (2 << 4) 86*5656b40bSMacpaul Lin 87*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_1M 0x0 88*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_2M 0x1 89*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_4M 0x2 90*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_8M 0x3 91*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_16M 0x4 92*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_32M 0x5 93*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_64M 0x6 94*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_128M 0x7 95*5656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_256M 0x8 96*5656b40bSMacpaul Lin 97*5656b40bSMacpaul Lin /* 98*5656b40bSMacpaul Lin * Arbiter Control Register 99*5656b40bSMacpaul Lin */ 100*5656b40bSMacpaul Lin #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) 101*5656b40bSMacpaul Lin #define FTSDMC020_ACR_TOE (1 << 8) 102*5656b40bSMacpaul Lin 103*5656b40bSMacpaul Lin #endif /* __FTSDMC020_H */ 104