1 /* 2 * (C) Copyright 2009 Faraday Technology 3 * Po-Yu Chuang <ratbert@faraday-tech.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 /* 21 * Power Management Unit 22 */ 23 #ifndef __FTPMU010_H 24 #define __FTPMU010_H 25 26 struct ftpmu010 { 27 unsigned int IDNMBR0; /* 0x00 */ 28 unsigned int reserved0; /* 0x04 */ 29 unsigned int OSCC; /* 0x08 */ 30 unsigned int PMODE; /* 0x0C */ 31 unsigned int PMCR; /* 0x10 */ 32 unsigned int PED; /* 0x14 */ 33 unsigned int PEDSR; /* 0x18 */ 34 unsigned int reserved1; /* 0x1C */ 35 unsigned int PMSR; /* 0x20 */ 36 unsigned int PGSR; /* 0x24 */ 37 unsigned int MFPSR; /* 0x28 */ 38 unsigned int MISC; /* 0x2C */ 39 unsigned int PDLLCR0; /* 0x30 */ 40 unsigned int PDLLCR1; /* 0x34 */ 41 unsigned int AHBMCLKOFF; /* 0x38 */ 42 unsigned int APBMCLKOFF; /* 0x3C */ 43 unsigned int DCSRCR0; /* 0x40 */ 44 unsigned int DCSRCR1; /* 0x44 */ 45 unsigned int DCSRCR2; /* 0x48 */ 46 unsigned int SDRAMHTC; /* 0x4C */ 47 unsigned int PSPR0; /* 0x50 */ 48 unsigned int PSPR1; /* 0x54 */ 49 unsigned int PSPR2; /* 0x58 */ 50 unsigned int PSPR3; /* 0x5C */ 51 unsigned int PSPR4; /* 0x60 */ 52 unsigned int PSPR5; /* 0x64 */ 53 unsigned int PSPR6; /* 0x68 */ 54 unsigned int PSPR7; /* 0x6C */ 55 unsigned int PSPR8; /* 0x70 */ 56 unsigned int PSPR9; /* 0x74 */ 57 unsigned int PSPR10; /* 0x78 */ 58 unsigned int PSPR11; /* 0x7C */ 59 unsigned int PSPR12; /* 0x80 */ 60 unsigned int PSPR13; /* 0x84 */ 61 unsigned int PSPR14; /* 0x88 */ 62 unsigned int PSPR15; /* 0x8C */ 63 unsigned int AHBDMA_RACCS; /* 0x90 */ 64 unsigned int reserved2; /* 0x94 */ 65 unsigned int reserved3; /* 0x98 */ 66 unsigned int JSS; /* 0x9C */ 67 unsigned int CFC_RACC; /* 0xA0 */ 68 unsigned int SSP1_RACC; /* 0xA4 */ 69 unsigned int UART1TX_RACC; /* 0xA8 */ 70 unsigned int UART1RX_RACC; /* 0xAC */ 71 unsigned int UART2TX_RACC; /* 0xB0 */ 72 unsigned int UART2RX_RACC; /* 0xB4 */ 73 unsigned int SDC_RACC; /* 0xB8 */ 74 unsigned int I2SAC97_RACC; /* 0xBC */ 75 unsigned int IRDATX_RACC; /* 0xC0 */ 76 unsigned int reserved4; /* 0xC4 */ 77 unsigned int USBD_RACC; /* 0xC8 */ 78 unsigned int IRDARX_RACC; /* 0xCC */ 79 unsigned int IRDA_RACC; /* 0xD0 */ 80 unsigned int ED0_RACC; /* 0xD4 */ 81 unsigned int ED1_RACC; /* 0xD8 */ 82 }; 83 84 /* 85 * ID Number 0 Register 86 */ 87 #define FTPMU010_ID_A320A 0x03200000 88 #define FTPMU010_ID_A320C 0x03200010 89 #define FTPMU010_ID_A320D 0x03200030 90 91 /* 92 * OSC Control Register 93 */ 94 #define FTPMU010_OSCC_OSCH_TRI (1 << 11) 95 #define FTPMU010_OSCC_OSCH_STABLE (1 << 9) 96 #define FTPMU010_OSCC_OSCH_OFF (1 << 8) 97 98 #define FTPMU010_OSCC_OSCL_TRI (1 << 3) 99 #define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) 100 #define FTPMU010_OSCC_OSCL_STABLE (1 << 1) 101 #define FTPMU010_OSCC_OSCL_OFF (1 << 0) 102 103 /* 104 * Power Mode Register 105 */ 106 #define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) 107 #define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) 108 #define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) 109 #define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) 110 #define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) 111 #define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) 112 #define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) 113 #define FTPMU010_PMODE_FCS (1 << 2) 114 #define FTPMU010_PMODE_TURBO (1 << 1) 115 #define FTPMU010_PMODE_SLEEP (1 << 0) 116 117 /* 118 * Power Manager Status Register 119 */ 120 #define FTPMU010_PMSR_SMR (1 << 10) 121 122 #define FTPMU010_PMSR_RDH (1 << 2) 123 #define FTPMU010_PMSR_PH (1 << 1) 124 #define FTPMU010_PMSR_CKEHLOW (1 << 0) 125 126 /* 127 * Multi-Function Port Setting Register 128 */ 129 #define FTPMU010_MFPSR_DEBUGSEL (1 << 17) 130 #define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) 131 #define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) 132 #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) 133 #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) 134 #define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) 135 #define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) 136 #define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) 137 #define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) 138 #define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) 139 #define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) 140 #define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) 141 #define FTPMU010_MFPSR_AC97PINSEL (1 << 3) 142 #define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) 143 #define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) 144 145 /* 146 * PLL/DLL Control Register 0 147 * Note: 148 * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: 149 * Datasheet indicated it starts at bit #21 which was wrong. 150 * 2. FTPMU010_PDLLCR0_DLLFRAG: 151 * Datasheet indicated it has 2 bit which was wrong. 152 */ 153 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) 154 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) 155 #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) 156 #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) 157 #define FTPMU010_PDLLCR0_DLLDIS (1 << 16) 158 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) 159 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) 160 #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) 161 #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) 162 #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) 163 164 /* 165 * SDRAM Signal Hold Time Control Register 166 */ 167 #define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) 168 #define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) 169 #define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) 170 #define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) 171 #define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) 172 #define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) 173 #define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) 174 #define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) 175 #define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) 176 #define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) 177 178 void ftpmu010_32768osc_enable(void); 179 void ftpmu010_dlldis_disable(void); 180 void ftpmu010_sdram_clk_disable(unsigned int cr0); 181 182 #endif /* __FTPMU010_H */ 183