1*baaa7dd7SNikita Kiryanov /* 2*baaa7dd7SNikita Kiryanov * exynos_lcd.h - Exynos LCD Controller structures 3*baaa7dd7SNikita Kiryanov * 4*baaa7dd7SNikita Kiryanov * (C) Copyright 2001 5*baaa7dd7SNikita Kiryanov * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*baaa7dd7SNikita Kiryanov * 7*baaa7dd7SNikita Kiryanov * SPDX-License-Identifier: GPL-2.0+ 8*baaa7dd7SNikita Kiryanov */ 9*baaa7dd7SNikita Kiryanov 10*baaa7dd7SNikita Kiryanov #ifndef _EXYNOS_LCD_H_ 11*baaa7dd7SNikita Kiryanov #define _EXYNOS_LCD_H_ 12*baaa7dd7SNikita Kiryanov 13*baaa7dd7SNikita Kiryanov enum { 14*baaa7dd7SNikita Kiryanov FIMD_RGB_INTERFACE = 1, 15*baaa7dd7SNikita Kiryanov FIMD_CPU_INTERFACE = 2, 16*baaa7dd7SNikita Kiryanov }; 17*baaa7dd7SNikita Kiryanov 18*baaa7dd7SNikita Kiryanov enum exynos_fb_rgb_mode_t { 19*baaa7dd7SNikita Kiryanov MODE_RGB_P = 0, 20*baaa7dd7SNikita Kiryanov MODE_BGR_P = 1, 21*baaa7dd7SNikita Kiryanov MODE_RGB_S = 2, 22*baaa7dd7SNikita Kiryanov MODE_BGR_S = 3, 23*baaa7dd7SNikita Kiryanov }; 24*baaa7dd7SNikita Kiryanov 25*baaa7dd7SNikita Kiryanov typedef struct vidinfo { 26*baaa7dd7SNikita Kiryanov ushort vl_col; /* Number of columns (i.e. 640) */ 27*baaa7dd7SNikita Kiryanov ushort vl_row; /* Number of rows (i.e. 480) */ 28*baaa7dd7SNikita Kiryanov ushort vl_width; /* Width of display area in millimeters */ 29*baaa7dd7SNikita Kiryanov ushort vl_height; /* Height of display area in millimeters */ 30*baaa7dd7SNikita Kiryanov 31*baaa7dd7SNikita Kiryanov /* LCD configuration register */ 32*baaa7dd7SNikita Kiryanov u_char vl_freq; /* Frequency */ 33*baaa7dd7SNikita Kiryanov u_char vl_clkp; /* Clock polarity */ 34*baaa7dd7SNikita Kiryanov u_char vl_oep; /* Output Enable polarity */ 35*baaa7dd7SNikita Kiryanov u_char vl_hsp; /* Horizontal Sync polarity */ 36*baaa7dd7SNikita Kiryanov u_char vl_vsp; /* Vertical Sync polarity */ 37*baaa7dd7SNikita Kiryanov u_char vl_dp; /* Data polarity */ 38*baaa7dd7SNikita Kiryanov u_char vl_bpix; /* Bits per pixel */ 39*baaa7dd7SNikita Kiryanov 40*baaa7dd7SNikita Kiryanov /* Horizontal control register. Timing from data sheet */ 41*baaa7dd7SNikita Kiryanov u_char vl_hspw; /* Horz sync pulse width */ 42*baaa7dd7SNikita Kiryanov u_char vl_hfpd; /* Wait before of line */ 43*baaa7dd7SNikita Kiryanov u_char vl_hbpd; /* Wait end of line */ 44*baaa7dd7SNikita Kiryanov 45*baaa7dd7SNikita Kiryanov /* Vertical control register. */ 46*baaa7dd7SNikita Kiryanov u_char vl_vspw; /* Vertical sync pulse width */ 47*baaa7dd7SNikita Kiryanov u_char vl_vfpd; /* Wait before of frame */ 48*baaa7dd7SNikita Kiryanov u_char vl_vbpd; /* Wait end of frame */ 49*baaa7dd7SNikita Kiryanov u_char vl_cmd_allow_len; /* Wait end of frame */ 50*baaa7dd7SNikita Kiryanov 51*baaa7dd7SNikita Kiryanov unsigned int win_id; 52*baaa7dd7SNikita Kiryanov unsigned int init_delay; 53*baaa7dd7SNikita Kiryanov unsigned int power_on_delay; 54*baaa7dd7SNikita Kiryanov unsigned int reset_delay; 55*baaa7dd7SNikita Kiryanov unsigned int interface_mode; 56*baaa7dd7SNikita Kiryanov unsigned int mipi_enabled; 57*baaa7dd7SNikita Kiryanov unsigned int dp_enabled; 58*baaa7dd7SNikita Kiryanov unsigned int cs_setup; 59*baaa7dd7SNikita Kiryanov unsigned int wr_setup; 60*baaa7dd7SNikita Kiryanov unsigned int wr_act; 61*baaa7dd7SNikita Kiryanov unsigned int wr_hold; 62*baaa7dd7SNikita Kiryanov unsigned int logo_on; 63*baaa7dd7SNikita Kiryanov unsigned int logo_width; 64*baaa7dd7SNikita Kiryanov unsigned int logo_height; 65*baaa7dd7SNikita Kiryanov int logo_x_offset; 66*baaa7dd7SNikita Kiryanov int logo_y_offset; 67*baaa7dd7SNikita Kiryanov unsigned long logo_addr; 68*baaa7dd7SNikita Kiryanov unsigned int rgb_mode; 69*baaa7dd7SNikita Kiryanov unsigned int resolution; 70*baaa7dd7SNikita Kiryanov 71*baaa7dd7SNikita Kiryanov /* parent clock name(MPLL, EPLL or VPLL) */ 72*baaa7dd7SNikita Kiryanov unsigned int pclk_name; 73*baaa7dd7SNikita Kiryanov /* ratio value for source clock from parent clock. */ 74*baaa7dd7SNikita Kiryanov unsigned int sclk_div; 75*baaa7dd7SNikita Kiryanov 76*baaa7dd7SNikita Kiryanov unsigned int dual_lcd_enabled; 77*baaa7dd7SNikita Kiryanov } vidinfo_t; 78*baaa7dd7SNikita Kiryanov 79*baaa7dd7SNikita Kiryanov void init_panel_info(vidinfo_t *vid); 80*baaa7dd7SNikita Kiryanov 81*baaa7dd7SNikita Kiryanov #endif 82