1baaa7dd7SNikita Kiryanov /* 2baaa7dd7SNikita Kiryanov * exynos_lcd.h - Exynos LCD Controller structures 3baaa7dd7SNikita Kiryanov * 4baaa7dd7SNikita Kiryanov * (C) Copyright 2001 5baaa7dd7SNikita Kiryanov * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6baaa7dd7SNikita Kiryanov * 7baaa7dd7SNikita Kiryanov * SPDX-License-Identifier: GPL-2.0+ 8baaa7dd7SNikita Kiryanov */ 9baaa7dd7SNikita Kiryanov 10baaa7dd7SNikita Kiryanov #ifndef _EXYNOS_LCD_H_ 11baaa7dd7SNikita Kiryanov #define _EXYNOS_LCD_H_ 12baaa7dd7SNikita Kiryanov 13baaa7dd7SNikita Kiryanov enum { 14baaa7dd7SNikita Kiryanov FIMD_RGB_INTERFACE = 1, 15baaa7dd7SNikita Kiryanov FIMD_CPU_INTERFACE = 2, 16baaa7dd7SNikita Kiryanov }; 17baaa7dd7SNikita Kiryanov 18baaa7dd7SNikita Kiryanov enum exynos_fb_rgb_mode_t { 19baaa7dd7SNikita Kiryanov MODE_RGB_P = 0, 20baaa7dd7SNikita Kiryanov MODE_BGR_P = 1, 21baaa7dd7SNikita Kiryanov MODE_RGB_S = 2, 22baaa7dd7SNikita Kiryanov MODE_BGR_S = 3, 23baaa7dd7SNikita Kiryanov }; 24baaa7dd7SNikita Kiryanov 25baaa7dd7SNikita Kiryanov typedef struct vidinfo { 26baaa7dd7SNikita Kiryanov ushort vl_col; /* Number of columns (i.e. 640) */ 27baaa7dd7SNikita Kiryanov ushort vl_row; /* Number of rows (i.e. 480) */ 28604c7d4aSHannes Petermaier ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 29baaa7dd7SNikita Kiryanov ushort vl_width; /* Width of display area in millimeters */ 30baaa7dd7SNikita Kiryanov ushort vl_height; /* Height of display area in millimeters */ 31baaa7dd7SNikita Kiryanov 32baaa7dd7SNikita Kiryanov /* LCD configuration register */ 33baaa7dd7SNikita Kiryanov u_char vl_freq; /* Frequency */ 34baaa7dd7SNikita Kiryanov u_char vl_clkp; /* Clock polarity */ 35baaa7dd7SNikita Kiryanov u_char vl_oep; /* Output Enable polarity */ 36baaa7dd7SNikita Kiryanov u_char vl_hsp; /* Horizontal Sync polarity */ 37baaa7dd7SNikita Kiryanov u_char vl_vsp; /* Vertical Sync polarity */ 38baaa7dd7SNikita Kiryanov u_char vl_dp; /* Data polarity */ 39baaa7dd7SNikita Kiryanov u_char vl_bpix; /* Bits per pixel */ 40baaa7dd7SNikita Kiryanov 41baaa7dd7SNikita Kiryanov /* Horizontal control register. Timing from data sheet */ 42baaa7dd7SNikita Kiryanov u_char vl_hspw; /* Horz sync pulse width */ 43baaa7dd7SNikita Kiryanov u_char vl_hfpd; /* Wait before of line */ 44baaa7dd7SNikita Kiryanov u_char vl_hbpd; /* Wait end of line */ 45baaa7dd7SNikita Kiryanov 46baaa7dd7SNikita Kiryanov /* Vertical control register. */ 47baaa7dd7SNikita Kiryanov u_char vl_vspw; /* Vertical sync pulse width */ 48baaa7dd7SNikita Kiryanov u_char vl_vfpd; /* Wait before of frame */ 49baaa7dd7SNikita Kiryanov u_char vl_vbpd; /* Wait end of frame */ 50baaa7dd7SNikita Kiryanov u_char vl_cmd_allow_len; /* Wait end of frame */ 51baaa7dd7SNikita Kiryanov 52baaa7dd7SNikita Kiryanov unsigned int win_id; 53baaa7dd7SNikita Kiryanov unsigned int init_delay; 54baaa7dd7SNikita Kiryanov unsigned int power_on_delay; 55baaa7dd7SNikita Kiryanov unsigned int reset_delay; 56baaa7dd7SNikita Kiryanov unsigned int interface_mode; 57baaa7dd7SNikita Kiryanov unsigned int mipi_enabled; 58baaa7dd7SNikita Kiryanov unsigned int dp_enabled; 59baaa7dd7SNikita Kiryanov unsigned int cs_setup; 60baaa7dd7SNikita Kiryanov unsigned int wr_setup; 61baaa7dd7SNikita Kiryanov unsigned int wr_act; 62baaa7dd7SNikita Kiryanov unsigned int wr_hold; 63baaa7dd7SNikita Kiryanov unsigned int logo_on; 64baaa7dd7SNikita Kiryanov unsigned int logo_width; 65baaa7dd7SNikita Kiryanov unsigned int logo_height; 66baaa7dd7SNikita Kiryanov int logo_x_offset; 67baaa7dd7SNikita Kiryanov int logo_y_offset; 68baaa7dd7SNikita Kiryanov unsigned long logo_addr; 69baaa7dd7SNikita Kiryanov unsigned int rgb_mode; 70baaa7dd7SNikita Kiryanov unsigned int resolution; 71baaa7dd7SNikita Kiryanov 72baaa7dd7SNikita Kiryanov /* parent clock name(MPLL, EPLL or VPLL) */ 73baaa7dd7SNikita Kiryanov unsigned int pclk_name; 74baaa7dd7SNikita Kiryanov /* ratio value for source clock from parent clock. */ 75baaa7dd7SNikita Kiryanov unsigned int sclk_div; 76baaa7dd7SNikita Kiryanov 77baaa7dd7SNikita Kiryanov unsigned int dual_lcd_enabled; 78*8b449a66SSimon Glass struct exynos_fb *reg; 79652d15c0SSimon Glass struct exynos_platform_mipi_dsim *dsim_platform_data_dt; 80baaa7dd7SNikita Kiryanov } vidinfo_t; 81baaa7dd7SNikita Kiryanov 82baaa7dd7SNikita Kiryanov #endif 83