1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #ifndef __EDID_H_ 15 #define __EDID_H_ 16 17 #include <div64.h> 18 #include <linux/types.h> 19 #include <drm_modes.h> 20 #include <i2c.h> 21 22 /* Size of the EDID data */ 23 #define EDID_SIZE 128 24 #define EDID_EXT_SIZE 256 25 #define MODE_LEN 240 26 27 #define CEA_EXT 0x02 28 #define VTB_EXT 0x10 29 #define DI_EXT 0x40 30 #define LS_EXT 0x50 31 #define MI_EXT 0x60 32 #define DISPLAYID_EXT 0x70 33 34 #define EDID_TIMING_ASPECT_SHIFT 6 35 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 36 37 /* need to add 60 */ 38 #define EDID_TIMING_VFREQ_SHIFT 0 39 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 40 41 /* OUI of HDMI vendor specific data block */ 42 #define HDMI_IEEE_OUI 0x000c03 43 44 /* drm mode 4k and 3d */ 45 #define DRM_MODE_FLAG_420_MASK (0x03 << 23) 46 #define DRM_MODE_FLAG_420 BIT(23) 47 #define DRM_MODE_FLAG_420_ONLY BIT(24) 48 49 #define DRM_MODE_FLAG_3D_MASK (0x1f << 14) 50 #define DRM_MODE_FLAG_3D_NONE (0 << 14) 51 #define DRM_MODE_FLAG_3D_FRAME_PACKING BIT(14) 52 #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14) 53 #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14) 54 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14) 55 #define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14) 56 #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14) 57 #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14) 58 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14) 59 60 #define BITS_PER_BYTE 8 61 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) 62 #define GET_BIT(_x, _pos) \ 63 (((_x) >> (_pos)) & 1) 64 #define GET_BITS(_x, _pos_msb, _pos_lsb) \ 65 (((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1)) 66 #define DRM_MODE(t, c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 67 .clock = (c), .type = (t),\ 68 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 69 .htotal = (ht), .vdisplay = (vd), \ 70 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 71 .vscan = (vs), .flags = (f) 72 73 #define DDC_SEGMENT_ADDR 0x30 74 #define DDC_ADDR 0x50 75 #define HDMI_EDID_BLOCK_SIZE 128 76 #define SCDC_I2C_SLAVE_ADDRESS 0x54 77 78 /* Aspect ratios used in EDID info. */ 79 enum edid_aspect { 80 ASPECT_625 = 0, 81 ASPECT_75, 82 ASPECT_8, 83 ASPECT_5625, 84 }; 85 86 struct est_timings { 87 u8 t1; 88 u8 t2; 89 u8 mfg_rsvd; 90 } __packed; 91 92 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 93 #define EDID_TIMING_ASPECT_SHIFT 6 94 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 95 96 /* need to add 60 */ 97 #define EDID_TIMING_VFREQ_SHIFT 0 98 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 99 100 struct std_timing { 101 u8 hsize; /* need to multiply by 8 then add 248 */ 102 u8 vfreq_aspect; 103 } __packed; 104 105 struct detailed_pixel_timing { 106 u8 hactive_lo; 107 u8 hblank_lo; 108 u8 hactive_hblank_hi; 109 u8 vactive_lo; 110 u8 vblank_lo; 111 u8 vactive_vblank_hi; 112 u8 hsync_offset_lo; 113 u8 hsync_pulse_width_lo; 114 u8 vsync_offset_pulse_width_lo; 115 u8 hsync_vsync_offset_pulse_width_hi; 116 u8 width_mm_lo; 117 u8 height_mm_lo; 118 u8 width_height_mm_hi; 119 u8 hborder; 120 u8 vborder; 121 u8 misc; 122 } __packed; 123 124 /* If it's not pixel timing, it'll be one of the below */ 125 struct detailed_data_string { 126 u8 str[13]; 127 } __packed; 128 129 struct detailed_data_monitor_range { 130 u8 min_vfreq; 131 u8 max_vfreq; 132 u8 min_hfreq_khz; 133 u8 max_hfreq_khz; 134 u8 pixel_clock_mhz; /* need to multiply by 10 */ 135 u8 flags; 136 union { 137 struct { 138 u8 reserved; 139 u8 hfreq_start_khz; /* need to multiply by 2 */ 140 u8 c; /* need to divide by 2 */ 141 __le16 m; 142 u8 k; 143 u8 j; /* need to divide by 2 */ 144 } __packed gtf2; 145 struct { 146 u8 version; 147 u8 data1; /* high 6 bits: extra clock resolution */ 148 u8 data2; /* plus low 2 of above: max hactive */ 149 u8 supported_aspects; 150 u8 flags; /* preferred aspect and blanking support */ 151 u8 supported_scalings; 152 u8 preferred_refresh; 153 } __packed cvt; 154 } formula; 155 } __packed; 156 157 struct detailed_data_wpindex { 158 u8 white_yx_lo; /* Lower 2 bits each */ 159 u8 white_x_hi; 160 u8 white_y_hi; 161 u8 gamma; /* need to divide by 100 then add 1 */ 162 } __packed; 163 164 struct detailed_data_color_point { 165 u8 windex1; 166 u8 wpindex1[3]; 167 u8 windex2; 168 u8 wpindex2[3]; 169 } __packed; 170 171 struct cvt_timing { 172 u8 code[3]; 173 } __packed; 174 175 struct detailed_non_pixel { 176 u8 pad1; 177 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 178 * fb=color point data, fa=standard timing data, 179 * f9=undefined, f8=mfg. reserved 180 */ 181 u8 pad2; 182 union { 183 struct detailed_data_string str; 184 struct detailed_data_monitor_range range; 185 struct detailed_data_wpindex color; 186 struct std_timing timings[6]; 187 struct cvt_timing cvt[4]; 188 } data; 189 } __packed; 190 191 #define EDID_DETAIL_EST_TIMINGS 0xf7 192 #define EDID_DETAIL_CVT_3BYTE 0xf8 193 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 194 #define EDID_DETAIL_STD_MODES 0xfa 195 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 196 #define EDID_DETAIL_MONITOR_NAME 0xfc 197 #define EDID_DETAIL_MONITOR_RANGE 0xfd 198 #define EDID_DETAIL_MONITOR_STRING 0xfe 199 #define EDID_DETAIL_MONITOR_SERIAL 0xff 200 201 struct detailed_timing { 202 __le16 pixel_clock; /* need to multiply by 10 KHz */ 203 union { 204 struct detailed_pixel_timing pixel_data; 205 struct detailed_non_pixel other_data; 206 } data; 207 } __packed; 208 209 /* Detailed timing information used in EDID v1.x */ 210 struct edid_detailed_timing { 211 unsigned char pixel_clock[2]; 212 #define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \ 213 (((((uint32_t)(_x).pixel_clock[1]) << 8) + \ 214 (_x).pixel_clock[0]) * 10000) 215 unsigned char horizontal_active; 216 unsigned char horizontal_blanking; 217 unsigned char horizontal_active_blanking_hi; 218 #define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \ 219 ((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \ 220 (_x).horizontal_active) 221 #define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \ 222 ((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \ 223 (_x).horizontal_blanking) 224 unsigned char vertical_active; 225 unsigned char vertical_blanking; 226 unsigned char vertical_active_blanking_hi; 227 #define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \ 228 ((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \ 229 (_x).vertical_active) 230 #define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \ 231 ((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \ 232 (_x).vertical_blanking) 233 unsigned char hsync_offset; 234 unsigned char hsync_pulse_width; 235 unsigned char vsync_offset_pulse_width; 236 unsigned char hsync_vsync_offset_pulse_width_hi; 237 #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ 238 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \ 239 (_x).hsync_offset) 240 #define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \ 241 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \ 242 (_x).hsync_pulse_width) 243 #define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \ 244 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \ 245 GET_BITS((_x).vsync_offset_pulse_width, 7, 4)) 246 #define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \ 247 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \ 248 GET_BITS((_x).vsync_offset_pulse_width, 3, 0)) 249 unsigned char himage_size; 250 unsigned char vimage_size; 251 unsigned char himage_vimage_size_hi; 252 #define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \ 253 ((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size) 254 #define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \ 255 ((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size) 256 unsigned char hborder; 257 unsigned char vborder; 258 unsigned char flags; 259 #define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \ 260 GET_BIT((_x).flags, 7) 261 #define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \ 262 GET_BITS((_x).flags, 6, 5) 263 #define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \ 264 GET_BITS((_x).flags, 4, 3) 265 #define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \ 266 GET_BITS((_x).flags, 2, 1) 267 #define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \ 268 GET_BIT((_x).flags, 2) 269 #define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \ 270 GET_BIT((_x).flags, 1) 271 #define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \ 272 GET_BIT((_x).flags, 0) 273 } __attribute__ ((__packed__)); 274 275 enum edid_monitor_descriptor_types { 276 EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff, 277 EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe, 278 EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd, 279 EDID_MONITOR_DESCRIPTOR_NAME = 0xfc, 280 }; 281 282 struct edid_monitor_descriptor { 283 uint16_t zero_flag_1; 284 unsigned char zero_flag_2; 285 unsigned char type; 286 unsigned char zero_flag_3; 287 union { 288 char string[13]; 289 struct { 290 unsigned char vertical_min; 291 unsigned char vertical_max; 292 unsigned char horizontal_min; 293 unsigned char horizontal_max; 294 unsigned char pixel_clock_max; 295 unsigned char gtf_data[8]; 296 } range_data; 297 } data; 298 } __attribute__ ((__packed__)); 299 300 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 301 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 302 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 303 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 304 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 305 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 306 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 307 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 308 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 309 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 310 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 311 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 312 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 313 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 314 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 315 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 316 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 317 #define DRM_EDID_DIGITAL_TYPE_DVI (1) 318 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 319 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 320 #define DRM_EDID_DIGITAL_TYPE_MDDI (4) 321 #define DRM_EDID_DIGITAL_TYPE_DP (5) 322 323 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 324 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 325 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 326 /* If analog */ 327 /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 328 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) 329 /* If digital */ 330 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 331 #define DRM_EDID_FEATURE_RGB (0 << 3) 332 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 333 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 334 /* both 4:4:4 and 4:2:2 */ 335 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) 336 337 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 338 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 339 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 340 341 #define DRM_EDID_HDMI_DC_48 (1 << 6) 342 #define DRM_EDID_HDMI_DC_36 (1 << 5) 343 #define DRM_EDID_HDMI_DC_30 (1 << 4) 344 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 345 346 /* YCBCR 420 deep color modes */ 347 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 348 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 349 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 350 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 351 DRM_EDID_YCBCR420_DC_36 | \ 352 DRM_EDID_YCBCR420_DC_30) 353 354 /* HDMI 2.1 additional fields */ 355 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 356 #define DRM_EDID_FAPA_START_LOCATION BIT(0) 357 #define DRM_EDID_ALLM BIT(1) 358 #define DRM_EDID_FVA BIT(2) 359 360 /* Deep Color specific */ 361 #define DRM_EDID_DC_30BIT_420 BIT(0) 362 #define DRM_EDID_DC_36BIT_420 BIT(1) 363 #define DRM_EDID_DC_48BIT_420 BIT(2) 364 365 /* VRR specific */ 366 #define DRM_EDID_CNMVRR BIT(3) 367 #define DRM_EDID_CINEMA_VRR BIT(4) 368 #define DRM_EDID_MDELTA BIT(5) 369 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 370 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff 371 #define DRM_EDID_VRR_MIN_MASK 0x3f 372 373 /* DSC specific */ 374 #define DRM_EDID_DSC_10BPC BIT(0) 375 #define DRM_EDID_DSC_12BPC BIT(1) 376 #define DRM_EDID_DSC_16BPC BIT(2) 377 #define DRM_EDID_DSC_ALL_BPP BIT(3) 378 #define DRM_EDID_DSC_NATIVE_420 BIT(6) 379 #define DRM_EDID_DSC_1P2 BIT(7) 380 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 381 #define DRM_EDID_DSC_MAX_SLICES 0xf 382 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f 383 384 struct edid1_info { 385 unsigned char header[8]; 386 unsigned char manufacturer_name[2]; 387 #define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \ 388 GET_BIT(((_x).manufacturer_name[0]), 7) 389 #define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \ 390 GET_BITS(((_x).manufacturer_name[0]), 6, 2) 391 #define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \ 392 ((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \ 393 GET_BITS(((_x).manufacturer_name[1]), 7, 5)) 394 #define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \ 395 GET_BITS(((_x).manufacturer_name[1]), 4, 0) 396 unsigned char product_code[2]; 397 #define EDID1_INFO_PRODUCT_CODE(_x) \ 398 (((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0]) 399 unsigned char serial_number[4]; 400 #define EDID1_INFO_SERIAL_NUMBER(_x) \ 401 (((uint32_t)(_x).serial_number[3] << 24) + \ 402 ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \ 403 (_x).serial_number[0]) 404 unsigned char week; 405 unsigned char year; 406 unsigned char version; 407 unsigned char revision; 408 unsigned char video_input_definition; 409 #define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \ 410 GET_BIT(((_x).video_input_definition), 7) 411 #define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \ 412 GET_BITS(((_x).video_input_definition), 6, 5) 413 #define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \ 414 GET_BIT(((_x).video_input_definition), 4) 415 #define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \ 416 GET_BIT(((_x).video_input_definition), 3) 417 #define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \ 418 GET_BIT(((_x).video_input_definition), 2) 419 #define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \ 420 GET_BIT(((_x).video_input_definition), 1) 421 #define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \ 422 GET_BIT(((_x).video_input_definition), 0) 423 unsigned char max_size_horizontal; 424 unsigned char max_size_vertical; 425 unsigned char gamma; 426 unsigned char feature_support; 427 #define EDID1_INFO_FEATURE_STANDBY(_x) \ 428 GET_BIT(((_x).feature_support), 7) 429 #define EDID1_INFO_FEATURE_SUSPEND(_x) \ 430 GET_BIT(((_x).feature_support), 6) 431 #define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \ 432 GET_BIT(((_x).feature_support), 5) 433 #define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \ 434 GET_BITS(((_x).feature_support), 4, 3) 435 #define EDID1_INFO_FEATURE_RGB(_x) \ 436 GET_BIT(((_x).feature_support), 2) 437 #define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \ 438 GET_BIT(((_x).feature_support), 1) 439 #define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \ 440 GET_BIT(((_x).feature_support), 0) 441 unsigned char color_characteristics[10]; 442 unsigned char established_timings[3]; 443 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \ 444 GET_BIT(((_x).established_timings[0]), 7) 445 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \ 446 GET_BIT(((_x).established_timings[0]), 6) 447 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \ 448 GET_BIT(((_x).established_timings[0]), 5) 449 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \ 450 GET_BIT(((_x).established_timings[0]), 4) 451 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \ 452 GET_BIT(((_x).established_timings[0]), 3) 453 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \ 454 GET_BIT(((_x).established_timings[0]), 2) 455 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \ 456 GET_BIT(((_x).established_timings[0]), 1) 457 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \ 458 GET_BIT(((_x).established_timings[0]), 0) 459 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \ 460 GET_BIT(((_x).established_timings[1]), 7) 461 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \ 462 GET_BIT(((_x).established_timings[1]), 6) 463 #define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \ 464 GET_BIT(((_x).established_timings[1]), 5) 465 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \ 466 GET_BIT(((_x).established_timings[1]), 4) 467 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \ 468 GET_BIT(((_x).established_timings[1]), 3) 469 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \ 470 GET_BIT(((_x).established_timings[1]), 2) 471 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \ 472 GET_BIT(((_x).established_timings[1]), 1) 473 #define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \ 474 GET_BIT(((_x).established_timings[1]), 0) 475 #define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \ 476 GET_BIT(((_x).established_timings[2]), 7) 477 struct { 478 unsigned char xresolution; 479 unsigned char aspect_vfreq; 480 } __attribute__((__packed__)) standard_timings[8]; 481 #define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \ 482 (((_x).standard_timings[_i]).xresolution) 483 #define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \ 484 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6) 485 #define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \ 486 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0) 487 union { 488 unsigned char timing[72]; 489 struct edid_monitor_descriptor descriptor[4]; 490 } monitor_details; 491 unsigned char extension_flag; 492 unsigned char checksum; 493 } __attribute__ ((__packed__)); 494 495 enum edid_cea861_db_types { 496 EDID_CEA861_DB_AUDIO = 0x01, 497 EDID_CEA861_DB_VIDEO = 0x02, 498 EDID_CEA861_DB_VENDOR = 0x03, 499 EDID_CEA861_DB_SPEAKER = 0x04, 500 EDID_CEA861_DB_USE_EXTENDED = 0x07, 501 }; 502 503 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 504 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 505 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 506 #define EDID_BASIC_AUDIO BIT(6) 507 #define EDID_CEA_YCRCB444 BIT(5) 508 #define EDID_CEA_YCRCB422 BIT(4) 509 #define EDID_CEA_VCDB_QS BIT(6) 510 511 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 512 513 struct edid_cea861_info { 514 unsigned char extension_tag; 515 #define EDID_CEA861_EXTENSION_TAG 0x02 516 unsigned char revision; 517 unsigned char dtd_offset; 518 unsigned char dtd_count; 519 #define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \ 520 GET_BIT(((_x).dtd_count), 7) 521 #define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \ 522 GET_BIT(((_x).dtd_count), 6) 523 #define EDID_CEA861_SUPPORTS_YUV444(_x) \ 524 GET_BIT(((_x).dtd_count), 5) 525 #define EDID_CEA861_SUPPORTS_YUV422(_x) \ 526 GET_BIT(((_x).dtd_count), 4) 527 #define EDID_CEA861_DTD_COUNT(_x) \ 528 GET_BITS(((_x).dtd_count), 3, 0) 529 unsigned char data[124]; 530 #define EDID_CEA861_DB_TYPE(_x, offset) \ 531 GET_BITS((_x).data[offset], 7, 5) 532 #define EDID_CEA861_DB_LEN(_x, offset) \ 533 GET_BITS((_x).data[offset], 4, 0) 534 } __attribute__ ((__packed__)); 535 536 #define DATA_BLOCK_PRODUCT_ID 0x00 537 #define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 538 #define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 539 #define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 540 #define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 541 #define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 542 #define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 543 #define DATA_BLOCK_VESA_TIMING 0x07 544 #define DATA_BLOCK_CEA_TIMING 0x08 545 #define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 546 #define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a 547 #define DATA_BLOCK_GP_ASCII_STRING 0x0b 548 #define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c 549 #define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d 550 #define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e 551 #define DATA_BLOCK_DISPLAY_INTERFACE 0x0f 552 #define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 553 #define DATA_BLOCK_TILED_DISPLAY 0x12 554 555 struct displayid_hdr { 556 u8 rev; 557 u8 bytes; 558 u8 prod_id; 559 u8 ext_count; 560 } __packed; 561 562 struct displayid_block { 563 u8 tag; 564 u8 rev; 565 u8 num_bytes; 566 } __packed; 567 568 struct displayid_detailed_timings_1 { 569 u8 pixel_clock[3]; 570 u8 flags; 571 u8 hactive[2]; 572 u8 hblank[2]; 573 u8 hsync[2]; 574 u8 hsw[2]; 575 u8 vactive[2]; 576 u8 vblank[2]; 577 u8 vsync[2]; 578 u8 vsw[2]; 579 } __packed; 580 581 struct displayid_detailed_timing_block { 582 struct displayid_block base; 583 struct displayid_detailed_timings_1 timings[0]; 584 }; 585 586 /** 587 * struct drm_scrambling: sink's scrambling support. 588 */ 589 struct drm_scrambling { 590 /** 591 * @supported: scrambling supported for rates > 340 Mhz. 592 */ 593 bool supported; 594 /** 595 * @low_rates: scrambling supported for rates <= 340 Mhz. 596 */ 597 bool low_rates; 598 }; 599 600 /** 601 * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink 602 * 603 * Provides SCDC register support and capabilities related information on a 604 * HDMI 2.0 sink. In case of a HDMI 1.4 sink, all parameter must be 0. 605 */ 606 607 struct drm_scdc { 608 /** 609 * @supported: status control & data channel present. 610 */ 611 bool supported; 612 /** 613 * @read_request: sink is capable of generating scdc read request. 614 */ 615 bool read_request; 616 /** 617 * @scrambling: sink's scrambling capabilities 618 */ 619 struct drm_scrambling scrambling; 620 }; 621 622 /** 623 * struct drm_hdmi_dsc_cap - DSC capabilities of HDMI sink 624 * 625 * Describes the DSC support provided by HDMI 2.1 sink. 626 * The information is fetched fom additional HFVSDB blocks defined 627 * for HDMI 2.1. 628 */ 629 struct drm_hdmi_dsc_cap { 630 /** @v_1p2: flag for dsc1.2 version support by sink */ 631 bool v_1p2; 632 633 /** @native_420: Does sink support DSC with 4:2:0 compression */ 634 bool native_420; 635 636 /** 637 * @all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2 638 * compressed formats 639 */ 640 bool all_bpp; 641 642 /** 643 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc 644 */ 645 u8 bpc_supported; 646 647 /** @max_slices: maximum number of Horizontal slices supported by */ 648 u8 max_slices; 649 650 /** @clk_per_slice : max pixel clock in MHz supported per slice */ 651 int clk_per_slice; 652 653 /** @max_lanes : dsc max lanes supported for Fixed rate Link training */ 654 u8 max_lanes; 655 656 /** @max_frl_rate_per_lane : maximum frl rate with DSC per lane */ 657 u8 max_frl_rate_per_lane; 658 659 /** @total_chunk_kbytes: max size of chunks in KBs supported per line*/ 660 u8 total_chunk_kbytes; 661 }; 662 663 /** 664 * struct drm_hdmi_info - runtime information about the connected HDMI sink 665 * 666 * Describes if a given display supports advanced HDMI 2.0 features. 667 * This information is available in CEA-861-F extension blocks (like HF-VSDB). 668 */ 669 struct drm_hdmi_info { 670 struct drm_scdc scdc; 671 672 /** 673 * @y420_vdb_modes: bitmap of modes which can support ycbcr420 674 * output only (not normal RGB/YCBCR444/422 outputs). There are total 675 * 107 VICs defined by CEA-861-F spec, so the size is 128 bits to map 676 * upto 128 VICs; 677 */ 678 unsigned long y420_vdb_modes[BITS_TO_LONGS(128)]; 679 680 /** 681 * @y420_cmdb_modes: bitmap of modes which can support ycbcr420 682 * output also, along with normal HDMI outputs. There are total 107 683 * VICs defined by CEA-861-F spec, so the size is 128 bits to map upto 684 * 128 VICs; 685 */ 686 unsigned long y420_cmdb_modes[BITS_TO_LONGS(128)]; 687 688 /** @y420_cmdb_map: bitmap of SVD index, to extraxt vcb modes */ 689 u64 y420_cmdb_map; 690 691 /** @y420_dc_modes: bitmap of deep color support index */ 692 u8 y420_dc_modes; 693 694 /** @max_frl_rate_per_lane: support fixed rate link */ 695 u8 max_frl_rate_per_lane; 696 697 /** @max_lanes: supported by sink */ 698 u8 max_lanes; 699 700 /** @dsc_cap: DSC capabilities of the sink */ 701 struct drm_hdmi_dsc_cap dsc_cap; 702 }; 703 704 enum subpixel_order { 705 subpixelunknown = 0, 706 subpixelhorizontalrgb, 707 subpixelhorizontalbgr, 708 subpixelverticalrgb, 709 subpixelverticalbgr, 710 subpixelnone, 711 }; 712 713 #define DRM_COLOR_FORMAT_RGB444 BIT(0) 714 #define DRM_COLOR_FORMAT_YCRCB444 BIT(1) 715 #define DRM_COLOR_FORMAT_YCRCB422 BIT(2) 716 #define DRM_COLOR_FORMAT_YCRCB420 BIT(3) 717 718 /* 719 * Describes a given display (e.g. CRT or flat panel) and its limitations. 720 */ 721 struct drm_display_info { 722 char name[32]; 723 724 /* Physical size */ 725 unsigned int width_mm; 726 unsigned int height_mm; 727 728 /* Clock limits FIXME: storage format */ 729 unsigned int min_vfreq, max_vfreq; 730 unsigned int min_hfreq, max_hfreq; 731 unsigned int pixel_clock; 732 unsigned int bpc; 733 734 enum subpixel_order subpixel_order; 735 u32 color_formats; 736 737 const u32 *bus_formats; 738 unsigned int num_bus_formats; 739 740 /** 741 * @max_tmds_clock: Maximum TMDS clock rate supported by the 742 * sink in kHz. 0 means undefined. 743 */ 744 int max_tmds_clock; 745 746 /** 747 * @dvi_dual: Dual-link DVI sink? 748 */ 749 bool dvi_dual; 750 751 /* Mask of supported hdmi deep color modes */ 752 u8 edid_hdmi_dc_modes; 753 754 u8 cea_rev; 755 756 /** 757 * @hdmi: advance features of a HDMI sink. 758 */ 759 struct drm_hdmi_info hdmi; 760 }; 761 762 struct edid { 763 u8 header[8]; 764 /* Vendor & product info */ 765 u8 mfg_id[2]; 766 u8 prod_code[2]; 767 u32 serial; /* FIXME: byte order */ 768 u8 mfg_week; 769 u8 mfg_year; 770 /* EDID version */ 771 u8 version; 772 u8 revision; 773 /* Display info: */ 774 u8 input; 775 u8 width_cm; 776 u8 height_cm; 777 u8 gamma; 778 u8 features; 779 /* Color characteristics */ 780 u8 red_green_lo; 781 u8 black_white_lo; 782 u8 red_x; 783 u8 red_y; 784 u8 green_x; 785 u8 green_y; 786 u8 blue_x; 787 u8 blue_y; 788 u8 white_x; 789 u8 white_y; 790 /* Est. timings and mfg rsvd timings*/ 791 struct est_timings established_timings; 792 /* Standard timings 1-8*/ 793 struct std_timing standard_timings[8]; 794 /* Detailing timings 1-4 */ 795 struct detailed_timing detailed_timings[4]; 796 /* Number of 128 byte ext. blocks */ 797 u8 extensions; 798 /* Checksum */ 799 u8 checksum; 800 } __packed; 801 802 enum base_output_format { 803 DRM_HDMI_OUTPUT_DEFAULT_RGB, /* default RGB */ 804 DRM_HDMI_OUTPUT_YCBCR444, /* YCBCR 444 */ 805 DRM_HDMI_OUTPUT_YCBCR422, /* YCBCR 422 */ 806 DRM_HDMI_OUTPUT_YCBCR420, /* YCBCR 420 */ 807 /* (YCbCr444 > YCbCr422 > YCbCr420 > RGB) */ 808 DRM_HDMI_OUTPUT_YCBCR_HQ, 809 /* (YCbCr420 > YCbCr422 > YCbCr444 > RGB) */ 810 DRM_HDMI_OUTPUT_YCBCR_LQ, 811 DRM_HDMI_OUTPUT_INVALID, /* Guess what ? */ 812 }; 813 814 enum base_output_depth { 815 AUTOMATIC = 0, 816 DEPTH_24BIT = 8, 817 DEPTH_30BIT = 10, 818 }; 819 820 struct base_bcsh_info { 821 unsigned short brightness; 822 unsigned short contrast; 823 unsigned short saturation; 824 unsigned short hue; 825 }; 826 827 struct base_overscan { 828 unsigned int maxvalue; 829 unsigned short leftscale; 830 unsigned short rightscale; 831 unsigned short topscale; 832 unsigned short bottomscale; 833 }; 834 835 struct base_drm_display_mode { 836 int clock; /* in kHz */ 837 int hdisplay; 838 int hsync_start; 839 int hsync_end; 840 int htotal; 841 int vdisplay; 842 int vsync_start; 843 int vsync_end; 844 int vtotal; 845 int vrefresh; 846 int vscan; 847 unsigned int flags; 848 int picture_aspect_ratio; 849 }; 850 851 struct base_screen_info { 852 int type; 853 struct base_drm_display_mode mode; /* 52 bytes */ 854 enum base_output_format format; /* 4 bytes */ 855 enum base_output_depth depth; /* 4 bytes */ 856 unsigned int feature; /* 4 bytes */ 857 }; 858 859 struct base_disp_info { 860 struct base_screen_info screen_list[5]; 861 struct base_overscan scan; /* 12 bytes */ 862 }; 863 864 struct base2_cubic_lut_data { 865 u16 size; 866 u16 lred[4913]; 867 u16 lgreen[4913]; 868 u16 lblue[4913]; 869 }; 870 871 struct base2_screen_info { 872 u32 type; 873 u32 id; 874 struct base_drm_display_mode resolution; 875 enum base_output_format format; 876 enum base_output_depth depthc; 877 u32 feature; 878 }; 879 880 struct base2_gamma_lut_data { 881 u16 size; 882 u16 lred[1024]; 883 u16 lgreen[1024]; 884 u16 lblue[1024]; 885 }; 886 887 struct framebuffer_info { 888 u32 framebuffer_width; 889 u32 framebuffer_height; 890 u32 fps; 891 }; 892 893 struct base2_disp_info { 894 char disp_head_flag[6]; 895 struct base2_screen_info screen_info[4]; 896 struct base_bcsh_info bcsh_info; 897 struct base_overscan overscan_info; 898 struct base2_gamma_lut_data gamma_lut_data; 899 struct base2_cubic_lut_data cubic_lut_data; 900 struct framebuffer_info framebuffer_info; 901 u32 reserved[244]; 902 u32 crc; 903 }; 904 905 struct base2_disp_header { 906 u32 connector_type; 907 u32 connector_id; 908 u32 offset; 909 }; 910 911 struct base2_info { 912 char head_flag[4]; 913 u16 major_version; 914 u16 minor_version; 915 struct base2_disp_header disp_header[8]; 916 struct base2_disp_info disp_info[8]; 917 }; 918 919 /** 920 * Print the EDID info. 921 * 922 * @param edid_info The EDID info to be printed 923 */ 924 void edid_print_info(struct edid1_info *edid_info); 925 926 /** 927 * Check the EDID info. 928 * 929 * @param info The EDID info to be checked 930 * @return 0 on valid, or -1 on invalid 931 */ 932 int edid_check_info(struct edid1_info *info); 933 934 /** 935 * Check checksum of a 128 bytes EDID data block 936 * 937 * @param edid_block EDID block data 938 * 939 * @return 0 on success, or a negative errno on error 940 */ 941 int edid_check_checksum(u8 *edid_block); 942 943 /** 944 * Get the horizontal and vertical rate ranges of the monitor. 945 * 946 * @param edid The EDID info 947 * @param hmin Returns the minimum horizontal rate 948 * @param hmax Returns the maximum horizontal rate 949 * @param vmin Returns the minimum vertical rate 950 * @param vmax Returns the maximum vertical rate 951 * @return 0 on success, or -1 on error 952 */ 953 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 954 unsigned int *hmax, unsigned int *vmin, 955 unsigned int *vmax); 956 957 struct drm_display_mode; 958 struct display_timing; 959 960 struct hdmi_edid_data { 961 struct drm_display_mode *preferred_mode; 962 int modes; 963 struct drm_display_mode *mode_buf; 964 struct drm_display_info display_info; 965 }; 966 967 struct ddc_adapter { 968 int (*ddc_xfer)(struct ddc_adapter *adap, struct i2c_msg *msgs, 969 int num); 970 struct udevice *i2c_bus; 971 struct dm_i2c_ops *ops; 972 }; 973 974 /** 975 * edid_get_timing() - Get basic digital display parameters 976 * 977 * @param buf Buffer containing EDID data 978 * @param buf_size Size of buffer in bytes 979 * @param timing Place to put preferring timing information 980 * @param panel_bits_per_colourp Place to put the number of bits per 981 * colour supported by the panel. This will be set to 982 * -1 if not available 983 * @return 0 if timings are OK, -ve on error 984 */ 985 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 986 int *panel_bits_per_colourp); 987 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 988 int *panel_bits_per_colourp); 989 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *edid); 990 bool drm_detect_hdmi_monitor(struct edid *edid); 991 bool drm_detect_monitor_audio(struct edid *edid); 992 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len); 993 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid); 994 enum hdmi_quantization_range 995 drm_default_rgb_quant_range(struct drm_display_mode *mode); 996 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 997 u8 *value); 998 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 999 u8 value); 1000 void drm_mode_sort(struct hdmi_edid_data *edid_data); 1001 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data); 1002 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data); 1003 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 1004 struct base_screen_info *screen_info); 1005 1006 #endif /* __EDID_H_ */ 1007