1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #ifndef __EDID_H_ 15 #define __EDID_H_ 16 17 #include <div64.h> 18 #include <linux/types.h> 19 20 /* Size of the EDID data */ 21 #define EDID_SIZE 128 22 #define EDID_EXT_SIZE 256 23 #define MODE_LEN 120 24 25 #define CEA_EXT 0x02 26 #define VTB_EXT 0x10 27 #define DI_EXT 0x40 28 #define LS_EXT 0x50 29 #define MI_EXT 0x60 30 #define DISPLAYID_EXT 0x70 31 32 #define EDID_TIMING_ASPECT_SHIFT 6 33 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 34 35 /* need to add 60 */ 36 #define EDID_TIMING_VFREQ_SHIFT 0 37 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 38 39 /* OUI of HDMI vendor specific data block */ 40 #define HDMI_IEEE_OUI 0x000c03 41 42 /* drm mode 4k and 3d */ 43 #define DRM_MODE_FLAG_420_MASK (0x03 << 23) 44 #define DRM_MODE_FLAG_420 BIT(23) 45 #define DRM_MODE_FLAG_420_ONLY BIT(24) 46 47 #define DRM_MODE_FLAG_3D_MASK (0x1f << 14) 48 #define DRM_MODE_FLAG_3D_NONE (0 << 14) 49 #define DRM_MODE_FLAG_3D_FRAME_PACKING BIT(14) 50 #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14) 51 #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14) 52 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14) 53 #define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14) 54 #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14) 55 #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14) 56 #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14) 57 58 #define BITS_PER_BYTE 8 59 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) 60 #define GET_BIT(_x, _pos) \ 61 (((_x) >> (_pos)) & 1) 62 #define GET_BITS(_x, _pos_msb, _pos_lsb) \ 63 (((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1)) 64 #define DRM_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 65 .clock = (c), \ 66 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 67 .htotal = (ht), .vdisplay = (vd), \ 68 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 69 .vscan = (vs), .flags = (f) 70 71 /* Aspect ratios used in EDID info. */ 72 enum edid_aspect { 73 ASPECT_625 = 0, 74 ASPECT_75, 75 ASPECT_8, 76 ASPECT_5625, 77 }; 78 79 struct est_timings { 80 u8 t1; 81 u8 t2; 82 u8 mfg_rsvd; 83 } __packed; 84 85 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 86 #define EDID_TIMING_ASPECT_SHIFT 6 87 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 88 89 /* need to add 60 */ 90 #define EDID_TIMING_VFREQ_SHIFT 0 91 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 92 93 struct std_timing { 94 u8 hsize; /* need to multiply by 8 then add 248 */ 95 u8 vfreq_aspect; 96 } __packed; 97 98 struct detailed_pixel_timing { 99 u8 hactive_lo; 100 u8 hblank_lo; 101 u8 hactive_hblank_hi; 102 u8 vactive_lo; 103 u8 vblank_lo; 104 u8 vactive_vblank_hi; 105 u8 hsync_offset_lo; 106 u8 hsync_pulse_width_lo; 107 u8 vsync_offset_pulse_width_lo; 108 u8 hsync_vsync_offset_pulse_width_hi; 109 u8 width_mm_lo; 110 u8 height_mm_lo; 111 u8 width_height_mm_hi; 112 u8 hborder; 113 u8 vborder; 114 u8 misc; 115 } __packed; 116 117 /* If it's not pixel timing, it'll be one of the below */ 118 struct detailed_data_string { 119 u8 str[13]; 120 } __packed; 121 122 struct detailed_data_monitor_range { 123 u8 min_vfreq; 124 u8 max_vfreq; 125 u8 min_hfreq_khz; 126 u8 max_hfreq_khz; 127 u8 pixel_clock_mhz; /* need to multiply by 10 */ 128 u8 flags; 129 union { 130 struct { 131 u8 reserved; 132 u8 hfreq_start_khz; /* need to multiply by 2 */ 133 u8 c; /* need to divide by 2 */ 134 __le16 m; 135 u8 k; 136 u8 j; /* need to divide by 2 */ 137 } __packed gtf2; 138 struct { 139 u8 version; 140 u8 data1; /* high 6 bits: extra clock resolution */ 141 u8 data2; /* plus low 2 of above: max hactive */ 142 u8 supported_aspects; 143 u8 flags; /* preferred aspect and blanking support */ 144 u8 supported_scalings; 145 u8 preferred_refresh; 146 } __packed cvt; 147 } formula; 148 } __packed; 149 150 struct detailed_data_wpindex { 151 u8 white_yx_lo; /* Lower 2 bits each */ 152 u8 white_x_hi; 153 u8 white_y_hi; 154 u8 gamma; /* need to divide by 100 then add 1 */ 155 } __packed; 156 157 struct detailed_data_color_point { 158 u8 windex1; 159 u8 wpindex1[3]; 160 u8 windex2; 161 u8 wpindex2[3]; 162 } __packed; 163 164 struct cvt_timing { 165 u8 code[3]; 166 } __packed; 167 168 struct detailed_non_pixel { 169 u8 pad1; 170 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 171 * fb=color point data, fa=standard timing data, 172 * f9=undefined, f8=mfg. reserved 173 */ 174 u8 pad2; 175 union { 176 struct detailed_data_string str; 177 struct detailed_data_monitor_range range; 178 struct detailed_data_wpindex color; 179 struct std_timing timings[6]; 180 struct cvt_timing cvt[4]; 181 } data; 182 } __packed; 183 184 #define EDID_DETAIL_EST_TIMINGS 0xf7 185 #define EDID_DETAIL_CVT_3BYTE 0xf8 186 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 187 #define EDID_DETAIL_STD_MODES 0xfa 188 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 189 #define EDID_DETAIL_MONITOR_NAME 0xfc 190 #define EDID_DETAIL_MONITOR_RANGE 0xfd 191 #define EDID_DETAIL_MONITOR_STRING 0xfe 192 #define EDID_DETAIL_MONITOR_SERIAL 0xff 193 194 struct detailed_timing { 195 __le16 pixel_clock; /* need to multiply by 10 KHz */ 196 union { 197 struct detailed_pixel_timing pixel_data; 198 struct detailed_non_pixel other_data; 199 } data; 200 } __packed; 201 202 /* Detailed timing information used in EDID v1.x */ 203 struct edid_detailed_timing { 204 unsigned char pixel_clock[2]; 205 #define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \ 206 (((((uint32_t)(_x).pixel_clock[1]) << 8) + \ 207 (_x).pixel_clock[0]) * 10000) 208 unsigned char horizontal_active; 209 unsigned char horizontal_blanking; 210 unsigned char horizontal_active_blanking_hi; 211 #define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \ 212 ((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \ 213 (_x).horizontal_active) 214 #define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \ 215 ((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \ 216 (_x).horizontal_blanking) 217 unsigned char vertical_active; 218 unsigned char vertical_blanking; 219 unsigned char vertical_active_blanking_hi; 220 #define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \ 221 ((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \ 222 (_x).vertical_active) 223 #define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \ 224 ((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \ 225 (_x).vertical_blanking) 226 unsigned char hsync_offset; 227 unsigned char hsync_pulse_width; 228 unsigned char vsync_offset_pulse_width; 229 unsigned char hsync_vsync_offset_pulse_width_hi; 230 #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \ 231 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \ 232 (_x).hsync_offset) 233 #define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \ 234 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \ 235 (_x).hsync_pulse_width) 236 #define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \ 237 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \ 238 GET_BITS((_x).vsync_offset_pulse_width, 7, 4)) 239 #define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \ 240 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \ 241 GET_BITS((_x).vsync_offset_pulse_width, 3, 0)) 242 unsigned char himage_size; 243 unsigned char vimage_size; 244 unsigned char himage_vimage_size_hi; 245 #define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \ 246 ((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size) 247 #define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \ 248 ((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size) 249 unsigned char hborder; 250 unsigned char vborder; 251 unsigned char flags; 252 #define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \ 253 GET_BIT((_x).flags, 7) 254 #define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \ 255 GET_BITS((_x).flags, 6, 5) 256 #define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \ 257 GET_BITS((_x).flags, 4, 3) 258 #define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \ 259 GET_BITS((_x).flags, 2, 1) 260 #define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \ 261 GET_BIT((_x).flags, 2) 262 #define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \ 263 GET_BIT((_x).flags, 1) 264 #define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \ 265 GET_BIT((_x).flags, 0) 266 } __attribute__ ((__packed__)); 267 268 enum edid_monitor_descriptor_types { 269 EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff, 270 EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe, 271 EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd, 272 EDID_MONITOR_DESCRIPTOR_NAME = 0xfc, 273 }; 274 275 struct edid_monitor_descriptor { 276 uint16_t zero_flag_1; 277 unsigned char zero_flag_2; 278 unsigned char type; 279 unsigned char zero_flag_3; 280 union { 281 char string[13]; 282 struct { 283 unsigned char vertical_min; 284 unsigned char vertical_max; 285 unsigned char horizontal_min; 286 unsigned char horizontal_max; 287 unsigned char pixel_clock_max; 288 unsigned char gtf_data[8]; 289 } range_data; 290 } data; 291 } __attribute__ ((__packed__)); 292 293 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 294 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 295 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 296 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 297 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 298 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 299 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 300 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 301 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 302 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 303 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 304 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 305 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 306 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 307 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 308 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 309 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 310 #define DRM_EDID_DIGITAL_TYPE_DVI (1) 311 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 312 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 313 #define DRM_EDID_DIGITAL_TYPE_MDDI (4) 314 #define DRM_EDID_DIGITAL_TYPE_DP (5) 315 316 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 317 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 318 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 319 /* If analog */ 320 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 321 /* If digital */ 322 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 323 #define DRM_EDID_FEATURE_RGB (0 << 3) 324 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 325 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 326 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 327 328 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 329 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 330 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 331 332 #define DRM_EDID_HDMI_DC_48 (1 << 6) 333 #define DRM_EDID_HDMI_DC_36 (1 << 5) 334 #define DRM_EDID_HDMI_DC_30 (1 << 4) 335 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 336 337 /* YCBCR 420 deep color modes */ 338 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 339 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 340 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 341 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 342 DRM_EDID_YCBCR420_DC_36 | \ 343 DRM_EDID_YCBCR420_DC_30) 344 345 struct edid1_info { 346 unsigned char header[8]; 347 unsigned char manufacturer_name[2]; 348 #define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \ 349 GET_BIT(((_x).manufacturer_name[0]), 7) 350 #define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \ 351 GET_BITS(((_x).manufacturer_name[0]), 6, 2) 352 #define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \ 353 ((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \ 354 GET_BITS(((_x).manufacturer_name[1]), 7, 5)) 355 #define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \ 356 GET_BITS(((_x).manufacturer_name[1]), 4, 0) 357 unsigned char product_code[2]; 358 #define EDID1_INFO_PRODUCT_CODE(_x) \ 359 (((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0]) 360 unsigned char serial_number[4]; 361 #define EDID1_INFO_SERIAL_NUMBER(_x) \ 362 (((uint32_t)(_x).serial_number[3] << 24) + \ 363 ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \ 364 (_x).serial_number[0]) 365 unsigned char week; 366 unsigned char year; 367 unsigned char version; 368 unsigned char revision; 369 unsigned char video_input_definition; 370 #define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \ 371 GET_BIT(((_x).video_input_definition), 7) 372 #define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \ 373 GET_BITS(((_x).video_input_definition), 6, 5) 374 #define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \ 375 GET_BIT(((_x).video_input_definition), 4) 376 #define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \ 377 GET_BIT(((_x).video_input_definition), 3) 378 #define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \ 379 GET_BIT(((_x).video_input_definition), 2) 380 #define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \ 381 GET_BIT(((_x).video_input_definition), 1) 382 #define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \ 383 GET_BIT(((_x).video_input_definition), 0) 384 unsigned char max_size_horizontal; 385 unsigned char max_size_vertical; 386 unsigned char gamma; 387 unsigned char feature_support; 388 #define EDID1_INFO_FEATURE_STANDBY(_x) \ 389 GET_BIT(((_x).feature_support), 7) 390 #define EDID1_INFO_FEATURE_SUSPEND(_x) \ 391 GET_BIT(((_x).feature_support), 6) 392 #define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \ 393 GET_BIT(((_x).feature_support), 5) 394 #define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \ 395 GET_BITS(((_x).feature_support), 4, 3) 396 #define EDID1_INFO_FEATURE_RGB(_x) \ 397 GET_BIT(((_x).feature_support), 2) 398 #define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \ 399 GET_BIT(((_x).feature_support), 1) 400 #define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \ 401 GET_BIT(((_x).feature_support), 0) 402 unsigned char color_characteristics[10]; 403 unsigned char established_timings[3]; 404 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \ 405 GET_BIT(((_x).established_timings[0]), 7) 406 #define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \ 407 GET_BIT(((_x).established_timings[0]), 6) 408 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \ 409 GET_BIT(((_x).established_timings[0]), 5) 410 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \ 411 GET_BIT(((_x).established_timings[0]), 4) 412 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \ 413 GET_BIT(((_x).established_timings[0]), 3) 414 #define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \ 415 GET_BIT(((_x).established_timings[0]), 2) 416 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \ 417 GET_BIT(((_x).established_timings[0]), 1) 418 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \ 419 GET_BIT(((_x).established_timings[0]), 0) 420 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \ 421 GET_BIT(((_x).established_timings[1]), 7) 422 #define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \ 423 GET_BIT(((_x).established_timings[1]), 6) 424 #define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \ 425 GET_BIT(((_x).established_timings[1]), 5) 426 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \ 427 GET_BIT(((_x).established_timings[1]), 4) 428 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \ 429 GET_BIT(((_x).established_timings[1]), 3) 430 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \ 431 GET_BIT(((_x).established_timings[1]), 2) 432 #define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \ 433 GET_BIT(((_x).established_timings[1]), 1) 434 #define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \ 435 GET_BIT(((_x).established_timings[1]), 0) 436 #define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \ 437 GET_BIT(((_x).established_timings[2]), 7) 438 struct { 439 unsigned char xresolution; 440 unsigned char aspect_vfreq; 441 } __attribute__((__packed__)) standard_timings[8]; 442 #define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \ 443 (((_x).standard_timings[_i]).xresolution) 444 #define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \ 445 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6) 446 #define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \ 447 GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0) 448 union { 449 unsigned char timing[72]; 450 struct edid_monitor_descriptor descriptor[4]; 451 } monitor_details; 452 unsigned char extension_flag; 453 unsigned char checksum; 454 } __attribute__ ((__packed__)); 455 456 enum edid_cea861_db_types { 457 EDID_CEA861_DB_AUDIO = 0x01, 458 EDID_CEA861_DB_VIDEO = 0x02, 459 EDID_CEA861_DB_VENDOR = 0x03, 460 EDID_CEA861_DB_SPEAKER = 0x04, 461 EDID_CEA861_DB_USE_EXTENDED = 0x07, 462 }; 463 464 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 465 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 466 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 467 #define EDID_BASIC_AUDIO BIT(6) 468 #define EDID_CEA_YCRCB444 BIT(5) 469 #define EDID_CEA_YCRCB422 BIT(4) 470 #define EDID_CEA_VCDB_QS BIT(6) 471 472 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 473 474 struct edid_cea861_info { 475 unsigned char extension_tag; 476 #define EDID_CEA861_EXTENSION_TAG 0x02 477 unsigned char revision; 478 unsigned char dtd_offset; 479 unsigned char dtd_count; 480 #define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \ 481 GET_BIT(((_x).dtd_count), 7) 482 #define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \ 483 GET_BIT(((_x).dtd_count), 6) 484 #define EDID_CEA861_SUPPORTS_YUV444(_x) \ 485 GET_BIT(((_x).dtd_count), 5) 486 #define EDID_CEA861_SUPPORTS_YUV422(_x) \ 487 GET_BIT(((_x).dtd_count), 4) 488 #define EDID_CEA861_DTD_COUNT(_x) \ 489 GET_BITS(((_x).dtd_count), 3, 0) 490 unsigned char data[124]; 491 #define EDID_CEA861_DB_TYPE(_x, offset) \ 492 GET_BITS((_x).data[offset], 7, 5) 493 #define EDID_CEA861_DB_LEN(_x, offset) \ 494 GET_BITS((_x).data[offset], 4, 0) 495 } __attribute__ ((__packed__)); 496 497 #define DATA_BLOCK_PRODUCT_ID 0x00 498 #define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 499 #define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 500 #define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 501 #define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 502 #define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 503 #define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 504 #define DATA_BLOCK_VESA_TIMING 0x07 505 #define DATA_BLOCK_CEA_TIMING 0x08 506 #define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 507 #define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a 508 #define DATA_BLOCK_GP_ASCII_STRING 0x0b 509 #define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c 510 #define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d 511 #define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e 512 #define DATA_BLOCK_DISPLAY_INTERFACE 0x0f 513 #define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 514 #define DATA_BLOCK_TILED_DISPLAY 0x12 515 516 struct displayid_hdr { 517 u8 rev; 518 u8 bytes; 519 u8 prod_id; 520 u8 ext_count; 521 } __packed; 522 523 struct displayid_block { 524 u8 tag; 525 u8 rev; 526 u8 num_bytes; 527 } __packed; 528 529 struct displayid_detailed_timings_1 { 530 u8 pixel_clock[3]; 531 u8 flags; 532 u8 hactive[2]; 533 u8 hblank[2]; 534 u8 hsync[2]; 535 u8 hsw[2]; 536 u8 vactive[2]; 537 u8 vblank[2]; 538 u8 vsync[2]; 539 u8 vsw[2]; 540 } __packed; 541 542 struct displayid_detailed_timing_block { 543 struct displayid_block base; 544 struct displayid_detailed_timings_1 timings[0]; 545 }; 546 547 /** 548 * struct drm_scrambling: sink's scrambling support. 549 */ 550 struct drm_scrambling { 551 /** 552 * @supported: scrambling supported for rates > 340 Mhz. 553 */ 554 bool supported; 555 /** 556 * @low_rates: scrambling supported for rates <= 340 Mhz. 557 */ 558 bool low_rates; 559 }; 560 561 /** 562 * struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink 563 * 564 * Provides SCDC register support and capabilities related information on a 565 * HDMI 2.0 sink. In case of a HDMI 1.4 sink, all parameter must be 0. 566 */ 567 568 struct drm_scdc { 569 /** 570 * @supported: status control & data channel present. 571 */ 572 bool supported; 573 /** 574 * @read_request: sink is capable of generating scdc read request. 575 */ 576 bool read_request; 577 /** 578 * @scrambling: sink's scrambling capabilities 579 */ 580 struct drm_scrambling scrambling; 581 }; 582 583 /** 584 * struct drm_hdmi_info - runtime information about the connected HDMI sink 585 * 586 * Describes if a given display supports advanced HDMI 2.0 features. 587 * This information is available in CEA-861-F extension blocks (like HF-VSDB). 588 */ 589 struct drm_hdmi_info { 590 struct drm_scdc scdc; 591 592 /** 593 * @y420_vdb_modes: bitmap of modes which can support ycbcr420 594 * output only (not normal RGB/YCBCR444/422 outputs). There are total 595 * 107 VICs defined by CEA-861-F spec, so the size is 128 bits to map 596 * upto 128 VICs; 597 */ 598 unsigned long y420_vdb_modes[BITS_TO_LONGS(128)]; 599 600 /** 601 * @y420_cmdb_modes: bitmap of modes which can support ycbcr420 602 * output also, along with normal HDMI outputs. There are total 107 603 * VICs defined by CEA-861-F spec, so the size is 128 bits to map upto 604 * 128 VICs; 605 */ 606 unsigned long y420_cmdb_modes[BITS_TO_LONGS(128)]; 607 608 /** @y420_cmdb_map: bitmap of SVD index, to extraxt vcb modes */ 609 u64 y420_cmdb_map; 610 611 /** @y420_dc_modes: bitmap of deep color support index */ 612 u8 y420_dc_modes; 613 }; 614 615 enum subpixel_order { 616 subpixelunknown = 0, 617 subpixelhorizontalrgb, 618 subpixelhorizontalbgr, 619 subpixelverticalrgb, 620 subpixelverticalbgr, 621 subpixelnone, 622 }; 623 624 #define DRM_COLOR_FORMAT_RGB444 BIT(0) 625 #define DRM_COLOR_FORMAT_YCRCB444 BIT(1) 626 #define DRM_COLOR_FORMAT_YCRCB422 BIT(2) 627 #define DRM_COLOR_FORMAT_YCRCB420 BIT(3) 628 629 /* 630 * Describes a given display (e.g. CRT or flat panel) and its limitations. 631 */ 632 struct drm_display_info { 633 char name[32]; 634 635 /* Physical size */ 636 unsigned int width_mm; 637 unsigned int height_mm; 638 639 /* Clock limits FIXME: storage format */ 640 unsigned int min_vfreq, max_vfreq; 641 unsigned int min_hfreq, max_hfreq; 642 unsigned int pixel_clock; 643 unsigned int bpc; 644 645 enum subpixel_order subpixel_order; 646 u32 color_formats; 647 648 const u32 *bus_formats; 649 unsigned int num_bus_formats; 650 651 /** 652 * @max_tmds_clock: Maximum TMDS clock rate supported by the 653 * sink in kHz. 0 means undefined. 654 */ 655 int max_tmds_clock; 656 657 /** 658 * @dvi_dual: Dual-link DVI sink? 659 */ 660 bool dvi_dual; 661 662 /* Mask of supported hdmi deep color modes */ 663 u8 edid_hdmi_dc_modes; 664 665 u8 cea_rev; 666 667 /** 668 * @hdmi: advance features of a HDMI sink. 669 */ 670 struct drm_hdmi_info hdmi; 671 }; 672 673 struct edid { 674 u8 header[8]; 675 /* Vendor & product info */ 676 u8 mfg_id[2]; 677 u8 prod_code[2]; 678 u32 serial; /* FIXME: byte order */ 679 u8 mfg_week; 680 u8 mfg_year; 681 /* EDID version */ 682 u8 version; 683 u8 revision; 684 /* Display info: */ 685 u8 input; 686 u8 width_cm; 687 u8 height_cm; 688 u8 gamma; 689 u8 features; 690 /* Color characteristics */ 691 u8 red_green_lo; 692 u8 black_white_lo; 693 u8 red_x; 694 u8 red_y; 695 u8 green_x; 696 u8 green_y; 697 u8 blue_x; 698 u8 blue_y; 699 u8 white_x; 700 u8 white_y; 701 /* Est. timings and mfg rsvd timings*/ 702 struct est_timings established_timings; 703 /* Standard timings 1-8*/ 704 struct std_timing standard_timings[8]; 705 /* Detailing timings 1-4 */ 706 struct detailed_timing detailed_timings[4]; 707 /* Number of 128 byte ext. blocks */ 708 u8 extensions; 709 /* Checksum */ 710 u8 checksum; 711 } __packed; 712 713 /** 714 * Print the EDID info. 715 * 716 * @param edid_info The EDID info to be printed 717 */ 718 void edid_print_info(struct edid1_info *edid_info); 719 720 /** 721 * Check the EDID info. 722 * 723 * @param info The EDID info to be checked 724 * @return 0 on valid, or -1 on invalid 725 */ 726 int edid_check_info(struct edid1_info *info); 727 728 /** 729 * Check checksum of a 128 bytes EDID data block 730 * 731 * @param edid_block EDID block data 732 * 733 * @return 0 on success, or a negative errno on error 734 */ 735 int edid_check_checksum(u8 *edid_block); 736 737 /** 738 * Get the horizontal and vertical rate ranges of the monitor. 739 * 740 * @param edid The EDID info 741 * @param hmin Returns the minimum horizontal rate 742 * @param hmax Returns the maximum horizontal rate 743 * @param vmin Returns the minimum vertical rate 744 * @param vmax Returns the maximum vertical rate 745 * @return 0 on success, or -1 on error 746 */ 747 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 748 unsigned int *hmax, unsigned int *vmin, 749 unsigned int *vmax); 750 751 struct drm_display_mode; 752 struct display_timing; 753 754 struct hdmi_edid_data { 755 struct drm_display_mode *preferred_mode; 756 int modes; 757 struct drm_hdmi_info hdmi_info; 758 struct drm_display_mode *mode_buf; 759 struct drm_display_info display_info; 760 }; 761 762 /** 763 * edid_get_timing() - Get basic digital display parameters 764 * 765 * @param buf Buffer containing EDID data 766 * @param buf_size Size of buffer in bytes 767 * @param timing Place to put preferring timing information 768 * @param panel_bits_per_colourp Place to put the number of bits per 769 * colour supported by the panel. This will be set to 770 * -1 if not available 771 * @return 0 if timings are OK, -ve on error 772 */ 773 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 774 int *panel_bits_per_colourp); 775 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 776 int *panel_bits_per_colourp); 777 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *edid); 778 bool drm_detect_hdmi_monitor(struct edid *edid); 779 bool drm_detect_monitor_audio(struct edid *edid); 780 781 #endif /* __EDID_H_ */ 782