1*42d1f039Swdenk /* 2*42d1f039Swdenk * Copyright 2003 Motorola,Inc. 3*42d1f039Swdenk * Xianghua Xiao(x.xiao@motorola.com) 4*42d1f039Swdenk */ 5*42d1f039Swdenk 6*42d1f039Swdenk #ifndef __E500_H__ 7*42d1f039Swdenk #define __E500_H__ 8*42d1f039Swdenk 9*42d1f039Swdenk #ifndef __ASSEMBLY__ 10*42d1f039Swdenk 11*42d1f039Swdenk typedef struct 12*42d1f039Swdenk { 13*42d1f039Swdenk unsigned long freqProcessor; 14*42d1f039Swdenk unsigned long freqSystemBus; 15*42d1f039Swdenk } MPC85xx_SYS_INFO; 16*42d1f039Swdenk 17*42d1f039Swdenk #endif /* _ASMLANGUAGE */ 18*42d1f039Swdenk 19*42d1f039Swdenk /* Motorola E500 core provides 16 TLB1 entries; they can be used for 20*42d1f039Swdenk * initial memory mapping like legacy BAT registers do. Usually we 21*42d1f039Swdenk * use four MAS registers(MAS0-3) to operate on TLB1 entries. 22*42d1f039Swdenk * 23*42d1f039Swdenk * We also need LAWs(Local Access Window) to associate a range of 24*42d1f039Swdenk * the local 32-bit address space with a particular target interface 25*42d1f039Swdenk * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. 26*42d1f039Swdenk * 27*42d1f039Swdenk * We put TLB1/LAW code here because memory mapping is board-specific 28*42d1f039Swdenk * instead of cpu-specific. 29*42d1f039Swdenk */ 30*42d1f039Swdenk 31*42d1f039Swdenk /* MAS0 32*42d1f039Swdenk * tlbsel(TLB Select):0,1 33*42d1f039Swdenk * esel(Entry Select): 0,1,2,...,15 for TLB1 34*42d1f039Swdenk * nv(Next victim):0,1 35*42d1f039Swdenk */ 36*42d1f039Swdenk #define TLB1_MAS0(tlbsel,esel,nv) \ 37*42d1f039Swdenk ((((tlbsel) << 28) & MAS0_TLBSEL) |\ 38*42d1f039Swdenk (((esel) << 16) & MAS0_ESEL ) |\ 39*42d1f039Swdenk (nv) ) 40*42d1f039Swdenk 41*42d1f039Swdenk 42*42d1f039Swdenk /* MAS1 43*42d1f039Swdenk * v(TLB valid bit):0,1 44*42d1f039Swdenk * iprot(invalidate protect):0,1 45*42d1f039Swdenk * tid(translation identity):8bit to match process IDs 46*42d1f039Swdenk * ts(translation space,comparing with MSR[IS,DS]): 0,1 47*42d1f039Swdenk * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) 48*42d1f039Swdenk */ 49*42d1f039Swdenk #define TLB1_MAS1(v,iprot,tid,ts,tsize) \ 50*42d1f039Swdenk ((((v) << 31) & MAS1_VALID) |\ 51*42d1f039Swdenk (((iprot) << 30) & MAS1_IPROT) |\ 52*42d1f039Swdenk (((tid) << 16) & MAS1_TID) |\ 53*42d1f039Swdenk (((ts) << 12) & MAS1_TS) |\ 54*42d1f039Swdenk (((tsize) << 8) & MAS1_TSIZE) ) 55*42d1f039Swdenk 56*42d1f039Swdenk 57*42d1f039Swdenk /* MAS2 58*42d1f039Swdenk * epn(effective page number):20bits 59*42d1f039Swdenk * sharen(Shared cache state):0,1 60*42d1f039Swdenk * x0,x1(implementation specific page attribute):0,1 61*42d1f039Swdenk * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, 62*42d1f039Swdenk * endianness):0,1 63*42d1f039Swdenk */ 64*42d1f039Swdenk #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ 65*42d1f039Swdenk ((((epn) << 12) & MAS2_EPN) |\ 66*42d1f039Swdenk (((sharen) << 9) & MAS2_SHAREN) |\ 67*42d1f039Swdenk (((x0) << 6) & MAS2_X0) |\ 68*42d1f039Swdenk (((x1) << 5) & MAS2_X1) |\ 69*42d1f039Swdenk (((w) << 4) & MAS2_W) |\ 70*42d1f039Swdenk (((i) << 3) & MAS2_I) |\ 71*42d1f039Swdenk (((m) << 2) & MAS2_M) |\ 72*42d1f039Swdenk (((g) << 1) & MAS2_G) |\ 73*42d1f039Swdenk (e) ) 74*42d1f039Swdenk 75*42d1f039Swdenk 76*42d1f039Swdenk /* MAS3 77*42d1f039Swdenk * rpn(real page number):20bits 78*42d1f039Swdenk * u0-u3(user bits, useful for page table management in OS):0,1 79*42d1f039Swdenk * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, 80*42d1f039Swdenk * write,execute permission). 81*42d1f039Swdenk */ 82*42d1f039Swdenk #define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ 83*42d1f039Swdenk ((((rpn) << 12) & MAS3_RPN) |\ 84*42d1f039Swdenk (((u0) << 9) & MAS3_U0) |\ 85*42d1f039Swdenk (((u1) << 8) & MAS3_U1) |\ 86*42d1f039Swdenk (((u2) << 7) & MAS3_U2) |\ 87*42d1f039Swdenk (((u3) << 6) & MAS3_U3) |\ 88*42d1f039Swdenk (((ux) << 5) & MAS3_UX) |\ 89*42d1f039Swdenk (((sx) << 4) & MAS3_SX) |\ 90*42d1f039Swdenk (((uw) << 3) & MAS3_UW) |\ 91*42d1f039Swdenk (((sw) << 2) & MAS3_SW) |\ 92*42d1f039Swdenk (((ur) << 1) & MAS3_UR) |\ 93*42d1f039Swdenk (sr) ) 94*42d1f039Swdenk 95*42d1f039Swdenk 96*42d1f039Swdenk #define RESET_VECTOR 0xfffffffc 97*42d1f039Swdenk #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache 98*42d1f039Swdenk line aligned data. */ 99*42d1f039Swdenk 100*42d1f039Swdenk #endif /* __E500_H__ */ 101