151c580c6SStefan Roese /* 251c580c6SStefan Roese * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 351c580c6SStefan Roese * 4*f37a1266SStefan Roese * SPDX-License-Identifier: GPL-2.0 551c580c6SStefan Roese */ 651c580c6SStefan Roese 751c580c6SStefan Roese #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 851c580c6SStefan Roese #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 951c580c6SStefan Roese 1051c580c6SStefan Roese /* MPUMODRST */ 1151c580c6SStefan Roese #define CPU0_RESET 0 1251c580c6SStefan Roese #define CPU1_RESET 1 1351c580c6SStefan Roese #define WDS_RESET 2 1451c580c6SStefan Roese #define SCUPER_RESET 3 1551c580c6SStefan Roese #define L2_RESET 4 1651c580c6SStefan Roese 1751c580c6SStefan Roese /* PERMODRST */ 1851c580c6SStefan Roese #define EMAC0_RESET 32 1951c580c6SStefan Roese #define EMAC1_RESET 33 2051c580c6SStefan Roese #define USB0_RESET 34 2151c580c6SStefan Roese #define USB1_RESET 35 2251c580c6SStefan Roese #define NAND_RESET 36 2351c580c6SStefan Roese #define QSPI_RESET 37 2451c580c6SStefan Roese #define L4WD0_RESET 38 2551c580c6SStefan Roese #define L4WD1_RESET 39 2651c580c6SStefan Roese #define OSC1TIMER0_RESET 40 2751c580c6SStefan Roese #define OSC1TIMER1_RESET 41 2851c580c6SStefan Roese #define SPTIMER0_RESET 42 2951c580c6SStefan Roese #define SPTIMER1_RESET 43 3051c580c6SStefan Roese #define I2C0_RESET 44 3151c580c6SStefan Roese #define I2C1_RESET 45 3251c580c6SStefan Roese #define I2C2_RESET 46 3351c580c6SStefan Roese #define I2C3_RESET 47 3451c580c6SStefan Roese #define UART0_RESET 48 3551c580c6SStefan Roese #define UART1_RESET 49 3651c580c6SStefan Roese #define SPIM0_RESET 50 3751c580c6SStefan Roese #define SPIM1_RESET 51 3851c580c6SStefan Roese #define SPIS0_RESET 52 3951c580c6SStefan Roese #define SPIS1_RESET 53 4051c580c6SStefan Roese #define SDMMC_RESET 54 4151c580c6SStefan Roese #define CAN0_RESET 55 4251c580c6SStefan Roese #define CAN1_RESET 56 4351c580c6SStefan Roese #define GPIO0_RESET 57 4451c580c6SStefan Roese #define GPIO1_RESET 58 4551c580c6SStefan Roese #define GPIO2_RESET 59 4651c580c6SStefan Roese #define DMA_RESET 60 4751c580c6SStefan Roese #define SDR_RESET 61 4851c580c6SStefan Roese 4951c580c6SStefan Roese /* PER2MODRST */ 5051c580c6SStefan Roese #define DMAIF0_RESET 64 5151c580c6SStefan Roese #define DMAIF1_RESET 65 5251c580c6SStefan Roese #define DMAIF2_RESET 66 5351c580c6SStefan Roese #define DMAIF3_RESET 67 5451c580c6SStefan Roese #define DMAIF4_RESET 68 5551c580c6SStefan Roese #define DMAIF5_RESET 69 5651c580c6SStefan Roese #define DMAIF6_RESET 70 5751c580c6SStefan Roese #define DMAIF7_RESET 71 5851c580c6SStefan Roese 5951c580c6SStefan Roese /* BRGMODRST */ 6051c580c6SStefan Roese #define HPS2FPGA_RESET 96 6151c580c6SStefan Roese #define LWHPS2FPGA_RESET 97 6251c580c6SStefan Roese #define FPGA2HPS_RESET 98 6351c580c6SStefan Roese 6451c580c6SStefan Roese /* MISCMODRST*/ 6551c580c6SStefan Roese #define ROM_RESET 128 6651c580c6SStefan Roese #define OCRAM_RESET 129 6751c580c6SStefan Roese #define SYSMGR_RESET 130 6851c580c6SStefan Roese #define SYSMGRCOLD_RESET 131 6951c580c6SStefan Roese #define FPGAMGR_RESET 132 7051c580c6SStefan Roese #define ACPIDMAP_RESET 133 7151c580c6SStefan Roese #define S2F_RESET 134 7251c580c6SStefan Roese #define S2FCOLD_RESET 135 7351c580c6SStefan Roese #define NRSTPIN_RESET 136 7451c580c6SStefan Roese #define TIMESTAMPCOLD_RESET 137 7551c580c6SStefan Roese #define CLKMGRCOLD_RESET 138 7651c580c6SStefan Roese #define SCANMGR_RESET 139 7751c580c6SStefan Roese #define FRZCTRLCOLD_RESET 140 7851c580c6SStefan Roese #define SYSDBG_RESET 141 7951c580c6SStefan Roese #define DBG_RESET 142 8051c580c6SStefan Roese #define TAPCOLD_RESET 143 8151c580c6SStefan Roese #define SDRCOLD_RESET 144 8251c580c6SStefan Roese 8351c580c6SStefan Roese #endif 84