1*b965fc57SElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 2*b965fc57SElaine Zhang #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ 3*b965fc57SElaine Zhang #define __DT_BINDINGS_POWER_RK3588_POWER_H__ 4*b965fc57SElaine Zhang 5*b965fc57SElaine Zhang /* VD_LITDSU */ 6*b965fc57SElaine Zhang #define RK3588_PD_CPU_0 0 7*b965fc57SElaine Zhang #define RK3588_PD_CPU_1 1 8*b965fc57SElaine Zhang #define RK3588_PD_CPU_2 2 9*b965fc57SElaine Zhang #define RK3588_PD_CPU_3 3 10*b965fc57SElaine Zhang 11*b965fc57SElaine Zhang /* VD_BIGCORE0 */ 12*b965fc57SElaine Zhang #define RK3588_PD_CPU_4 4 13*b965fc57SElaine Zhang #define RK3588_PD_CPU_5 5 14*b965fc57SElaine Zhang 15*b965fc57SElaine Zhang /* VD_BIGCORE1 */ 16*b965fc57SElaine Zhang #define RK3588_PD_CPU_6 6 17*b965fc57SElaine Zhang #define RK3588_PD_CPU_7 7 18*b965fc57SElaine Zhang 19*b965fc57SElaine Zhang /* VD_NPU */ 20*b965fc57SElaine Zhang #define RK3588_PD_NPU 8 21*b965fc57SElaine Zhang #define RK3588_PD_NPUTOP 9 22*b965fc57SElaine Zhang #define RK3588_PD_NPU1 10 23*b965fc57SElaine Zhang #define RK3588_PD_NPU2 11 24*b965fc57SElaine Zhang 25*b965fc57SElaine Zhang /* VD_GPU */ 26*b965fc57SElaine Zhang #define RK3588_PD_GPU 12 27*b965fc57SElaine Zhang 28*b965fc57SElaine Zhang /* VD_VCODEC */ 29*b965fc57SElaine Zhang #define RK3588_PD_VCODEC 13 30*b965fc57SElaine Zhang #define RK3588_PD_RKVDEC0 14 31*b965fc57SElaine Zhang #define RK3588_PD_RKVDEC1 15 32*b965fc57SElaine Zhang #define RK3588_PD_VENC0 16 33*b965fc57SElaine Zhang #define RK3588_PD_VENC1 17 34*b965fc57SElaine Zhang 35*b965fc57SElaine Zhang /* VD_DD01 */ 36*b965fc57SElaine Zhang #define RK3588_PD_DDR01 18 37*b965fc57SElaine Zhang 38*b965fc57SElaine Zhang /* VD_DD23 */ 39*b965fc57SElaine Zhang #define RK3588_PD_DDR23 19 40*b965fc57SElaine Zhang 41*b965fc57SElaine Zhang /* VD_LOGIC */ 42*b965fc57SElaine Zhang #define RK3588_PD_CENTER 20 43*b965fc57SElaine Zhang #define RK3588_PD_VDPU 21 44*b965fc57SElaine Zhang #define RK3588_PD_RGA30 22 45*b965fc57SElaine Zhang #define RK3588_PD_AV1 23 46*b965fc57SElaine Zhang #define RK3588_PD_VOP 24 47*b965fc57SElaine Zhang #define RK3588_PD_VO0 25 48*b965fc57SElaine Zhang #define RK3588_PD_VO1 26 49*b965fc57SElaine Zhang #define RK3588_PD_VI 27 50*b965fc57SElaine Zhang #define RK3588_PD_ISP1 28 51*b965fc57SElaine Zhang #define RK3588_PD_FEC 29 52*b965fc57SElaine Zhang #define RK3588_PD_RGA31 30 53*b965fc57SElaine Zhang #define RK3588_PD_USB 31 54*b965fc57SElaine Zhang #define RK3588_PD_PHP 32 55*b965fc57SElaine Zhang #define RK3588_PD_GMAC 33 56*b965fc57SElaine Zhang #define RK3588_PD_PCIE 34 57*b965fc57SElaine Zhang #define RK3588_PD_NVM 35 58*b965fc57SElaine Zhang #define RK3588_PD_NVM0 36 59*b965fc57SElaine Zhang #define RK3588_PD_SDIO 37 60*b965fc57SElaine Zhang #define RK3588_PD_AUDIO 38 61*b965fc57SElaine Zhang #define RK3588_PD_SECURE 39 62*b965fc57SElaine Zhang #define RK3588_PD_SDMMC 40 63*b965fc57SElaine Zhang #define RK3588_PD_CRYPTO 41 64*b965fc57SElaine Zhang #define RK3588_PD_BUS 42 65*b965fc57SElaine Zhang 66*b965fc57SElaine Zhang /* VD_PMU */ 67*b965fc57SElaine Zhang #define RK3588_PD_PMU1 43 68*b965fc57SElaine Zhang 69*b965fc57SElaine Zhang #endif 70