1*be7064f8SJoseph Chen /* SPDX-License-Identifier: GPL-2.0 */ 2*be7064f8SJoseph Chen #ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ 3*be7064f8SJoseph Chen #define __DT_BINDINGS_POWER_RK3568_POWER_H__ 4*be7064f8SJoseph Chen 5*be7064f8SJoseph Chen /* VD_CORE */ 6*be7064f8SJoseph Chen #define RK3568_PD_CPU_0 0 7*be7064f8SJoseph Chen #define RK3568_PD_CPU_1 1 8*be7064f8SJoseph Chen #define RK3568_PD_CPU_2 2 9*be7064f8SJoseph Chen #define RK3568_PD_CPU_3 3 10*be7064f8SJoseph Chen #define RK3568_PD_CORE_ALIVE 4 11*be7064f8SJoseph Chen 12*be7064f8SJoseph Chen /* VD_PMU */ 13*be7064f8SJoseph Chen #define RK3568_PD_PMU 5 14*be7064f8SJoseph Chen 15*be7064f8SJoseph Chen /* VD_NPU */ 16*be7064f8SJoseph Chen #define RK3568_PD_NPU 6 17*be7064f8SJoseph Chen 18*be7064f8SJoseph Chen /* VD_GPU */ 19*be7064f8SJoseph Chen #define RK3568_PD_GPU 7 20*be7064f8SJoseph Chen 21*be7064f8SJoseph Chen /* VD_LOGIC */ 22*be7064f8SJoseph Chen #define RK3568_PD_VI 8 23*be7064f8SJoseph Chen #define RK3568_PD_VO 9 24*be7064f8SJoseph Chen #define RK3568_PD_RGA 10 25*be7064f8SJoseph Chen #define RK3568_PD_VPU 11 26*be7064f8SJoseph Chen #define RK3568_PD_CENTER 12 27*be7064f8SJoseph Chen #define RK3568_PD_RKVDEC 13 28*be7064f8SJoseph Chen #define RK3568_PD_RKVENC 14 29*be7064f8SJoseph Chen #define RK3568_PD_PIPE 15 30*be7064f8SJoseph Chen #define RK3568_PD_LOGIC_ALIVE 16 31*be7064f8SJoseph Chen 32*be7064f8SJoseph Chen #endif 33