1*56f7d184SJoseph Chen /* SPDX-License-Identifier: GPL-2.0 */ 2*56f7d184SJoseph Chen #ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__ 3*56f7d184SJoseph Chen #define __DT_BINDINGS_POWER_RK3562_POWER_H__ 4*56f7d184SJoseph Chen 5*56f7d184SJoseph Chen /* VD_CORE */ 6*56f7d184SJoseph Chen #define RK3562_PD_CPU_0 0 7*56f7d184SJoseph Chen #define RK3562_PD_CPU_1 1 8*56f7d184SJoseph Chen #define RK3562_PD_CPU_2 2 9*56f7d184SJoseph Chen #define RK3562_PD_CPU_3 3 10*56f7d184SJoseph Chen #define RK3562_PD_CORE_ALIVE 4 11*56f7d184SJoseph Chen 12*56f7d184SJoseph Chen /* VD_PMU */ 13*56f7d184SJoseph Chen #define RK3562_PD_PMU 5 14*56f7d184SJoseph Chen #define RK3562_PD_PMU_ALIVE 6 15*56f7d184SJoseph Chen 16*56f7d184SJoseph Chen /* VD_NPU */ 17*56f7d184SJoseph Chen #define RK3562_PD_NPU 7 18*56f7d184SJoseph Chen 19*56f7d184SJoseph Chen /* VD_GPU */ 20*56f7d184SJoseph Chen #define RK3562_PD_GPU 8 21*56f7d184SJoseph Chen 22*56f7d184SJoseph Chen /* VD_LOGIC */ 23*56f7d184SJoseph Chen #define RK3562_PD_DDR 9 24*56f7d184SJoseph Chen #define RK3562_PD_VEPU 10 25*56f7d184SJoseph Chen #define RK3562_PD_VDPU 11 26*56f7d184SJoseph Chen #define RK3562_PD_VI 12 27*56f7d184SJoseph Chen #define RK3562_PD_VO 13 28*56f7d184SJoseph Chen #define RK3562_PD_RGA 14 29*56f7d184SJoseph Chen #define RK3562_PD_EBK 15 30*56f7d184SJoseph Chen #define RK3562_PD_PHP 16 31*56f7d184SJoseph Chen #define RK3562_PD_LOGIC_ALIVE 17 32*56f7d184SJoseph Chen 33*56f7d184SJoseph Chen #endif 34